LXR uboot/arch/mips/include/asm/byteorder.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (C) 1996, 99, 2003 by Ralf Baechle
   4 */
   5#ifndef _ASM_BYTEORDER_H
   6#define _ASM_BYTEORDER_H
   7
   8#include <asm/types.h>
   9
  10#ifdef __GNUC__
  11
  12#ifdef CONFIG_CPU_MIPSR2
  13
  14static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
  15{
  16        __asm__(
  17        "       wsbh    %0, %1                  \n"
  18        : "=r" (x)
  19        : "r" (x));
  20
  21        return x;
  22}
  23#define __arch__swab16(x)       ___arch__swab16(x)
  24
  25static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
  26{
  27        __asm__(
  28        "       wsbh    %0, %1                  \n"
  29        "       rotr    %0, %0, 16              \n"
  30        : "=r" (x)
  31        : "r" (x));
  32
  33        return x;
  34}
  35#define __arch__swab32(x)       ___arch__swab32(x)
  36
  37#ifdef CONFIG_CPU_MIPS64_R2
  38
  39static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
  40{
  41        __asm__(
  42        "       dsbh    %0, %1                  \n"
  43        "       dshd    %0, %0                  \n"
  44        "       drotr   %0, %0, 32              \n"
  45        : "=r" (x)
  46        : "r" (x));
  47
  48        return x;
  49}
  50
  51#define __arch__swab64(x)       ___arch__swab64(x)
  52
  53#endif /* CONFIG_CPU_MIPS64_R2 */
  54
  55#endif /* CONFIG_CPU_MIPSR2 */
  56
  57#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
  58#  define __BYTEORDER_HAS_U64__
  59#  define __SWAB_64_THRU_32__
  60#endif
  61
  62#endif /* __GNUC__ */
  63
  64#if defined(__MIPSEB__)
  65#  include <linux/byteorder/big_endian.h>
  66#elif defined(__MIPSEL__)
  67#  include <linux/byteorder/little_endian.h>
  68#else
  69#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
  70#endif
  71
  72#endif /* _ASM_BYTEORDER_H */
  73