1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2018-2022 Marvell International Ltd. 4 * 5 * Configuration and status register (CSR) type definitions for 6 * Octeon npei. 7 */ 8 9#ifndef __CVMX_NPEI_DEFS_H__ 10#define __CVMX_NPEI_DEFS_H__ 11 12#define CVMX_NPEI_BAR1_INDEXX(offset) \ 13 (0x0000000000000000ull + ((offset) & 31) * 16) 14#define CVMX_NPEI_BIST_STATUS (0x0000000000000580ull) 15#define CVMX_NPEI_BIST_STATUS2 (0x0000000000000680ull) 16#define CVMX_NPEI_CTL_PORT0 (0x0000000000000250ull) 17#define CVMX_NPEI_CTL_PORT1 (0x0000000000000260ull) 18#define CVMX_NPEI_CTL_STATUS (0x0000000000000570ull) 19#define CVMX_NPEI_CTL_STATUS2 (0x0000000000003C00ull) 20#define CVMX_NPEI_DATA_OUT_CNT (0x00000000000005F0ull) 21#define CVMX_NPEI_DBG_DATA (0x0000000000000510ull) 22#define CVMX_NPEI_DBG_SELECT (0x0000000000000500ull) 23#define CVMX_NPEI_DMA0_INT_LEVEL (0x00000000000005C0ull) 24#define CVMX_NPEI_DMA1_INT_LEVEL (0x00000000000005D0ull) 25#define CVMX_NPEI_DMAX_COUNTS(offset) \ 26 (0x0000000000000450ull + ((offset) & 7) * 16) 27#define CVMX_NPEI_DMAX_DBELL(offset) (0x00000000000003B0ull + ((offset) & 7) * 16) 28#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \ 29 (0x0000000000000400ull + ((offset) & 7) * 16) 30#define CVMX_NPEI_DMAX_NADDR(offset) (0x00000000000004A0ull + ((offset) & 7) * 16) 31#define CVMX_NPEI_DMA_CNTS (0x00000000000005E0ull) 32#define CVMX_NPEI_DMA_CONTROL (0x00000000000003A0ull) 33#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x00000000000005B0ull) 34#define CVMX_NPEI_DMA_STATE1 (0x00000000000006C0ull) 35#define CVMX_NPEI_DMA_STATE1_P1 (0x0000000000000680ull) 36#define CVMX_NPEI_DMA_STATE2 (0x00000000000006D0ull) 37#define CVMX_NPEI_DMA_STATE2_P1 (0x0000000000000690ull) 38#define CVMX_NPEI_DMA_STATE3_P1 (0x00000000000006A0ull) 39#define CVMX_NPEI_DMA_STATE4_P1 (0x00000000000006B0ull) 40#define CVMX_NPEI_DMA_STATE5_P1 (0x00000000000006C0ull) 41#define CVMX_NPEI_INT_A_ENB (0x0000000000000560ull) 42#define CVMX_NPEI_INT_A_ENB2 (0x0000000000003CE0ull) 43#define CVMX_NPEI_INT_A_SUM (0x0000000000000550ull) 44#define CVMX_NPEI_INT_ENB (0x0000000000000540ull) 45#define CVMX_NPEI_INT_ENB2 (0x0000000000003CD0ull) 46#define CVMX_NPEI_INT_INFO (0x0000000000000590ull) 47#define CVMX_NPEI_INT_SUM (0x0000000000000530ull) 48#define CVMX_NPEI_INT_SUM2 (0x0000000000003CC0ull) 49#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull) 50#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull) 51#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull) 52#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \ 53 (0x0000000000000280ull + ((offset) & 31) * 16 - 16 * 12) 54#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull) 55#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull) 56#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull) 57#define CVMX_NPEI_MSI_ENB3 (0x0000000000003C80ull) 58#define CVMX_NPEI_MSI_RCV0 (0x0000000000003C10ull) 59#define CVMX_NPEI_MSI_RCV1 (0x0000000000003C20ull) 60#define CVMX_NPEI_MSI_RCV2 (0x0000000000003C30ull) 61#define CVMX_NPEI_MSI_RCV3 (0x0000000000003C40ull) 62#define CVMX_NPEI_MSI_RD_MAP (0x0000000000003CA0ull) 63#define CVMX_NPEI_MSI_W1C_ENB0 (0x0000000000003CF0ull) 64#define CVMX_NPEI_MSI_W1C_ENB1 (0x0000000000003D00ull) 65#define CVMX_NPEI_MSI_W1C_ENB2 (0x0000000000003D10ull) 66#define CVMX_NPEI_MSI_W1C_ENB3 (0x0000000000003D20ull) 67#define CVMX_NPEI_MSI_W1S_ENB0 (0x0000000000003D30ull) 68#define CVMX_NPEI_MSI_W1S_ENB1 (0x0000000000003D40ull) 69#define CVMX_NPEI_MSI_W1S_ENB2 (0x0000000000003D50ull) 70#define CVMX_NPEI_MSI_W1S_ENB3 (0x0000000000003D60ull) 71#define CVMX_NPEI_MSI_WR_MAP (0x0000000000003C90ull) 72#define CVMX_NPEI_PCIE_CREDIT_CNT (0x0000000000003D70ull) 73#define CVMX_NPEI_PCIE_MSI_RCV (0x0000000000003CB0ull) 74#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0000000000000650ull) 75#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0000000000000660ull) 76#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x0000000000000670ull) 77#define CVMX_NPEI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16) 78#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \ 79 (0x0000000000002800ull + ((offset) & 31) * 16) 80#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \ 81 (0x0000000000002C00ull + ((offset) & 31) * 16) 82#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \ 83 (0x0000000000003000ull + ((offset) & 31) * 16) 84#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \ 85 (0x0000000000003400ull + ((offset) & 31) * 16) 86#define CVMX_NPEI_PKTX_IN_BP(offset) \ 87 (0x0000000000003800ull + ((offset) & 31) * 16) 88#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \ 89 (0x0000000000001400ull + ((offset) & 31) * 16) 90#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \ 91 (0x0000000000001800ull + ((offset) & 31) * 16) 92#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \ 93 (0x0000000000001C00ull + ((offset) & 31) * 16) 94#define CVMX_NPEI_PKT_CNT_INT (0x0000000000001110ull) 95#define CVMX_NPEI_PKT_CNT_INT_ENB (0x0000000000001130ull) 96#define CVMX_NPEI_PKT_DATA_OUT_ES (0x00000000000010B0ull) 97#define CVMX_NPEI_PKT_DATA_OUT_NS (0x00000000000010A0ull) 98#define CVMX_NPEI_PKT_DATA_OUT_ROR (0x0000000000001090ull) 99#define CVMX_NPEI_PKT_DPADDR (0x0000000000001080ull) 100#define CVMX_NPEI_PKT_INPUT_CONTROL (0x0000000000001150ull) 101#define CVMX_NPEI_PKT_INSTR_ENB (0x0000000000001000ull) 102#define CVMX_NPEI_PKT_INSTR_RD_SIZE (0x0000000000001190ull) 103#define CVMX_NPEI_PKT_INSTR_SIZE (0x0000000000001020ull) 104#define CVMX_NPEI_PKT_INT_LEVELS (0x0000000000001100ull) 105#define CVMX_NPEI_PKT_IN_BP (0x00000000000006B0ull) 106#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \ 107 (0x0000000000002000ull + ((offset) & 31) * 16) 108#define CVMX_NPEI_PKT_IN_INSTR_COUNTS (0x00000000000006A0ull) 109#define CVMX_NPEI_PKT_IN_PCIE_PORT (0x00000000000011A0ull) 110#define CVMX_NPEI_PKT_IPTR (0x0000000000001070ull) 111#define CVMX_NPEI_PKT_OUTPUT_WMARK (0x0000000000001160ull) 112#define CVMX_NPEI_PKT_OUT_BMODE (0x00000000000010D0ull) 113#define CVMX_NPEI_PKT_OUT_ENB (0x0000000000001010ull) 114#define CVMX_NPEI_PKT_PCIE_PORT (0x00000000000010E0ull) 115#define CVMX_NPEI_PKT_PORT_IN_RST (0x0000000000000690ull) 116#define CVMX_NPEI_PKT_SLIST_ES (0x0000000000001050ull) 117#define CVMX_NPEI_PKT_SLIST_ID_SIZE (0x0000000000001180ull) 118#define CVMX_NPEI_PKT_SLIST_NS (0x0000000000001040ull) 119#define CVMX_NPEI_PKT_SLIST_ROR (0x0000000000001030ull) 120#define CVMX_NPEI_PKT_TIME_INT (0x0000000000001120ull) 121#define CVMX_NPEI_PKT_TIME_INT_ENB (0x0000000000001140ull) 122#define CVMX_NPEI_RSL_INT_BLOCKS (0x0000000000000520ull) 123#define CVMX_NPEI_SCRATCH_1 (0x0000000000000270ull) 124#define CVMX_NPEI_STATE1 (0x0000000000000620ull) 125#define CVMX_NPEI_STATE2 (0x0000000000000630ull) 126#define CVMX_NPEI_STATE3 (0x0000000000000640ull) 127#define CVMX_NPEI_WINDOW_CTL (0x0000000000000380ull) 128#define CVMX_NPEI_WIN_RD_ADDR (0x0000000000000210ull) 129#define CVMX_NPEI_WIN_RD_DATA (0x0000000000000240ull) 130#define CVMX_NPEI_WIN_WR_ADDR (0x0000000000000200ull) 131#define CVMX_NPEI_WIN_WR_DATA (0x0000000000000220ull) 132#define CVMX_NPEI_WIN_WR_MASK (0x0000000000000230ull) 133 134/** 135 * cvmx_npei_bar1_index# 136 * 137 * Total Address is 16Kb; 0x0000 - 0x3fff, 0x000 - 0x7fe(Reg, every other 8B) 138 * 139 * General 5kb; 0x0000 - 0x13ff, 0x000 - 0x27e(Reg-General) 140 * PktMem 10Kb; 0x1400 - 0x3bff, 0x280 - 0x77e(Reg-General-Packet) 141 * Rsvd 1Kb; 0x3c00 - 0x3fff, 0x780 - 0x7fe(Reg-NCB Only Mode) 142 * == NPEI_PKT_CNT_INT_ENB[PORT] 143 * == NPEI_PKT_TIME_INT_ENB[PORT] 144 * == NPEI_PKT_CNT_INT[PORT] 145 * == NPEI_PKT_TIME_INT[PORT] 146 * == NPEI_PKT_PCIE_PORT[PP] 147 * == NPEI_PKT_SLIST_ROR[ROR] 148 * == NPEI_PKT_SLIST_ROR[NSR] ? 149 * == NPEI_PKT_SLIST_ES[ES] 150 * == NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 151 * == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 152 * == NPEI_PKTn_CNTS[CNT] 153 * NPEI_CTL_STATUS[OUTn_ENB] == NPEI_PKT_OUT_ENB[ENB] 154 * NPEI_BASE_ADDRESS_OUTPUTn[BADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] 155 * NPEI_DESC_OUTPUTn[SIZE] == NPEI_PKTn_SLIST_FIFO_RSIZE[RSIZE] 156 * NPEI_Pn_DBPAIR_ADDR[NADDR] == NPEI_PKTn_SLIST_BADDR[ADDR] + 157 * NPEI_PKTn_SLIST_BAOFF_DBELL[AOFF] 158 * NPEI_PKT_CREDITSn[PTR_CNT] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 159 * NPEI_P0_PAIR_CNTS[AVAIL] == NPEI_PKTn_SLIST_BAOFF_DBELL[DBELL] 160 * NPEI_P0_PAIR_CNTS[FCNT] == 161 * NPEI_PKTS_SENTn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 162 * NPEI_OUTPUT_CONTROL[Pn_BMODE] == NPEI_PKT_OUT_BMODE[BMODE] 163 * NPEI_PKT_CREDITSn[PKT_CNT] == NPEI_PKTn_CNTS[CNT] 164 * NPEI_BUFF_SIZE_OUTPUTn[BSIZE] == NPEI_PKT_SLIST_ID_SIZE[BSIZE] 165 * NPEI_BUFF_SIZE_OUTPUTn[ISIZE] == NPEI_PKT_SLIST_ID_SIZE[ISIZE] 166 * NPEI_OUTPUT_CONTROL[On_CSRM] == NPEI_PKT_DPADDR[DPTR] & 167 * NPEI_PKT_OUT_USE_IPTR[PORT] 168 * NPEI_OUTPUT_CONTROL[On_ES] == NPEI_PKT_DATA_OUT_ES[ES] 169 * NPEI_OUTPUT_CONTROL[On_NS] == NPEI_PKT_DATA_OUT_NS[NSR] ? 170 * NPEI_OUTPUT_CONTROL[On_RO] == NPEI_PKT_DATA_OUT_ROR[ROR] 171 * NPEI_PKTS_SENT_INT_LEVn[PKT_CNT] == NPEI_PKT_INT_LEVELS[CNT] 172 * NPEI_PKTS_SENT_TIMEn[PKT_TIME] == NPEI_PKT_INT_LEVELS[TIME] 173 * NPEI_OUTPUT_CONTROL[IPTR_On] == NPEI_PKT_IPTR[IPTR] 174 * NPEI_PCIE_PORT_OUTPUT[] == NPEI_PKT_PCIE_PORT[PP] 175 * 176 * NPEI_BAR1_INDEXX = NPEI BAR1 IndexX Register 177 * 178 * Contains address index and control bits for access to memory ranges of 179 * BAR-1. Index is build from supplied address [25:22]. 180 * NPEI_BAR1_INDEX0 through NPEI_BAR1_INDEX15 is used for transactions 181 * orginating with PCIE-PORT0 and NPEI_BAR1_INDEX16 182 * through NPEI_BAR1_INDEX31 is used for transactions originating with 183 * PCIE-PORT1. 184 */ 185union cvmx_npei_bar1_indexx { 186 u32 u32; 187 struct cvmx_npei_bar1_indexx_s { 188 u32 reserved_18_31 : 14; 189 u32 addr_idx : 14; 190 u32 ca : 1; 191 u32 end_swp : 2; 192 u32 addr_v : 1; 193 } s; 194 struct cvmx_npei_bar1_indexx_s cn52xx; 195 struct cvmx_npei_bar1_indexx_s cn52xxp1; 196 struct cvmx_npei_bar1_indexx_s cn56xx; 197 struct cvmx_npei_bar1_indexx_s cn56xxp1; 198}; 199 200typedef union cvmx_npei_bar1_indexx cvmx_npei_bar1_indexx_t; 201 202/** 203 * cvmx_npei_bist_status 204 * 205 * NPEI_BIST_STATUS = NPI's BIST Status Register 206 * 207 * Results from BIST runs of NPEI's memories. 208 */ 209union cvmx_npei_bist_status { 210 u64 u64; 211 struct cvmx_npei_bist_status_s { 212 u64 pkt_rdf : 1; 213 u64 reserved_60_62 : 3; 214 u64 pcr_gim : 1; 215 u64 pkt_pif : 1; 216 u64 pcsr_int : 1; 217 u64 pcsr_im : 1; 218 u64 pcsr_cnt : 1; 219 u64 pcsr_id : 1; 220 u64 pcsr_sl : 1; 221 u64 reserved_50_52 : 3; 222 u64 pkt_ind : 1; 223 u64 pkt_slm : 1; 224 u64 reserved_36_47 : 12; 225 u64 d0_pst : 1; 226 u64 d1_pst : 1; 227 u64 d2_pst : 1; 228 u64 d3_pst : 1; 229 u64 reserved_31_31 : 1; 230 u64 n2p0_c : 1; 231 u64 n2p0_o : 1; 232 u64 n2p1_c : 1; 233 u64 n2p1_o : 1; 234 u64 cpl_p0 : 1; 235 u64 cpl_p1 : 1; 236 u64 p2n1_po : 1; 237 u64 p2n1_no : 1; 238 u64 p2n1_co : 1; 239 u64 p2n0_po : 1; 240 u64 p2n0_no : 1; 241 u64 p2n0_co : 1; 242 u64 p2n0_c0 : 1; 243 u64 p2n0_c1 : 1; 244 u64 p2n0_n : 1; 245 u64 p2n0_p0 : 1; 246 u64 p2n0_p1 : 1; 247 u64 p2n1_c0 : 1; 248 u64 p2n1_c1 : 1; 249 u64 p2n1_n : 1; 250 u64 p2n1_p0 : 1; 251 u64 p2n1_p1 : 1; 252 u64 csm0 : 1; 253 u64 csm1 : 1; 254 u64 dif0 : 1; 255 u64 dif1 : 1; 256 u64 dif2 : 1; 257 u64 dif3 : 1; 258 u64 reserved_2_2 : 1; 259 u64 msi : 1; 260 u64 ncb_cmd : 1; 261 } s; 262 struct cvmx_npei_bist_status_cn52xx { 263 u64 pkt_rdf : 1; 264 u64 reserved_60_62 : 3; 265 u64 pcr_gim : 1; 266 u64 pkt_pif : 1; 267 u64 pcsr_int : 1; 268 u64 pcsr_im : 1; 269 u64 pcsr_cnt : 1; 270 u64 pcsr_id : 1; 271 u64 pcsr_sl : 1; 272 u64 pkt_imem : 1; 273 u64 pkt_pfm : 1; 274 u64 pkt_pof : 1; 275 u64 reserved_48_49 : 2; 276 u64 pkt_pop0 : 1; 277 u64 pkt_pop1 : 1; 278 u64 d0_mem : 1; 279 u64 d1_mem : 1; 280 u64 d2_mem : 1; 281 u64 d3_mem : 1; 282 u64 d4_mem : 1; 283 u64 ds_mem : 1; 284 u64 reserved_36_39 : 4; 285 u64 d0_pst : 1; 286 u64 d1_pst : 1; 287 u64 d2_pst : 1; 288 u64 d3_pst : 1; 289 u64 d4_pst : 1; 290 u64 n2p0_c : 1; 291 u64 n2p0_o : 1; 292 u64 n2p1_c : 1; 293 u64 n2p1_o : 1; 294 u64 cpl_p0 : 1; 295 u64 cpl_p1 : 1; 296 u64 p2n1_po : 1; 297 u64 p2n1_no : 1; 298 u64 p2n1_co : 1; 299 u64 p2n0_po : 1; 300 u64 p2n0_no : 1; 301 u64 p2n0_co : 1; 302 u64 p2n0_c0 : 1; 303 u64 p2n0_c1 : 1; 304 u64 p2n0_n : 1; 305 u64 p2n0_p0 : 1; 306 u64 p2n0_p1 : 1; 307 u64 p2n1_c0 : 1; 308 u64 p2n1_c1 : 1; 309 u64 p2n1_n : 1; 310 u64 p2n1_p0 : 1; 311 u64 p2n1_p1 : 1; 312 u64 csm0 : 1; 313 u64 csm1 : 1; 314 u64 dif0 : 1; 315 u64 dif1 : 1; 316 u64 dif2 : 1; 317 u64 dif3 : 1; 318 u64 dif4 : 1; 319 u64 msi : 1; 320 u64 ncb_cmd : 1; 321 } cn52xx; 322 struct cvmx_npei_bist_status_cn52xxp1 { 323 u64 reserved_46_63 : 18; 324 u64 d0_mem0 : 1; 325 u64 d1_mem1 : 1; 326 u64 d2_mem2 : 1; 327 u64 d3_mem3 : 1; 328 u64 dr0_mem : 1; 329 u64 d0_mem : 1; 330 u64 d1_mem : 1; 331 u64 d2_mem : 1; 332 u64 d3_mem : 1; 333 u64 dr1_mem : 1; 334 u64 d0_pst : 1; 335 u64 d1_pst : 1; 336 u64 d2_pst : 1; 337 u64 d3_pst : 1; 338 u64 dr2_mem : 1; 339 u64 n2p0_c : 1; 340 u64 n2p0_o : 1; 341 u64 n2p1_c : 1; 342 u64 n2p1_o : 1; 343 u64 cpl_p0 : 1; 344 u64 cpl_p1 : 1; 345 u64 p2n1_po : 1; 346 u64 p2n1_no : 1; 347 u64 p2n1_co : 1; 348 u64 p2n0_po : 1; 349 u64 p2n0_no : 1; 350 u64 p2n0_co : 1; 351 u64 p2n0_c0 : 1; 352 u64 p2n0_c1 : 1; 353 u64 p2n0_n : 1; 354 u64 p2n0_p0 : 1; 355 u64 p2n0_p1 : 1; 356 u64 p2n1_c0 : 1; 357 u64 p2n1_c1 : 1; 358 u64 p2n1_n : 1; 359 u64 p2n1_p0 : 1; 360 u64 p2n1_p1 : 1; 361 u64 csm0 : 1; 362 u64 csm1 : 1; 363 u64 dif0 : 1; 364 u64 dif1 : 1; 365 u64 dif2 : 1; 366 u64 dif3 : 1; 367 u64 dr3_mem : 1; 368 u64 msi : 1; 369 u64 ncb_cmd : 1; 370 } cn52xxp1; 371 struct cvmx_npei_bist_status_cn52xx cn56xx; 372 struct cvmx_npei_bist_status_cn56xxp1 { 373 u64 reserved_58_63 : 6; 374 u64 pcsr_int : 1; 375 u64 pcsr_im : 1; 376 u64 pcsr_cnt : 1; 377 u64 pcsr_id : 1; 378 u64 pcsr_sl : 1; 379 u64 pkt_pout : 1; 380 u64 pkt_imem : 1; 381 u64 pkt_cntm : 1; 382 u64 pkt_ind : 1; 383 u64 pkt_slm : 1; 384 u64 pkt_odf : 1; 385 u64 pkt_oif : 1; 386 u64 pkt_out : 1; 387 u64 pkt_i0 : 1; 388 u64 pkt_i1 : 1; 389 u64 pkt_s0 : 1; 390 u64 pkt_s1 : 1; 391 u64 d0_mem : 1; 392 u64 d1_mem : 1; 393 u64 d2_mem : 1; 394 u64 d3_mem : 1; 395 u64 d4_mem : 1; 396 u64 d0_pst : 1; 397 u64 d1_pst : 1; 398 u64 d2_pst : 1; 399 u64 d3_pst : 1; 400 u64 d4_pst : 1; 401 u64 n2p0_c : 1; 402 u64 n2p0_o : 1; 403 u64 n2p1_c : 1; 404 u64 n2p1_o : 1; 405 u64 cpl_p0 : 1; 406 u64 cpl_p1 : 1; 407 u64 p2n1_po : 1; 408 u64 p2n1_no : 1; 409 u64 p2n1_co : 1; 410 u64 p2n0_po : 1; 411 u64 p2n0_no : 1; 412 u64 p2n0_co : 1; 413 u64 p2n0_c0 : 1; 414 u64 p2n0_c1 : 1; 415 u64 p2n0_n : 1; 416 u64 p2n0_p0 : 1; 417 u64 p2n0_p1 : 1; 418 u64 p2n1_c0 : 1; 419 u64 p2n1_c1 : 1; 420 u64 p2n1_n : 1; 421 u64 p2n1_p0 : 1; 422 u64 p2n1_p1 : 1; 423 u64 csm0 : 1; 424 u64 csm1 : 1; 425 u64 dif0 : 1; 426 u64 dif1 : 1; 427 u64 dif2 : 1; 428 u64 dif3 : 1; 429 u64 dif4 : 1; 430 u64 msi : 1; 431 u64 ncb_cmd : 1; 432 } cn56xxp1; 433}; 434 435typedef union cvmx_npei_bist_status cvmx_npei_bist_status_t; 436 437/** 438 * cvmx_npei_bist_status2 439 * 440 * NPEI_BIST_STATUS2 = NPI's BIST Status Register2 441 * 442 * Results from BIST runs of NPEI's memories. 443 */ 444union cvmx_npei_bist_status2 { 445 u64 u64; 446 struct cvmx_npei_bist_status2_s { 447 u64 reserved_14_63 : 50; 448 u64 prd_tag : 1; 449 u64 prd_st0 : 1; 450 u64 prd_st1 : 1; 451 u64 prd_err : 1; 452 u64 nrd_st : 1; 453 u64 nwe_st : 1; 454 u64 nwe_wr0 : 1; 455 u64 nwe_wr1 : 1; 456 u64 pkt_rd : 1; 457 u64 psc_p0 : 1; 458 u64 psc_p1 : 1; 459 u64 pkt_gd : 1; 460 u64 pkt_gl : 1; 461 u64 pkt_blk : 1; 462 } s; 463 struct cvmx_npei_bist_status2_s cn52xx; 464 struct cvmx_npei_bist_status2_s cn56xx; 465}; 466 467typedef union cvmx_npei_bist_status2 cvmx_npei_bist_status2_t; 468 469/** 470 * cvmx_npei_ctl_port0 471 * 472 * NPEI_CTL_PORT0 = NPEI's Control Port 0 473 * 474 * Contains control for access for Port0 475 */ 476union cvmx_npei_ctl_port0 { 477 u64 u64; 478 struct cvmx_npei_ctl_port0_s { 479 u64 reserved_21_63 : 43; 480 u64 waitl_com : 1; 481 u64 intd : 1; 482 u64 intc : 1; 483 u64 intb : 1; 484 u64 inta : 1; 485 u64 intd_map : 2; 486 u64 intc_map : 2; 487 u64 intb_map : 2; 488 u64 inta_map : 2; 489 u64 ctlp_ro : 1; 490 u64 reserved_6_6 : 1; 491 u64 ptlp_ro : 1; 492 u64 bar2_enb : 1; 493 u64 bar2_esx : 2; 494 u64 bar2_cax : 1; 495 u64 wait_com : 1; 496 } s; 497 struct cvmx_npei_ctl_port0_s cn52xx; 498 struct cvmx_npei_ctl_port0_s cn52xxp1; 499 struct cvmx_npei_ctl_port0_s cn56xx; 500 struct cvmx_npei_ctl_port0_s cn56xxp1; 501}; 502 503typedef union cvmx_npei_ctl_port0 cvmx_npei_ctl_port0_t; 504 505/** 506 * cvmx_npei_ctl_port1 507 * 508 * NPEI_CTL_PORT1 = NPEI's Control Port1 509 * 510 * Contains control for access for Port1 511 */ 512union cvmx_npei_ctl_port1 { 513 u64 u64; 514 struct cvmx_npei_ctl_port1_s { 515 u64 reserved_21_63 : 43; 516 u64 waitl_com : 1; 517 u64 intd : 1; 518 u64 intc : 1; 519 u64 intb : 1; 520 u64 inta : 1; 521 u64 intd_map : 2; 522 u64 intc_map : 2; 523 u64 intb_map : 2; 524 u64 inta_map : 2; 525 u64 ctlp_ro : 1; 526 u64 reserved_6_6 : 1; 527 u64 ptlp_ro : 1; 528 u64 bar2_enb : 1; 529 u64 bar2_esx : 2; 530 u64 bar2_cax : 1; 531 u64 wait_com : 1; 532 } s; 533 struct cvmx_npei_ctl_port1_s cn52xx; 534 struct cvmx_npei_ctl_port1_s cn52xxp1; 535 struct cvmx_npei_ctl_port1_s cn56xx; 536 struct cvmx_npei_ctl_port1_s cn56xxp1; 537}; 538 539typedef union cvmx_npei_ctl_port1 cvmx_npei_ctl_port1_t; 540 541/** 542 * cvmx_npei_ctl_status 543 * 544 * NPEI_CTL_STATUS = NPEI Control Status Register 545 * 546 * Contains control and status for NPEI. Writes to this register are not 547 * oSrdered with writes/reads to the PCIe Memory space. 548 * To ensure that a write has completed the user must read the register 549 * before making an access(i.e. PCIe memory space) 550 * that requires the value of this register to be updated. 551 */ 552union cvmx_npei_ctl_status { 553 u64 u64; 554 struct cvmx_npei_ctl_status_s { 555 u64 reserved_44_63 : 20; 556 u64 p1_ntags : 6; 557 u64 p0_ntags : 6; 558 u64 cfg_rtry : 16; 559 u64 ring_en : 1; 560 u64 lnk_rst : 1; 561 u64 arb : 1; 562 u64 pkt_bp : 4; 563 u64 host_mode : 1; 564 u64 chip_rev : 8; 565 } s; 566 struct cvmx_npei_ctl_status_s cn52xx; 567 struct cvmx_npei_ctl_status_cn52xxp1 { 568 u64 reserved_44_63 : 20; 569 u64 p1_ntags : 6; 570 u64 p0_ntags : 6; 571 u64 cfg_rtry : 16; 572 u64 reserved_15_15 : 1; 573 u64 lnk_rst : 1; 574 u64 arb : 1; 575 u64 reserved_9_12 : 4; 576 u64 host_mode : 1; 577 u64 chip_rev : 8; 578 } cn52xxp1; 579 struct cvmx_npei_ctl_status_s cn56xx; 580 struct cvmx_npei_ctl_status_cn56xxp1 { 581 u64 reserved_15_63 : 49; 582 u64 lnk_rst : 1; 583 u64 arb : 1; 584 u64 pkt_bp : 4; 585 u64 host_mode : 1; 586 u64 chip_rev : 8; 587 } cn56xxp1; 588}; 589 590typedef union cvmx_npei_ctl_status cvmx_npei_ctl_status_t; 591 592/** 593 * cvmx_npei_ctl_status2 594 * 595 * NPEI_CTL_STATUS2 = NPEI's Control Status2 Register 596 * 597 * Contains control and status for NPEI. 598 * Writes to this register are not ordered with writes/reads to the PCI 599 * Memory space. 600 * To ensure that a write has completed the user must read the register before 601 * making an access(i.e. PCI memory space) that requires the value of this 602 * register to be updated. 603 */ 604union cvmx_npei_ctl_status2 { 605 u64 u64; 606 struct cvmx_npei_ctl_status2_s { 607 u64 reserved_16_63 : 48; 608 u64 mps : 1; 609 u64 mrrs : 3; 610 u64 c1_w_flt : 1; 611 u64 c0_w_flt : 1; 612 u64 c1_b1_s : 3; 613 u64 c0_b1_s : 3; 614 u64 c1_wi_d : 1; 615 u64 c1_b0_d : 1; 616 u64 c0_wi_d : 1; 617 u64 c0_b0_d : 1; 618 } s; 619 struct cvmx_npei_ctl_status2_s cn52xx; 620 struct cvmx_npei_ctl_status2_s cn52xxp1; 621 struct cvmx_npei_ctl_status2_s cn56xx; 622 struct cvmx_npei_ctl_status2_s cn56xxp1; 623}; 624 625typedef union cvmx_npei_ctl_status2 cvmx_npei_ctl_status2_t; 626 627/** 628 * cvmx_npei_data_out_cnt 629 * 630 * NPEI_DATA_OUT_CNT = NPEI DATA OUT COUNT 631 * 632 * The EXEC data out fifo-count and the data unload counter. 633 */ 634union cvmx_npei_data_out_cnt { 635 u64 u64; 636 struct cvmx_npei_data_out_cnt_s { 637 u64 reserved_44_63 : 20; 638 u64 p1_ucnt : 16; 639 u64 p1_fcnt : 6; 640 u64 p0_ucnt : 16; 641 u64 p0_fcnt : 6; 642 } s; 643 struct cvmx_npei_data_out_cnt_s cn52xx; 644 struct cvmx_npei_data_out_cnt_s cn52xxp1; 645 struct cvmx_npei_data_out_cnt_s cn56xx; 646 struct cvmx_npei_data_out_cnt_s cn56xxp1; 647}; 648 649typedef union cvmx_npei_data_out_cnt cvmx_npei_data_out_cnt_t; 650 651/** 652 * cvmx_npei_dbg_data 653 * 654 * NPEI_DBG_DATA = NPEI Debug Data Register 655 * 656 * Value returned on the debug-data lines from the RSLs 657 */ 658union cvmx_npei_dbg_data { 659 u64 u64; 660 struct cvmx_npei_dbg_data_s { 661 u64 reserved_28_63 : 36; 662 u64 qlm0_rev_lanes : 1; 663 u64 reserved_25_26 : 2; 664 u64 qlm1_spd : 2; 665 u64 c_mul : 5; 666 u64 dsel_ext : 1; 667 u64 data : 17; 668 } s; 669 struct cvmx_npei_dbg_data_cn52xx { 670 u64 reserved_29_63 : 35; 671 u64 qlm0_link_width : 1; 672 u64 qlm0_rev_lanes : 1; 673 u64 qlm1_mode : 2; 674 u64 qlm1_spd : 2; 675 u64 c_mul : 5; 676 u64 dsel_ext : 1; 677 u64 data : 17; 678 } cn52xx; 679 struct cvmx_npei_dbg_data_cn52xx cn52xxp1; 680 struct cvmx_npei_dbg_data_cn56xx { 681 u64 reserved_29_63 : 35; 682 u64 qlm2_rev_lanes : 1; 683 u64 qlm0_rev_lanes : 1; 684 u64 qlm3_spd : 2; 685 u64 qlm1_spd : 2; 686 u64 c_mul : 5; 687 u64 dsel_ext : 1; 688 u64 data : 17; 689 } cn56xx; 690 struct cvmx_npei_dbg_data_cn56xx cn56xxp1; 691}; 692 693typedef union cvmx_npei_dbg_data cvmx_npei_dbg_data_t; 694 695/** 696 * cvmx_npei_dbg_select 697 * 698 * NPEI_DBG_SELECT = Debug Select Register 699 * 700 * Contains the debug select value last written to the RSLs. 701 */ 702union cvmx_npei_dbg_select { 703 u64 u64; 704 struct cvmx_npei_dbg_select_s { 705 u64 reserved_16_63 : 48; 706 u64 dbg_sel : 16; 707 } s; 708 struct cvmx_npei_dbg_select_s cn52xx; 709 struct cvmx_npei_dbg_select_s cn52xxp1; 710 struct cvmx_npei_dbg_select_s cn56xx; 711 struct cvmx_npei_dbg_select_s cn56xxp1; 712}; 713 714typedef union cvmx_npei_dbg_select cvmx_npei_dbg_select_t; 715 716/** 717 * cvmx_npei_dma#_counts 718 * 719 * NPEI_DMA[0..4]_COUNTS = DMA Instruction Counts 720 * 721 * Values for determing the number of instructions for DMA[0..4] in the NPEI. 722 */ 723union cvmx_npei_dmax_counts { 724 u64 u64; 725 struct cvmx_npei_dmax_counts_s { 726 u64 reserved_39_63 : 25; 727 u64 fcnt : 7; 728 u64 dbell : 32; 729 } s; 730 struct cvmx_npei_dmax_counts_s cn52xx; 731 struct cvmx_npei_dmax_counts_s cn52xxp1; 732 struct cvmx_npei_dmax_counts_s cn56xx; 733 struct cvmx_npei_dmax_counts_s cn56xxp1; 734}; 735 736typedef union cvmx_npei_dmax_counts cvmx_npei_dmax_counts_t; 737 738/** 739 * cvmx_npei_dma#_dbell 740 * 741 * NPEI_DMA_DBELL[0..4] = DMA Door Bell 742 * 743 * The door bell register for DMA[0..4] queue. 744 */ 745union cvmx_npei_dmax_dbell { 746 u32 u32; 747 struct cvmx_npei_dmax_dbell_s { 748 u32 reserved_16_31 : 16; 749 u32 dbell : 16; 750 } s; 751 struct cvmx_npei_dmax_dbell_s cn52xx; 752 struct cvmx_npei_dmax_dbell_s cn52xxp1; 753 struct cvmx_npei_dmax_dbell_s cn56xx; 754 struct cvmx_npei_dmax_dbell_s cn56xxp1; 755}; 756 757typedef union cvmx_npei_dmax_dbell cvmx_npei_dmax_dbell_t; 758 759/** 760 * cvmx_npei_dma#_ibuff_saddr 761 * 762 * NPEI_DMA[0..4]_IBUFF_SADDR = DMA Instruction Buffer Starting Address 763 * 764 * The address to start reading Instructions from for DMA[0..4]. 765 */ 766union cvmx_npei_dmax_ibuff_saddr { 767 u64 u64; 768 struct cvmx_npei_dmax_ibuff_saddr_s { 769 u64 reserved_37_63 : 27; 770 u64 idle : 1; 771 u64 saddr : 29; 772 u64 reserved_0_6 : 7; 773 } s; 774 struct cvmx_npei_dmax_ibuff_saddr_s cn52xx; 775 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 { 776 u64 reserved_36_63 : 28; 777 u64 saddr : 29; 778 u64 reserved_0_6 : 7; 779 } cn52xxp1; 780 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx; 781 struct cvmx_npei_dmax_ibuff_saddr_cn52xxp1 cn56xxp1; 782}; 783 784typedef union cvmx_npei_dmax_ibuff_saddr cvmx_npei_dmax_ibuff_saddr_t; 785 786/** 787 * cvmx_npei_dma#_naddr 788 * 789 * NPEI_DMA[0..4]_NADDR = DMA Next Ichunk Address 790 * 791 * Place NPEI will read the next Ichunk data from. This is valid when state is 0 792 */ 793union cvmx_npei_dmax_naddr { 794 u64 u64; 795 struct cvmx_npei_dmax_naddr_s { 796 u64 reserved_36_63 : 28; 797 u64 addr : 36; 798 } s; 799 struct cvmx_npei_dmax_naddr_s cn52xx; 800 struct cvmx_npei_dmax_naddr_s cn52xxp1; 801 struct cvmx_npei_dmax_naddr_s cn56xx; 802 struct cvmx_npei_dmax_naddr_s cn56xxp1; 803}; 804 805typedef union cvmx_npei_dmax_naddr cvmx_npei_dmax_naddr_t; 806 807/** 808 * cvmx_npei_dma0_int_level 809 * 810 * NPEI_DMA0_INT_LEVEL = NPEI DMA0 Interrupt Level 811 * 812 * Thresholds for DMA count and timer interrupts for DMA0. 813 */ 814union cvmx_npei_dma0_int_level { 815 u64 u64; 816 struct cvmx_npei_dma0_int_level_s { 817 u64 time : 32; 818 u64 cnt : 32; 819 } s; 820 struct cvmx_npei_dma0_int_level_s cn52xx; 821 struct cvmx_npei_dma0_int_level_s cn52xxp1; 822 struct cvmx_npei_dma0_int_level_s cn56xx; 823 struct cvmx_npei_dma0_int_level_s cn56xxp1; 824}; 825 826typedef union cvmx_npei_dma0_int_level cvmx_npei_dma0_int_level_t; 827 828/** 829 * cvmx_npei_dma1_int_level 830 * 831 * NPEI_DMA1_INT_LEVEL = NPEI DMA1 Interrupt Level 832 * 833 * Thresholds for DMA count and timer interrupts for DMA1. 834 */ 835union cvmx_npei_dma1_int_level { 836 u64 u64; 837 struct cvmx_npei_dma1_int_level_s { 838 u64 time : 32; 839 u64 cnt : 32; 840 } s; 841 struct cvmx_npei_dma1_int_level_s cn52xx; 842 struct cvmx_npei_dma1_int_level_s cn52xxp1; 843 struct cvmx_npei_dma1_int_level_s cn56xx; 844 struct cvmx_npei_dma1_int_level_s cn56xxp1; 845}; 846 847typedef union cvmx_npei_dma1_int_level cvmx_npei_dma1_int_level_t; 848 849/** 850 * cvmx_npei_dma_cnts 851 * 852 * NPEI_DMA_CNTS = NPEI DMA Count 853 * 854 * The DMA Count values for DMA0 and DMA1. 855 */ 856union cvmx_npei_dma_cnts { 857 u64 u64; 858 struct cvmx_npei_dma_cnts_s { 859 u64 dma1 : 32; 860 u64 dma0 : 32; 861 } s; 862 struct cvmx_npei_dma_cnts_s cn52xx; 863 struct cvmx_npei_dma_cnts_s cn52xxp1; 864 struct cvmx_npei_dma_cnts_s cn56xx; 865 struct cvmx_npei_dma_cnts_s cn56xxp1; 866}; 867 868typedef union cvmx_npei_dma_cnts cvmx_npei_dma_cnts_t; 869 870/** 871 * cvmx_npei_dma_control 872 * 873 * NPEI_DMA_CONTROL = DMA Control Register 874 * 875 * Controls operation of the DMA IN/OUT. 876 */ 877union cvmx_npei_dma_control { 878 u64 u64; 879 struct cvmx_npei_dma_control_s { 880 u64 reserved_40_63 : 24; 881 u64 p_32b_m : 1; 882 u64 dma4_enb : 1; 883 u64 dma3_enb : 1; 884 u64 dma2_enb : 1; 885 u64 dma1_enb : 1; 886 u64 dma0_enb : 1; 887 u64 b0_lend : 1; 888 u64 dwb_denb : 1; 889 u64 dwb_ichk : 9; 890 u64 fpa_que : 3; 891 u64 o_add1 : 1; 892 u64 o_ro : 1; 893 u64 o_ns : 1; 894 u64 o_es : 2; 895 u64 o_mode : 1; 896 u64 csize : 14; 897 } s; 898 struct cvmx_npei_dma_control_s cn52xx; 899 struct cvmx_npei_dma_control_cn52xxp1 { 900 u64 reserved_38_63 : 26; 901 u64 dma3_enb : 1; 902 u64 dma2_enb : 1; 903 u64 dma1_enb : 1; 904 u64 dma0_enb : 1; 905 u64 b0_lend : 1; 906 u64 dwb_denb : 1; 907 u64 dwb_ichk : 9; 908 u64 fpa_que : 3; 909 u64 o_add1 : 1; 910 u64 o_ro : 1; 911 u64 o_ns : 1; 912 u64 o_es : 2; 913 u64 o_mode : 1; 914 u64 csize : 14; 915 } cn52xxp1; 916 struct cvmx_npei_dma_control_s cn56xx; 917 struct cvmx_npei_dma_control_cn56xxp1 { 918 u64 reserved_39_63 : 25; 919 u64 dma4_enb : 1; 920 u64 dma3_enb : 1; 921 u64 dma2_enb : 1; 922 u64 dma1_enb : 1; 923 u64 dma0_enb : 1; 924 u64 b0_lend : 1; 925 u64 dwb_denb : 1; 926 u64 dwb_ichk : 9; 927 u64 fpa_que : 3; 928 u64 o_add1 : 1; 929 u64 o_ro : 1; 930 u64 o_ns : 1; 931 u64 o_es : 2; 932 u64 o_mode : 1; 933 u64 csize : 14; 934 } cn56xxp1; 935}; 936 937typedef union cvmx_npei_dma_control cvmx_npei_dma_control_t; 938 939/** 940 * cvmx_npei_dma_pcie_req_num 941 * 942 * NPEI_DMA_PCIE_REQ_NUM = NPEI DMA PCIE Outstanding Read Request Number 943 * 944 * Outstanding PCIE read request number for DMAs and Packet, maximum number 945 * is 16 946 */ 947union cvmx_npei_dma_pcie_req_num { 948 u64 u64; 949 struct cvmx_npei_dma_pcie_req_num_s { 950 u64 dma_arb : 1; 951 u64 reserved_53_62 : 10; 952 u64 pkt_cnt : 5; 953 u64 reserved_45_47 : 3; 954 u64 dma4_cnt : 5; 955 u64 reserved_37_39 : 3; 956 u64 dma3_cnt : 5; 957 u64 reserved_29_31 : 3; 958 u64 dma2_cnt : 5; 959 u64 reserved_21_23 : 3; 960 u64 dma1_cnt : 5; 961 u64 reserved_13_15 : 3; 962 u64 dma0_cnt : 5; 963 u64 reserved_5_7 : 3; 964 u64 dma_cnt : 5; 965 } s; 966 struct cvmx_npei_dma_pcie_req_num_s cn52xx; 967 struct cvmx_npei_dma_pcie_req_num_s cn56xx; 968}; 969 970typedef union cvmx_npei_dma_pcie_req_num cvmx_npei_dma_pcie_req_num_t; 971 972/** 973 * cvmx_npei_dma_state1 974 * 975 * NPEI_DMA_STATE1 = NPI's DMA State 1 976 * 977 * Results from DMA state register 1 978 */ 979union cvmx_npei_dma_state1 { 980 u64 u64; 981 struct cvmx_npei_dma_state1_s { 982 u64 reserved_40_63 : 24; 983 u64 d4_dwe : 8; 984 u64 d3_dwe : 8; 985 u64 d2_dwe : 8; 986 u64 d1_dwe : 8; 987 u64 d0_dwe : 8; 988 } s; 989 struct cvmx_npei_dma_state1_s cn52xx; 990}; 991 992typedef union cvmx_npei_dma_state1 cvmx_npei_dma_state1_t; 993 994/** 995 * cvmx_npei_dma_state1_p1 996 * 997 * NPEI_DMA_STATE1_P1 = NPEI DMA Request and Instruction State 998 * 999 * DMA engine Debug information. 1000 */
1001union cvmx_npei_dma_state1_p1 { 1002 u64 u64; 1003 struct cvmx_npei_dma_state1_p1_s { 1004 u64 reserved_60_63 : 4; 1005 u64 d0_difst : 7; 1006 u64 d1_difst : 7; 1007 u64 d2_difst : 7; 1008 u64 d3_difst : 7; 1009 u64 d4_difst : 7; 1010 u64 d0_reqst : 5; 1011 u64 d1_reqst : 5; 1012 u64 d2_reqst : 5; 1013 u64 d3_reqst : 5; 1014 u64 d4_reqst : 5; 1015 } s; 1016 struct cvmx_npei_dma_state1_p1_cn52xxp1 { 1017 u64 reserved_60_63 : 4; 1018 u64 d0_difst : 7; 1019 u64 d1_difst : 7; 1020 u64 d2_difst : 7; 1021 u64 d3_difst : 7; 1022 u64 reserved_25_31 : 7; 1023 u64 d0_reqst : 5; 1024 u64 d1_reqst : 5; 1025 u64 d2_reqst : 5; 1026 u64 d3_reqst : 5; 1027 u64 reserved_0_4 : 5; 1028 } cn52xxp1; 1029 struct cvmx_npei_dma_state1_p1_s cn56xxp1; 1030}; 1031 1032typedef union cvmx_npei_dma_state1_p1 cvmx_npei_dma_state1_p1_t; 1033 1034/** 1035 * cvmx_npei_dma_state2 1036 * 1037 * NPEI_DMA_STATE2 = NPI's DMA State 2 1038 * 1039 * Results from DMA state register 2 1040 */ 1041union cvmx_npei_dma_state2 { 1042 u64 u64; 1043 struct cvmx_npei_dma_state2_s { 1044 u64 reserved_28_63 : 36; 1045 u64 ndwe : 4; 1046 u64 reserved_21_23 : 3; 1047 u64 ndre : 5; 1048 u64 reserved_10_15 : 6; 1049 u64 prd : 10; 1050 } s; 1051 struct cvmx_npei_dma_state2_s cn52xx; 1052}; 1053 1054typedef union cvmx_npei_dma_state2 cvmx_npei_dma_state2_t; 1055 1056/** 1057 * cvmx_npei_dma_state2_p1 1058 * 1059 * NPEI_DMA_STATE2_P1 = NPEI DMA Instruction Fetch State 1060 * 1061 * DMA engine Debug information. 1062 */ 1063union cvmx_npei_dma_state2_p1 { 1064 u64 u64; 1065 struct cvmx_npei_dma_state2_p1_s { 1066 u64 reserved_45_63 : 19; 1067 u64 d0_dffst : 9; 1068 u64 d1_dffst : 9; 1069 u64 d2_dffst : 9; 1070 u64 d3_dffst : 9; 1071 u64 d4_dffst : 9; 1072 } s; 1073 struct cvmx_npei_dma_state2_p1_cn52xxp1 { 1074 u64 reserved_45_63 : 19; 1075 u64 d0_dffst : 9; 1076 u64 d1_dffst : 9; 1077 u64 d2_dffst : 9; 1078 u64 d3_dffst : 9; 1079 u64 reserved_0_8 : 9; 1080 } cn52xxp1; 1081 struct cvmx_npei_dma_state2_p1_s cn56xxp1; 1082}; 1083 1084typedef union cvmx_npei_dma_state2_p1 cvmx_npei_dma_state2_p1_t; 1085 1086/** 1087 * cvmx_npei_dma_state3_p1 1088 * 1089 * NPEI_DMA_STATE3_P1 = NPEI DMA DRE State 1090 * 1091 * DMA engine Debug information. 1092 */ 1093union cvmx_npei_dma_state3_p1 { 1094 u64 u64; 1095 struct cvmx_npei_dma_state3_p1_s { 1096 u64 reserved_60_63 : 4; 1097 u64 d0_drest : 15; 1098 u64 d1_drest : 15; 1099 u64 d2_drest : 15; 1100 u64 d3_drest : 15; 1101 } s; 1102 struct cvmx_npei_dma_state3_p1_s cn52xxp1; 1103 struct cvmx_npei_dma_state3_p1_s cn56xxp1; 1104}; 1105 1106typedef union cvmx_npei_dma_state3_p1 cvmx_npei_dma_state3_p1_t; 1107 1108/** 1109 * cvmx_npei_dma_state4_p1 1110 * 1111 * NPEI_DMA_STATE4_P1 = NPEI DMA DWE State 1112 * 1113 * DMA engine Debug information. 1114 */ 1115union cvmx_npei_dma_state4_p1 { 1116 u64 u64; 1117 struct cvmx_npei_dma_state4_p1_s { 1118 u64 reserved_52_63 : 12; 1119 u64 d0_dwest : 13; 1120 u64 d1_dwest : 13; 1121 u64 d2_dwest : 13; 1122 u64 d3_dwest : 13; 1123 } s; 1124 struct cvmx_npei_dma_state4_p1_s cn52xxp1; 1125 struct cvmx_npei_dma_state4_p1_s cn56xxp1; 1126}; 1127 1128typedef union cvmx_npei_dma_state4_p1 cvmx_npei_dma_state4_p1_t; 1129 1130/** 1131 * cvmx_npei_dma_state5_p1 1132 * 1133 * NPEI_DMA_STATE5_P1 = NPEI DMA DWE and DRE State 1134 * 1135 * DMA engine Debug information. 1136 */ 1137union cvmx_npei_dma_state5_p1 { 1138 u64 u64; 1139 struct cvmx_npei_dma_state5_p1_s { 1140 u64 reserved_28_63 : 36; 1141 u64 d4_drest : 15; 1142 u64 d4_dwest : 13; 1143 } s; 1144 struct cvmx_npei_dma_state5_p1_s cn56xxp1; 1145}; 1146 1147typedef union cvmx_npei_dma_state5_p1 cvmx_npei_dma_state5_p1_t; 1148 1149/** 1150 * cvmx_npei_int_a_enb 1151 * 1152 * NPEI_INTERRUPT_A_ENB = NPI's Interrupt A Enable Register 1153 * 1154 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe 1155 * CoresUsed to enable the various interrupting conditions of NPEI 1156 */ 1157union cvmx_npei_int_a_enb { 1158 u64 u64; 1159 struct cvmx_npei_int_a_enb_s { 1160 u64 reserved_10_63 : 54; 1161 u64 pout_err : 1; 1162 u64 pin_bp : 1; 1163 u64 p1_rdlk : 1; 1164 u64 p0_rdlk : 1; 1165 u64 pgl_err : 1; 1166 u64 pdi_err : 1; 1167 u64 pop_err : 1; 1168 u64 pins_err : 1; 1169 u64 dma1_cpl : 1; 1170 u64 dma0_cpl : 1; 1171 } s; 1172 struct cvmx_npei_int_a_enb_s cn52xx; 1173 struct cvmx_npei_int_a_enb_cn52xxp1 { 1174 u64 reserved_2_63 : 62; 1175 u64 dma1_cpl : 1; 1176 u64 dma0_cpl : 1; 1177 } cn52xxp1; 1178 struct cvmx_npei_int_a_enb_s cn56xx; 1179}; 1180 1181typedef union cvmx_npei_int_a_enb cvmx_npei_int_a_enb_t; 1182 1183/** 1184 * cvmx_npei_int_a_enb2 1185 * 1186 * NPEI_INTERRUPT_A_ENB2 = NPEI's Interrupt A Enable2 Register 1187 * 1188 * Used to enable the various interrupting conditions of NPEI 1189 */ 1190union cvmx_npei_int_a_enb2 { 1191 u64 u64; 1192 struct cvmx_npei_int_a_enb2_s { 1193 u64 reserved_10_63 : 54; 1194 u64 pout_err : 1; 1195 u64 pin_bp : 1; 1196 u64 p1_rdlk : 1; 1197 u64 p0_rdlk : 1; 1198 u64 pgl_err : 1; 1199 u64 pdi_err : 1; 1200 u64 pop_err : 1; 1201 u64 pins_err : 1; 1202 u64 dma1_cpl : 1; 1203 u64 dma0_cpl : 1; 1204 } s; 1205 struct cvmx_npei_int_a_enb2_s cn52xx; 1206 struct cvmx_npei_int_a_enb2_cn52xxp1 { 1207 u64 reserved_2_63 : 62; 1208 u64 dma1_cpl : 1; 1209 u64 dma0_cpl : 1; 1210 } cn52xxp1; 1211 struct cvmx_npei_int_a_enb2_s cn56xx; 1212}; 1213 1214typedef union cvmx_npei_int_a_enb2 cvmx_npei_int_a_enb2_t; 1215 1216/** 1217 * cvmx_npei_int_a_sum 1218 * 1219 * NPEI_INTERRUPT_A_SUM = NPI Interrupt A Summary Register 1220 * 1221 * Set when an interrupt condition occurs, write '1' to clear. When an 1222 * interrupt bitin this register is set and 1223 * the cooresponding bit in the NPEI_INT_A_ENB register is set, then 1224 * NPEI_INT_SUM[61] will be set. 1225 */ 1226union cvmx_npei_int_a_sum { 1227 u64 u64; 1228 struct cvmx_npei_int_a_sum_s { 1229 u64 reserved_10_63 : 54; 1230 u64 pout_err : 1; 1231 u64 pin_bp : 1; 1232 u64 p1_rdlk : 1; 1233 u64 p0_rdlk : 1; 1234 u64 pgl_err : 1; 1235 u64 pdi_err : 1; 1236 u64 pop_err : 1; 1237 u64 pins_err : 1; 1238 u64 dma1_cpl : 1; 1239 u64 dma0_cpl : 1; 1240 } s; 1241 struct cvmx_npei_int_a_sum_s cn52xx; 1242 struct cvmx_npei_int_a_sum_cn52xxp1 { 1243 u64 reserved_2_63 : 62; 1244 u64 dma1_cpl : 1; 1245 u64 dma0_cpl : 1; 1246 } cn52xxp1; 1247 struct cvmx_npei_int_a_sum_s cn56xx; 1248}; 1249 1250typedef union cvmx_npei_int_a_sum cvmx_npei_int_a_sum_t; 1251 1252/** 1253 * cvmx_npei_int_enb 1254 * 1255 * NPEI_INTERRUPT_ENB = NPI's Interrupt Enable Register 1256 * 1257 * Used to allow the generation of interrupts (MSI/INTA) to the PCIe 1258 * CoresUsed to enable the various interrupting conditions of NPI 1259 */ 1260union cvmx_npei_int_enb { 1261 u64 u64; 1262 struct cvmx_npei_int_enb_s { 1263 u64 mio_inta : 1; 1264 u64 reserved_62_62 : 1; 1265 u64 int_a : 1; 1266 u64 c1_ldwn : 1; 1267 u64 c0_ldwn : 1; 1268 u64 c1_exc : 1; 1269 u64 c0_exc : 1; 1270 u64 c1_up_wf : 1; 1271 u64 c0_up_wf : 1; 1272 u64 c1_un_wf : 1; 1273 u64 c0_un_wf : 1; 1274 u64 c1_un_bx : 1; 1275 u64 c1_un_wi : 1; 1276 u64 c1_un_b2 : 1; 1277 u64 c1_un_b1 : 1; 1278 u64 c1_un_b0 : 1; 1279 u64 c1_up_bx : 1; 1280 u64 c1_up_wi : 1; 1281 u64 c1_up_b2 : 1; 1282 u64 c1_up_b1 : 1; 1283 u64 c1_up_b0 : 1; 1284 u64 c0_un_bx : 1; 1285 u64 c0_un_wi : 1; 1286 u64 c0_un_b2 : 1; 1287 u64 c0_un_b1 : 1; 1288 u64 c0_un_b0 : 1; 1289 u64 c0_up_bx : 1; 1290 u64 c0_up_wi : 1; 1291 u64 c0_up_b2 : 1; 1292 u64 c0_up_b1 : 1; 1293 u64 c0_up_b0 : 1; 1294 u64 c1_hpint : 1; 1295 u64 c1_pmei : 1; 1296 u64 c1_wake : 1; 1297 u64 crs1_dr : 1; 1298 u64 c1_se : 1; 1299 u64 crs1_er : 1; 1300 u64 c1_aeri : 1; 1301 u64 c0_hpint : 1; 1302 u64 c0_pmei : 1; 1303 u64 c0_wake : 1; 1304 u64 crs0_dr : 1; 1305 u64 c0_se : 1; 1306 u64 crs0_er : 1; 1307 u64 c0_aeri : 1; 1308 u64 ptime : 1; 1309 u64 pcnt : 1; 1310 u64 pidbof : 1; 1311 u64 psldbof : 1; 1312 u64 dtime1 : 1; 1313 u64 dtime0 : 1; 1314 u64 dcnt1 : 1; 1315 u64 dcnt0 : 1; 1316 u64 dma1fi : 1; 1317 u64 dma0fi : 1; 1318 u64 dma4dbo : 1; 1319 u64 dma3dbo : 1; 1320 u64 dma2dbo : 1; 1321 u64 dma1dbo : 1; 1322 u64 dma0dbo : 1; 1323 u64 iob2big : 1; 1324 u64 bar0_to : 1; 1325 u64 rml_wto : 1; 1326 u64 rml_rto : 1; 1327 } s; 1328 struct cvmx_npei_int_enb_s cn52xx; 1329 struct cvmx_npei_int_enb_cn52xxp1 { 1330 u64 mio_inta : 1; 1331 u64 reserved_62_62 : 1; 1332 u64 int_a : 1; 1333 u64 c1_ldwn : 1; 1334 u64 c0_ldwn : 1; 1335 u64 c1_exc : 1; 1336 u64 c0_exc : 1; 1337 u64 c1_up_wf : 1; 1338 u64 c0_up_wf : 1; 1339 u64 c1_un_wf : 1; 1340 u64 c0_un_wf : 1; 1341 u64 c1_un_bx : 1; 1342 u64 c1_un_wi : 1; 1343 u64 c1_un_b2 : 1; 1344 u64 c1_un_b1 : 1; 1345 u64 c1_un_b0 : 1; 1346 u64 c1_up_bx : 1; 1347 u64 c1_up_wi : 1; 1348 u64 c1_up_b2 : 1; 1349 u64 c1_up_b1 : 1; 1350 u64 c1_up_b0 : 1; 1351 u64 c0_un_bx : 1; 1352 u64 c0_un_wi : 1; 1353 u64 c0_un_b2 : 1; 1354 u64 c0_un_b1 : 1; 1355 u64 c0_un_b0 : 1; 1356 u64 c0_up_bx : 1; 1357 u64 c0_up_wi : 1; 1358 u64 c0_up_b2 : 1; 1359 u64 c0_up_b1 : 1; 1360 u64 c0_up_b0 : 1; 1361 u64 c1_hpint : 1; 1362 u64 c1_pmei : 1; 1363 u64 c1_wake : 1; 1364 u64 crs1_dr : 1; 1365 u64 c1_se : 1; 1366 u64 crs1_er : 1; 1367 u64 c1_aeri : 1; 1368 u64 c0_hpint : 1; 1369 u64 c0_pmei : 1; 1370 u64 c0_wake : 1; 1371 u64 crs0_dr : 1; 1372 u64 c0_se : 1; 1373 u64 crs0_er : 1; 1374 u64 c0_aeri : 1; 1375 u64 ptime : 1; 1376 u64 pcnt : 1; 1377 u64 pidbof : 1; 1378 u64 psldbof : 1; 1379 u64 dtime1 : 1; 1380 u64 dtime0 : 1; 1381 u64 dcnt1 : 1; 1382 u64 dcnt0 : 1; 1383 u64 dma1fi : 1; 1384 u64 dma0fi : 1; 1385 u64 reserved_8_8 : 1; 1386 u64 dma3dbo : 1; 1387 u64 dma2dbo : 1; 1388 u64 dma1dbo : 1; 1389 u64 dma0dbo : 1; 1390 u64 iob2big : 1; 1391 u64 bar0_to : 1; 1392 u64 rml_wto : 1; 1393 u64 rml_rto : 1; 1394 } cn52xxp1; 1395 struct cvmx_npei_int_enb_s cn56xx; 1396 struct cvmx_npei_int_enb_cn56xxp1 { 1397 u64 mio_inta : 1; 1398 u64 reserved_61_62 : 2; 1399 u64 c1_ldwn : 1; 1400 u64 c0_ldwn : 1; 1401 u64 c1_exc : 1; 1402 u64 c0_exc : 1; 1403 u64 c1_up_wf : 1; 1404 u64 c0_up_wf : 1; 1405 u64 c1_un_wf : 1; 1406 u64 c0_un_wf : 1; 1407 u64 c1_un_bx : 1; 1408 u64 c1_un_wi : 1; 1409 u64 c1_un_b2 : 1; 1410 u64 c1_un_b1 : 1; 1411 u64 c1_un_b0 : 1; 1412 u64 c1_up_bx : 1; 1413 u64 c1_up_wi : 1; 1414 u64 c1_up_b2 : 1; 1415 u64 c1_up_b1 : 1; 1416 u64 c1_up_b0 : 1; 1417 u64 c0_un_bx : 1; 1418 u64 c0_un_wi : 1; 1419 u64 c0_un_b2 : 1; 1420 u64 c0_un_b1 : 1; 1421 u64 c0_un_b0 : 1; 1422 u64 c0_up_bx : 1; 1423 u64 c0_up_wi : 1; 1424 u64 c0_up_b2 : 1; 1425 u64 c0_up_b1 : 1; 1426 u64 c0_up_b0 : 1; 1427 u64 c1_hpint : 1; 1428 u64 c1_pmei : 1; 1429 u64 c1_wake : 1; 1430 u64 reserved_29_29 : 1; 1431 u64 c1_se : 1; 1432 u64 reserved_27_27 : 1; 1433 u64 c1_aeri : 1; 1434 u64 c0_hpint : 1; 1435 u64 c0_pmei : 1; 1436 u64 c0_wake : 1; 1437 u64 reserved_22_22 : 1; 1438 u64 c0_se : 1; 1439 u64 reserved_20_20 : 1; 1440 u64 c0_aeri : 1; 1441 u64 ptime : 1; 1442 u64 pcnt : 1; 1443 u64 pidbof : 1; 1444 u64 psldbof : 1; 1445 u64 dtime1 : 1; 1446 u64 dtime0 : 1; 1447 u64 dcnt1 : 1; 1448 u64 dcnt0 : 1; 1449 u64 dma1fi : 1; 1450 u64 dma0fi : 1; 1451 u64 dma4dbo : 1; 1452 u64 dma3dbo : 1; 1453 u64 dma2dbo : 1; 1454 u64 dma1dbo : 1; 1455 u64 dma0dbo : 1; 1456 u64 iob2big : 1; 1457 u64 bar0_to : 1; 1458 u64 rml_wto : 1; 1459 u64 rml_rto : 1; 1460 } cn56xxp1; 1461}; 1462 1463typedef union cvmx_npei_int_enb cvmx_npei_int_enb_t; 1464 1465/** 1466 * cvmx_npei_int_enb2 1467 * 1468 * NPEI_INTERRUPT_ENB2 = NPI's Interrupt Enable2 Register 1469 * 1470 * Used to enable the various interrupting conditions of NPI 1471 */ 1472union cvmx_npei_int_enb2 { 1473 u64 u64; 1474 struct cvmx_npei_int_enb2_s { 1475 u64 reserved_62_63 : 2; 1476 u64 int_a : 1; 1477 u64 c1_ldwn : 1; 1478 u64 c0_ldwn : 1; 1479 u64 c1_exc : 1; 1480 u64 c0_exc : 1; 1481 u64 c1_up_wf : 1; 1482 u64 c0_up_wf : 1; 1483 u64 c1_un_wf : 1; 1484 u64 c0_un_wf : 1; 1485 u64 c1_un_bx : 1; 1486 u64 c1_un_wi : 1; 1487 u64 c1_un_b2 : 1; 1488 u64 c1_un_b1 : 1; 1489 u64 c1_un_b0 : 1; 1490 u64 c1_up_bx : 1; 1491 u64 c1_up_wi : 1; 1492 u64 c1_up_b2 : 1; 1493 u64 c1_up_b1 : 1; 1494 u64 c1_up_b0 : 1; 1495 u64 c0_un_bx : 1; 1496 u64 c0_un_wi : 1; 1497 u64 c0_un_b2 : 1; 1498 u64 c0_un_b1 : 1; 1499 u64 c0_un_b0 : 1; 1500 u64 c0_up_bx : 1; 1501 u64 c0_up_wi : 1; 1502 u64 c0_up_b2 : 1; 1503 u64 c0_up_b1 : 1; 1504 u64 c0_up_b0 : 1; 1505 u64 c1_hpint : 1; 1506 u64 c1_pmei : 1; 1507 u64 c1_wake : 1; 1508 u64 crs1_dr : 1; 1509 u64 c1_se : 1; 1510 u64 crs1_er : 1; 1511 u64 c1_aeri : 1; 1512 u64 c0_hpint : 1; 1513 u64 c0_pmei : 1; 1514 u64 c0_wake : 1; 1515 u64 crs0_dr : 1; 1516 u64 c0_se : 1; 1517 u64 crs0_er : 1; 1518 u64 c0_aeri : 1; 1519 u64 ptime : 1; 1520 u64 pcnt : 1; 1521 u64 pidbof : 1; 1522 u64 psldbof : 1; 1523 u64 dtime1 : 1; 1524 u64 dtime0 : 1; 1525 u64 dcnt1 : 1; 1526 u64 dcnt0 : 1; 1527 u64 dma1fi : 1; 1528 u64 dma0fi : 1; 1529 u64 dma4dbo : 1; 1530 u64 dma3dbo : 1; 1531 u64 dma2dbo : 1; 1532 u64 dma1dbo : 1; 1533 u64 dma0dbo : 1; 1534 u64 iob2big : 1; 1535 u64 bar0_to : 1; 1536 u64 rml_wto : 1; 1537 u64 rml_rto : 1; 1538 } s; 1539 struct cvmx_npei_int_enb2_s cn52xx; 1540 struct cvmx_npei_int_enb2_cn52xxp1 { 1541 u64 reserved_62_63 : 2; 1542 u64 int_a : 1; 1543 u64 c1_ldwn : 1; 1544 u64 c0_ldwn : 1; 1545 u64 c1_exc : 1; 1546 u64 c0_exc : 1; 1547 u64 c1_up_wf : 1; 1548 u64 c0_up_wf : 1; 1549 u64 c1_un_wf : 1; 1550 u64 c0_un_wf : 1; 1551 u64 c1_un_bx : 1; 1552 u64 c1_un_wi : 1; 1553 u64 c1_un_b2 : 1; 1554 u64 c1_un_b1 : 1; 1555 u64 c1_un_b0 : 1; 1556 u64 c1_up_bx : 1; 1557 u64 c1_up_wi : 1; 1558 u64 c1_up_b2 : 1; 1559 u64 c1_up_b1 : 1; 1560 u64 c1_up_b0 : 1; 1561 u64 c0_un_bx : 1; 1562 u64 c0_un_wi : 1; 1563 u64 c0_un_b2 : 1; 1564 u64 c0_un_b1 : 1; 1565 u64 c0_un_b0 : 1; 1566 u64 c0_up_bx : 1; 1567 u64 c0_up_wi : 1; 1568 u64 c0_up_b2 : 1; 1569 u64 c0_up_b1 : 1; 1570 u64 c0_up_b0 : 1; 1571 u64 c1_hpint : 1; 1572 u64 c1_pmei : 1; 1573 u64 c1_wake : 1; 1574 u64 crs1_dr : 1; 1575 u64 c1_se : 1; 1576 u64 crs1_er : 1; 1577 u64 c1_aeri : 1; 1578 u64 c0_hpint : 1; 1579 u64 c0_pmei : 1; 1580 u64 c0_wake : 1; 1581 u64 crs0_dr : 1; 1582 u64 c0_se : 1; 1583 u64 crs0_er : 1; 1584 u64 c0_aeri : 1; 1585 u64 ptime : 1; 1586 u64 pcnt : 1; 1587 u64 pidbof : 1; 1588 u64 psldbof : 1; 1589 u64 dtime1 : 1; 1590 u64 dtime0 : 1; 1591 u64 dcnt1 : 1; 1592 u64 dcnt0 : 1; 1593 u64 dma1fi : 1; 1594 u64 dma0fi : 1; 1595 u64 reserved_8_8 : 1; 1596 u64 dma3dbo : 1; 1597 u64 dma2dbo : 1; 1598 u64 dma1dbo : 1; 1599 u64 dma0dbo : 1; 1600 u64 iob2big : 1; 1601 u64 bar0_to : 1; 1602 u64 rml_wto : 1; 1603 u64 rml_rto : 1; 1604 } cn52xxp1; 1605 struct cvmx_npei_int_enb2_s cn56xx; 1606 struct cvmx_npei_int_enb2_cn56xxp1 { 1607 u64 reserved_61_63 : 3; 1608 u64 c1_ldwn : 1; 1609 u64 c0_ldwn : 1; 1610 u64 c1_exc : 1; 1611 u64 c0_exc : 1; 1612 u64 c1_up_wf : 1; 1613 u64 c0_up_wf : 1; 1614 u64 c1_un_wf : 1; 1615 u64 c0_un_wf : 1; 1616 u64 c1_un_bx : 1; 1617 u64 c1_un_wi : 1; 1618 u64 c1_un_b2 : 1; 1619 u64 c1_un_b1 : 1; 1620 u64 c1_un_b0 : 1; 1621 u64 c1_up_bx : 1; 1622 u64 c1_up_wi : 1; 1623 u64 c1_up_b2 : 1; 1624 u64 c1_up_b1 : 1; 1625 u64 c1_up_b0 : 1; 1626 u64 c0_un_bx : 1; 1627 u64 c0_un_wi : 1; 1628 u64 c0_un_b2 : 1; 1629 u64 c0_un_b1 : 1; 1630 u64 c0_un_b0 : 1; 1631 u64 c0_up_bx : 1; 1632 u64 c0_up_wi : 1; 1633 u64 c0_up_b2 : 1; 1634 u64 c0_up_b1 : 1; 1635 u64 c0_up_b0 : 1; 1636 u64 c1_hpint : 1; 1637 u64 c1_pmei : 1; 1638 u64 c1_wake : 1; 1639 u64 reserved_29_29 : 1; 1640 u64 c1_se : 1; 1641 u64 reserved_27_27 : 1; 1642 u64 c1_aeri : 1; 1643 u64 c0_hpint : 1; 1644 u64 c0_pmei : 1; 1645 u64 c0_wake : 1; 1646 u64 reserved_22_22 : 1; 1647 u64 c0_se : 1; 1648 u64 reserved_20_20 : 1; 1649 u64 c0_aeri : 1; 1650 u64 ptime : 1; 1651 u64 pcnt : 1; 1652 u64 pidbof : 1; 1653 u64 psldbof : 1; 1654 u64 dtime1 : 1; 1655 u64 dtime0 : 1; 1656 u64 dcnt1 : 1; 1657 u64 dcnt0 : 1; 1658 u64 dma1fi : 1; 1659 u64 dma0fi : 1; 1660 u64 dma4dbo : 1; 1661 u64 dma3dbo : 1; 1662 u64 dma2dbo : 1; 1663 u64 dma1dbo : 1; 1664 u64 dma0dbo : 1; 1665 u64 iob2big : 1; 1666 u64 bar0_to : 1; 1667 u64 rml_wto : 1; 1668 u64 rml_rto : 1; 1669 } cn56xxp1; 1670}; 1671 1672typedef union cvmx_npei_int_enb2 cvmx_npei_int_enb2_t; 1673 1674/** 1675 * cvmx_npei_int_info 1676 * 1677 * NPEI_INT_INFO = NPI Interrupt Information 1678 * 1679 * Contains information about some of the interrupt condition that can occur 1680 * in the NPEI_INTERRUPT_SUM register. 1681 */ 1682union cvmx_npei_int_info { 1683 u64 u64; 1684 struct cvmx_npei_int_info_s { 1685 u64 reserved_12_63 : 52; 1686 u64 pidbof : 6; 1687 u64 psldbof : 6; 1688 } s; 1689 struct cvmx_npei_int_info_s cn52xx; 1690 struct cvmx_npei_int_info_s cn56xx; 1691 struct cvmx_npei_int_info_s cn56xxp1; 1692}; 1693 1694typedef union cvmx_npei_int_info cvmx_npei_int_info_t; 1695 1696/** 1697 * cvmx_npei_int_sum 1698 * 1699 * NPEI_INTERRUPT_SUM = NPI Interrupt Summary Register 1700 * 1701 * Set when an interrupt condition occurs, write '1' to clear. 1702 */ 1703union cvmx_npei_int_sum { 1704 u64 u64; 1705 struct cvmx_npei_int_sum_s { 1706 u64 mio_inta : 1; 1707 u64 reserved_62_62 : 1; 1708 u64 int_a : 1; 1709 u64 c1_ldwn : 1; 1710 u64 c0_ldwn : 1; 1711 u64 c1_exc : 1; 1712 u64 c0_exc : 1; 1713 u64 c1_up_wf : 1; 1714 u64 c0_up_wf : 1; 1715 u64 c1_un_wf : 1; 1716 u64 c0_un_wf : 1; 1717 u64 c1_un_bx : 1; 1718 u64 c1_un_wi : 1; 1719 u64 c1_un_b2 : 1; 1720 u64 c1_un_b1 : 1; 1721 u64 c1_un_b0 : 1; 1722 u64 c1_up_bx : 1; 1723 u64 c1_up_wi : 1; 1724 u64 c1_up_b2 : 1; 1725 u64 c1_up_b1 : 1; 1726 u64 c1_up_b0 : 1; 1727 u64 c0_un_bx : 1; 1728 u64 c0_un_wi : 1; 1729 u64 c0_un_b2 : 1; 1730 u64 c0_un_b1 : 1; 1731 u64 c0_un_b0 : 1; 1732 u64 c0_up_bx : 1; 1733 u64 c0_up_wi : 1; 1734 u64 c0_up_b2 : 1; 1735 u64 c0_up_b1 : 1; 1736 u64 c0_up_b0 : 1; 1737 u64 c1_hpint : 1; 1738 u64 c1_pmei : 1; 1739 u64 c1_wake : 1; 1740 u64 crs1_dr : 1; 1741 u64 c1_se : 1; 1742 u64 crs1_er : 1; 1743 u64 c1_aeri : 1; 1744 u64 c0_hpint : 1; 1745 u64 c0_pmei : 1; 1746 u64 c0_wake : 1; 1747 u64 crs0_dr : 1; 1748 u64 c0_se : 1; 1749 u64 crs0_er : 1; 1750 u64 c0_aeri : 1; 1751 u64 ptime : 1; 1752 u64 pcnt : 1; 1753 u64 pidbof : 1; 1754 u64 psldbof : 1; 1755 u64 dtime1 : 1; 1756 u64 dtime0 : 1; 1757 u64 dcnt1 : 1; 1758 u64 dcnt0 : 1; 1759 u64 dma1fi : 1; 1760 u64 dma0fi : 1; 1761 u64 dma4dbo : 1; 1762 u64 dma3dbo : 1; 1763 u64 dma2dbo : 1; 1764 u64 dma1dbo : 1; 1765 u64 dma0dbo : 1; 1766 u64 iob2big : 1; 1767 u64 bar0_to : 1; 1768 u64 rml_wto : 1; 1769 u64 rml_rto : 1; 1770 } s; 1771 struct cvmx_npei_int_sum_s cn52xx; 1772 struct cvmx_npei_int_sum_cn52xxp1 { 1773 u64 mio_inta : 1; 1774 u64 reserved_62_62 : 1; 1775 u64 int_a : 1; 1776 u64 c1_ldwn : 1; 1777 u64 c0_ldwn : 1; 1778 u64 c1_exc : 1; 1779 u64 c0_exc : 1; 1780 u64 c1_up_wf : 1; 1781 u64 c0_up_wf : 1; 1782 u64 c1_un_wf : 1; 1783 u64 c0_un_wf : 1; 1784 u64 c1_un_bx : 1; 1785 u64 c1_un_wi : 1; 1786 u64 c1_un_b2 : 1; 1787 u64 c1_un_b1 : 1; 1788 u64 c1_un_b0 : 1; 1789 u64 c1_up_bx : 1; 1790 u64 c1_up_wi : 1; 1791 u64 c1_up_b2 : 1; 1792 u64 c1_up_b1 : 1; 1793 u64 c1_up_b0 : 1; 1794 u64 c0_un_bx : 1; 1795 u64 c0_un_wi : 1; 1796 u64 c0_un_b2 : 1; 1797 u64 c0_un_b1 : 1; 1798 u64 c0_un_b0 : 1; 1799 u64 c0_up_bx : 1; 1800 u64 c0_up_wi : 1; 1801 u64 c0_up_b2 : 1; 1802 u64 c0_up_b1 : 1; 1803 u64 c0_up_b0 : 1; 1804 u64 c1_hpint : 1; 1805 u64 c1_pmei : 1; 1806 u64 c1_wake : 1; 1807 u64 crs1_dr : 1; 1808 u64 c1_se : 1; 1809 u64 crs1_er : 1; 1810 u64 c1_aeri : 1; 1811 u64 c0_hpint : 1; 1812 u64 c0_pmei : 1; 1813 u64 c0_wake : 1; 1814 u64 crs0_dr : 1; 1815 u64 c0_se : 1; 1816 u64 crs0_er : 1; 1817 u64 c0_aeri : 1; 1818 u64 reserved_15_18 : 4; 1819 u64 dtime1 : 1; 1820 u64 dtime0 : 1; 1821 u64 dcnt1 : 1; 1822 u64 dcnt0 : 1; 1823 u64 dma1fi : 1; 1824 u64 dma0fi : 1; 1825 u64 reserved_8_8 : 1; 1826 u64 dma3dbo : 1; 1827 u64 dma2dbo : 1; 1828 u64 dma1dbo : 1; 1829 u64 dma0dbo : 1; 1830 u64 iob2big : 1; 1831 u64 bar0_to : 1; 1832 u64 rml_wto : 1; 1833 u64 rml_rto : 1; 1834 } cn52xxp1; 1835 struct cvmx_npei_int_sum_s cn56xx; 1836 struct cvmx_npei_int_sum_cn56xxp1 { 1837 u64 mio_inta : 1; 1838 u64 reserved_61_62 : 2; 1839 u64 c1_ldwn : 1; 1840 u64 c0_ldwn : 1; 1841 u64 c1_exc : 1; 1842 u64 c0_exc : 1; 1843 u64 c1_up_wf : 1; 1844 u64 c0_up_wf : 1; 1845 u64 c1_un_wf : 1; 1846 u64 c0_un_wf : 1; 1847 u64 c1_un_bx : 1; 1848 u64 c1_un_wi : 1; 1849 u64 c1_un_b2 : 1; 1850 u64 c1_un_b1 : 1; 1851 u64 c1_un_b0 : 1; 1852 u64 c1_up_bx : 1; 1853 u64 c1_up_wi : 1; 1854 u64 c1_up_b2 : 1; 1855 u64 c1_up_b1 : 1; 1856 u64 c1_up_b0 : 1; 1857 u64 c0_un_bx : 1; 1858 u64 c0_un_wi : 1; 1859 u64 c0_un_b2 : 1; 1860 u64 c0_un_b1 : 1; 1861 u64 c0_un_b0 : 1; 1862 u64 c0_up_bx : 1; 1863 u64 c0_up_wi : 1; 1864 u64 c0_up_b2 : 1; 1865 u64 c0_up_b1 : 1; 1866 u64 c0_up_b0 : 1; 1867 u64 c1_hpint : 1; 1868 u64 c1_pmei : 1; 1869 u64 c1_wake : 1; 1870 u64 reserved_29_29 : 1; 1871 u64 c1_se : 1; 1872 u64 reserved_27_27 : 1; 1873 u64 c1_aeri : 1; 1874 u64 c0_hpint : 1; 1875 u64 c0_pmei : 1; 1876 u64 c0_wake : 1; 1877 u64 reserved_22_22 : 1; 1878 u64 c0_se : 1; 1879 u64 reserved_20_20 : 1; 1880 u64 c0_aeri : 1; 1881 u64 reserved_15_18 : 4; 1882 u64 dtime1 : 1; 1883 u64 dtime0 : 1; 1884 u64 dcnt1 : 1; 1885 u64 dcnt0 : 1; 1886 u64 dma1fi : 1; 1887 u64 dma0fi : 1; 1888 u64 dma4dbo : 1; 1889 u64 dma3dbo : 1; 1890 u64 dma2dbo : 1; 1891 u64 dma1dbo : 1; 1892 u64 dma0dbo : 1; 1893 u64 iob2big : 1; 1894 u64 bar0_to : 1; 1895 u64 rml_wto : 1; 1896 u64 rml_rto : 1; 1897 } cn56xxp1; 1898}; 1899 1900typedef union cvmx_npei_int_sum cvmx_npei_int_sum_t; 1901 1902/** 1903 * cvmx_npei_int_sum2 1904 * 1905 * NPEI_INTERRUPT_SUM2 = NPI Interrupt Summary2 Register 1906 * 1907 * This is a read only copy of the NPEI_INTERRUPT_SUM register with bit 1908 * variances. 1909 */ 1910union cvmx_npei_int_sum2 { 1911 u64 u64; 1912 struct cvmx_npei_int_sum2_s { 1913 u64 mio_inta : 1; 1914 u64 reserved_62_62 : 1; 1915 u64 int_a : 1; 1916 u64 c1_ldwn : 1; 1917 u64 c0_ldwn : 1; 1918 u64 c1_exc : 1; 1919 u64 c0_exc : 1; 1920 u64 c1_up_wf : 1; 1921 u64 c0_up_wf : 1; 1922 u64 c1_un_wf : 1; 1923 u64 c0_un_wf : 1; 1924 u64 c1_un_bx : 1; 1925 u64 c1_un_wi : 1; 1926 u64 c1_un_b2 : 1; 1927 u64 c1_un_b1 : 1; 1928 u64 c1_un_b0 : 1; 1929 u64 c1_up_bx : 1; 1930 u64 c1_up_wi : 1; 1931 u64 c1_up_b2 : 1; 1932 u64 c1_up_b1 : 1; 1933 u64 c1_up_b0 : 1; 1934 u64 c0_un_bx : 1; 1935 u64 c0_un_wi : 1; 1936 u64 c0_un_b2 : 1; 1937 u64 c0_un_b1 : 1; 1938 u64 c0_un_b0 : 1; 1939 u64 c0_up_bx : 1; 1940 u64 c0_up_wi : 1; 1941 u64 c0_up_b2 : 1; 1942 u64 c0_up_b1 : 1; 1943 u64 c0_up_b0 : 1; 1944 u64 c1_hpint : 1; 1945 u64 c1_pmei : 1; 1946 u64 c1_wake : 1; 1947 u64 crs1_dr : 1; 1948 u64 c1_se : 1; 1949 u64 crs1_er : 1; 1950 u64 c1_aeri : 1; 1951 u64 c0_hpint : 1; 1952 u64 c0_pmei : 1; 1953 u64 c0_wake : 1; 1954 u64 crs0_dr : 1; 1955 u64 c0_se : 1; 1956 u64 crs0_er : 1; 1957 u64 c0_aeri : 1; 1958 u64 reserved_15_18 : 4; 1959 u64 dtime1 : 1; 1960 u64 dtime0 : 1; 1961 u64 dcnt1 : 1; 1962 u64 dcnt0 : 1; 1963 u64 dma1fi : 1; 1964 u64 dma0fi : 1; 1965 u64 reserved_8_8 : 1; 1966 u64 dma3dbo : 1; 1967 u64 dma2dbo : 1; 1968 u64 dma1dbo : 1; 1969 u64 dma0dbo : 1; 1970 u64 iob2big : 1; 1971 u64 bar0_to : 1; 1972 u64 rml_wto : 1; 1973 u64 rml_rto : 1; 1974 } s; 1975 struct cvmx_npei_int_sum2_s cn52xx; 1976 struct cvmx_npei_int_sum2_s cn52xxp1; 1977 struct cvmx_npei_int_sum2_s cn56xx; 1978}; 1979 1980typedef union cvmx_npei_int_sum2 cvmx_npei_int_sum2_t; 1981 1982/** 1983 * cvmx_npei_last_win_rdata0 1984 * 1985 * NPEI_LAST_WIN_RDATA0 = NPEI Last Window Read Data Port0 1986 * 1987 * The data from the last initiated window read. 1988 */ 1989union cvmx_npei_last_win_rdata0 { 1990 u64 u64; 1991 struct cvmx_npei_last_win_rdata0_s { 1992 u64 data : 64; 1993 } s; 1994 struct cvmx_npei_last_win_rdata0_s cn52xx; 1995 struct cvmx_npei_last_win_rdata0_s cn52xxp1; 1996 struct cvmx_npei_last_win_rdata0_s cn56xx; 1997 struct cvmx_npei_last_win_rdata0_s cn56xxp1; 1998}; 1999 2000typedef union cvmx_npei_last_win_rdata0 cvmx_npei_last_win_rdata0_t;
2001 2002/** 2003 * cvmx_npei_last_win_rdata1 2004 * 2005 * NPEI_LAST_WIN_RDATA1 = NPEI Last Window Read Data Port1 2006 * 2007 * The data from the last initiated window read. 2008 */ 2009union cvmx_npei_last_win_rdata1 { 2010 u64 u64; 2011 struct cvmx_npei_last_win_rdata1_s { 2012 u64 data : 64; 2013 } s; 2014 struct cvmx_npei_last_win_rdata1_s cn52xx; 2015 struct cvmx_npei_last_win_rdata1_s cn52xxp1; 2016 struct cvmx_npei_last_win_rdata1_s cn56xx; 2017 struct cvmx_npei_last_win_rdata1_s cn56xxp1; 2018}; 2019 2020typedef union cvmx_npei_last_win_rdata1 cvmx_npei_last_win_rdata1_t; 2021 2022/** 2023 * cvmx_npei_mem_access_ctl 2024 * 2025 * NPEI_MEM_ACCESS_CTL = NPEI's Memory Access Control 2026 * 2027 * Contains control for access to the PCIe address space. 2028 */ 2029union cvmx_npei_mem_access_ctl { 2030 u64 u64; 2031 struct cvmx_npei_mem_access_ctl_s { 2032 u64 reserved_14_63 : 50; 2033 u64 max_word : 4; 2034 u64 timer : 10; 2035 } s; 2036 struct cvmx_npei_mem_access_ctl_s cn52xx; 2037 struct cvmx_npei_mem_access_ctl_s cn52xxp1; 2038 struct cvmx_npei_mem_access_ctl_s cn56xx; 2039 struct cvmx_npei_mem_access_ctl_s cn56xxp1; 2040}; 2041 2042typedef union cvmx_npei_mem_access_ctl cvmx_npei_mem_access_ctl_t; 2043 2044/** 2045 * cvmx_npei_mem_access_subid# 2046 * 2047 * NPEI_MEM_ACCESS_SUBIDX = NPEI Memory Access SubidX Register 2048 * 2049 * Contains address index and control bits for access to memory from Core PPs. 2050 */ 2051union cvmx_npei_mem_access_subidx { 2052 u64 u64; 2053 struct cvmx_npei_mem_access_subidx_s { 2054 u64 reserved_42_63 : 22; 2055 u64 zero : 1; 2056 u64 port : 2; 2057 u64 nmerge : 1; 2058 u64 esr : 2; 2059 u64 esw : 2; 2060 u64 nsr : 1; 2061 u64 nsw : 1; 2062 u64 ror : 1; 2063 u64 row : 1; 2064 u64 ba : 30; 2065 } s; 2066 struct cvmx_npei_mem_access_subidx_s cn52xx; 2067 struct cvmx_npei_mem_access_subidx_s cn52xxp1; 2068 struct cvmx_npei_mem_access_subidx_s cn56xx; 2069 struct cvmx_npei_mem_access_subidx_s cn56xxp1; 2070}; 2071 2072typedef union cvmx_npei_mem_access_subidx cvmx_npei_mem_access_subidx_t; 2073 2074/** 2075 * cvmx_npei_msi_enb0 2076 * 2077 * NPEI_MSI_ENB0 = NPEI MSI Enable0 2078 * 2079 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV0. 2080 */ 2081union cvmx_npei_msi_enb0 { 2082 u64 u64; 2083 struct cvmx_npei_msi_enb0_s { 2084 u64 enb : 64; 2085 } s; 2086 struct cvmx_npei_msi_enb0_s cn52xx; 2087 struct cvmx_npei_msi_enb0_s cn52xxp1; 2088 struct cvmx_npei_msi_enb0_s cn56xx; 2089 struct cvmx_npei_msi_enb0_s cn56xxp1; 2090}; 2091 2092typedef union cvmx_npei_msi_enb0 cvmx_npei_msi_enb0_t; 2093 2094/** 2095 * cvmx_npei_msi_enb1 2096 * 2097 * NPEI_MSI_ENB1 = NPEI MSI Enable1 2098 * 2099 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV1. 2100 */ 2101union cvmx_npei_msi_enb1 { 2102 u64 u64; 2103 struct cvmx_npei_msi_enb1_s { 2104 u64 enb : 64; 2105 } s; 2106 struct cvmx_npei_msi_enb1_s cn52xx; 2107 struct cvmx_npei_msi_enb1_s cn52xxp1; 2108 struct cvmx_npei_msi_enb1_s cn56xx; 2109 struct cvmx_npei_msi_enb1_s cn56xxp1; 2110}; 2111 2112typedef union cvmx_npei_msi_enb1 cvmx_npei_msi_enb1_t; 2113 2114/** 2115 * cvmx_npei_msi_enb2 2116 * 2117 * NPEI_MSI_ENB2 = NPEI MSI Enable2 2118 * 2119 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV2. 2120 */ 2121union cvmx_npei_msi_enb2 { 2122 u64 u64; 2123 struct cvmx_npei_msi_enb2_s { 2124 u64 enb : 64; 2125 } s; 2126 struct cvmx_npei_msi_enb2_s cn52xx; 2127 struct cvmx_npei_msi_enb2_s cn52xxp1; 2128 struct cvmx_npei_msi_enb2_s cn56xx; 2129 struct cvmx_npei_msi_enb2_s cn56xxp1; 2130}; 2131 2132typedef union cvmx_npei_msi_enb2 cvmx_npei_msi_enb2_t; 2133 2134/** 2135 * cvmx_npei_msi_enb3 2136 * 2137 * NPEI_MSI_ENB3 = NPEI MSI Enable3 2138 * 2139 * Used to enable the interrupt generation for the bits in the NPEI_MSI_RCV3. 2140 */ 2141union cvmx_npei_msi_enb3 { 2142 u64 u64; 2143 struct cvmx_npei_msi_enb3_s { 2144 u64 enb : 64; 2145 } s; 2146 struct cvmx_npei_msi_enb3_s cn52xx; 2147 struct cvmx_npei_msi_enb3_s cn52xxp1; 2148 struct cvmx_npei_msi_enb3_s cn56xx; 2149 struct cvmx_npei_msi_enb3_s cn56xxp1; 2150}; 2151 2152typedef union cvmx_npei_msi_enb3 cvmx_npei_msi_enb3_t; 2153 2154/** 2155 * cvmx_npei_msi_rcv0 2156 * 2157 * NPEI_MSI_RCV0 = NPEI MSI Receive0 2158 * 2159 * Contains bits [63:0] of the 256 bits oof MSI interrupts. 2160 */ 2161union cvmx_npei_msi_rcv0 { 2162 u64 u64; 2163 struct cvmx_npei_msi_rcv0_s { 2164 u64 intr : 64; 2165 } s; 2166 struct cvmx_npei_msi_rcv0_s cn52xx; 2167 struct cvmx_npei_msi_rcv0_s cn52xxp1; 2168 struct cvmx_npei_msi_rcv0_s cn56xx; 2169 struct cvmx_npei_msi_rcv0_s cn56xxp1; 2170}; 2171 2172typedef union cvmx_npei_msi_rcv0 cvmx_npei_msi_rcv0_t; 2173 2174/** 2175 * cvmx_npei_msi_rcv1 2176 * 2177 * NPEI_MSI_RCV1 = NPEI MSI Receive1 2178 * 2179 * Contains bits [127:64] of the 256 bits oof MSI interrupts. 2180 */ 2181union cvmx_npei_msi_rcv1 { 2182 u64 u64; 2183 struct cvmx_npei_msi_rcv1_s { 2184 u64 intr : 64; 2185 } s; 2186 struct cvmx_npei_msi_rcv1_s cn52xx; 2187 struct cvmx_npei_msi_rcv1_s cn52xxp1; 2188 struct cvmx_npei_msi_rcv1_s cn56xx; 2189 struct cvmx_npei_msi_rcv1_s cn56xxp1; 2190}; 2191 2192typedef union cvmx_npei_msi_rcv1 cvmx_npei_msi_rcv1_t; 2193 2194/** 2195 * cvmx_npei_msi_rcv2 2196 * 2197 * NPEI_MSI_RCV2 = NPEI MSI Receive2 2198 * 2199 * Contains bits [191:128] of the 256 bits oof MSI interrupts. 2200 */ 2201union cvmx_npei_msi_rcv2 { 2202 u64 u64; 2203 struct cvmx_npei_msi_rcv2_s { 2204 u64 intr : 64; 2205 } s; 2206 struct cvmx_npei_msi_rcv2_s cn52xx; 2207 struct cvmx_npei_msi_rcv2_s cn52xxp1; 2208 struct cvmx_npei_msi_rcv2_s cn56xx; 2209 struct cvmx_npei_msi_rcv2_s cn56xxp1; 2210}; 2211 2212typedef union cvmx_npei_msi_rcv2 cvmx_npei_msi_rcv2_t; 2213 2214/** 2215 * cvmx_npei_msi_rcv3 2216 * 2217 * NPEI_MSI_RCV3 = NPEI MSI Receive3 2218 * 2219 * Contains bits [255:192] of the 256 bits oof MSI interrupts. 2220 */ 2221union cvmx_npei_msi_rcv3 { 2222 u64 u64; 2223 struct cvmx_npei_msi_rcv3_s { 2224 u64 intr : 64; 2225 } s; 2226 struct cvmx_npei_msi_rcv3_s cn52xx; 2227 struct cvmx_npei_msi_rcv3_s cn52xxp1; 2228 struct cvmx_npei_msi_rcv3_s cn56xx; 2229 struct cvmx_npei_msi_rcv3_s cn56xxp1; 2230}; 2231 2232typedef union cvmx_npei_msi_rcv3 cvmx_npei_msi_rcv3_t; 2233 2234/** 2235 * cvmx_npei_msi_rd_map 2236 * 2237 * NPEI_MSI_RD_MAP = NPEI MSI Read MAP 2238 * 2239 * Used to read the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV 2240 * registers. 2241 */ 2242union cvmx_npei_msi_rd_map { 2243 u64 u64; 2244 struct cvmx_npei_msi_rd_map_s { 2245 u64 reserved_16_63 : 48; 2246 u64 rd_int : 8; 2247 u64 msi_int : 8; 2248 } s; 2249 struct cvmx_npei_msi_rd_map_s cn52xx; 2250 struct cvmx_npei_msi_rd_map_s cn52xxp1; 2251 struct cvmx_npei_msi_rd_map_s cn56xx; 2252 struct cvmx_npei_msi_rd_map_s cn56xxp1; 2253}; 2254 2255typedef union cvmx_npei_msi_rd_map cvmx_npei_msi_rd_map_t; 2256 2257/** 2258 * cvmx_npei_msi_w1c_enb0 2259 * 2260 * NPEI_MSI_W1C_ENB0 = NPEI MSI Write 1 To Clear Enable0 2261 * 2262 * Used to clear bits in NPEI_MSI_ENB0. This is a PASS2 register. 2263 */ 2264union cvmx_npei_msi_w1c_enb0 { 2265 u64 u64; 2266 struct cvmx_npei_msi_w1c_enb0_s { 2267 u64 clr : 64; 2268 } s; 2269 struct cvmx_npei_msi_w1c_enb0_s cn52xx; 2270 struct cvmx_npei_msi_w1c_enb0_s cn56xx; 2271}; 2272 2273typedef union cvmx_npei_msi_w1c_enb0 cvmx_npei_msi_w1c_enb0_t; 2274 2275/** 2276 * cvmx_npei_msi_w1c_enb1 2277 * 2278 * NPEI_MSI_W1C_ENB1 = NPEI MSI Write 1 To Clear Enable1 2279 * 2280 * Used to clear bits in NPEI_MSI_ENB1. This is a PASS2 register. 2281 */ 2282union cvmx_npei_msi_w1c_enb1 { 2283 u64 u64; 2284 struct cvmx_npei_msi_w1c_enb1_s { 2285 u64 clr : 64; 2286 } s; 2287 struct cvmx_npei_msi_w1c_enb1_s cn52xx; 2288 struct cvmx_npei_msi_w1c_enb1_s cn56xx; 2289}; 2290 2291typedef union cvmx_npei_msi_w1c_enb1 cvmx_npei_msi_w1c_enb1_t; 2292 2293/** 2294 * cvmx_npei_msi_w1c_enb2 2295 * 2296 * NPEI_MSI_W1C_ENB2 = NPEI MSI Write 1 To Clear Enable2 2297 * 2298 * Used to clear bits in NPEI_MSI_ENB2. This is a PASS2 register. 2299 */ 2300union cvmx_npei_msi_w1c_enb2 { 2301 u64 u64; 2302 struct cvmx_npei_msi_w1c_enb2_s { 2303 u64 clr : 64; 2304 } s; 2305 struct cvmx_npei_msi_w1c_enb2_s cn52xx; 2306 struct cvmx_npei_msi_w1c_enb2_s cn56xx; 2307}; 2308 2309typedef union cvmx_npei_msi_w1c_enb2 cvmx_npei_msi_w1c_enb2_t; 2310 2311/** 2312 * cvmx_npei_msi_w1c_enb3 2313 * 2314 * NPEI_MSI_W1C_ENB3 = NPEI MSI Write 1 To Clear Enable3 2315 * 2316 * Used to clear bits in NPEI_MSI_ENB3. This is a PASS2 register. 2317 */ 2318union cvmx_npei_msi_w1c_enb3 { 2319 u64 u64; 2320 struct cvmx_npei_msi_w1c_enb3_s { 2321 u64 clr : 64; 2322 } s; 2323 struct cvmx_npei_msi_w1c_enb3_s cn52xx; 2324 struct cvmx_npei_msi_w1c_enb3_s cn56xx; 2325}; 2326 2327typedef union cvmx_npei_msi_w1c_enb3 cvmx_npei_msi_w1c_enb3_t; 2328 2329/** 2330 * cvmx_npei_msi_w1s_enb0 2331 * 2332 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable0 2333 * 2334 * Used to set bits in NPEI_MSI_ENB0. This is a PASS2 register. 2335 */ 2336union cvmx_npei_msi_w1s_enb0 { 2337 u64 u64; 2338 struct cvmx_npei_msi_w1s_enb0_s { 2339 u64 set : 64; 2340 } s; 2341 struct cvmx_npei_msi_w1s_enb0_s cn52xx; 2342 struct cvmx_npei_msi_w1s_enb0_s cn56xx; 2343}; 2344 2345typedef union cvmx_npei_msi_w1s_enb0 cvmx_npei_msi_w1s_enb0_t; 2346 2347/** 2348 * cvmx_npei_msi_w1s_enb1 2349 * 2350 * NPEI_MSI_W1S_ENB0 = NPEI MSI Write 1 To Set Enable1 2351 * 2352 * Used to set bits in NPEI_MSI_ENB1. This is a PASS2 register. 2353 */ 2354union cvmx_npei_msi_w1s_enb1 { 2355 u64 u64; 2356 struct cvmx_npei_msi_w1s_enb1_s { 2357 u64 set : 64; 2358 } s; 2359 struct cvmx_npei_msi_w1s_enb1_s cn52xx; 2360 struct cvmx_npei_msi_w1s_enb1_s cn56xx; 2361}; 2362 2363typedef union cvmx_npei_msi_w1s_enb1 cvmx_npei_msi_w1s_enb1_t; 2364 2365/** 2366 * cvmx_npei_msi_w1s_enb2 2367 * 2368 * NPEI_MSI_W1S_ENB2 = NPEI MSI Write 1 To Set Enable2 2369 * 2370 * Used to set bits in NPEI_MSI_ENB2. This is a PASS2 register. 2371 */ 2372union cvmx_npei_msi_w1s_enb2 { 2373 u64 u64; 2374 struct cvmx_npei_msi_w1s_enb2_s { 2375 u64 set : 64; 2376 } s; 2377 struct cvmx_npei_msi_w1s_enb2_s cn52xx; 2378 struct cvmx_npei_msi_w1s_enb2_s cn56xx; 2379}; 2380 2381typedef union cvmx_npei_msi_w1s_enb2 cvmx_npei_msi_w1s_enb2_t; 2382 2383/** 2384 * cvmx_npei_msi_w1s_enb3 2385 * 2386 * NPEI_MSI_W1S_ENB3 = NPEI MSI Write 1 To Set Enable3 2387 * 2388 * Used to set bits in NPEI_MSI_ENB3. This is a PASS2 register. 2389 */ 2390union cvmx_npei_msi_w1s_enb3 { 2391 u64 u64; 2392 struct cvmx_npei_msi_w1s_enb3_s { 2393 u64 set : 64; 2394 } s; 2395 struct cvmx_npei_msi_w1s_enb3_s cn52xx; 2396 struct cvmx_npei_msi_w1s_enb3_s cn56xx; 2397}; 2398 2399typedef union cvmx_npei_msi_w1s_enb3 cvmx_npei_msi_w1s_enb3_t; 2400 2401/** 2402 * cvmx_npei_msi_wr_map 2403 * 2404 * NPEI_MSI_WR_MAP = NPEI MSI Write MAP 2405 * 2406 * Used to write the mapping function of the NPEI_PCIE_MSI_RCV to NPEI_MSI_RCV 2407 * registers. 2408 */ 2409union cvmx_npei_msi_wr_map { 2410 u64 u64; 2411 struct cvmx_npei_msi_wr_map_s { 2412 u64 reserved_16_63 : 48; 2413 u64 ciu_int : 8; 2414 u64 msi_int : 8; 2415 } s; 2416 struct cvmx_npei_msi_wr_map_s cn52xx; 2417 struct cvmx_npei_msi_wr_map_s cn52xxp1; 2418 struct cvmx_npei_msi_wr_map_s cn56xx; 2419 struct cvmx_npei_msi_wr_map_s cn56xxp1; 2420}; 2421 2422typedef union cvmx_npei_msi_wr_map cvmx_npei_msi_wr_map_t; 2423 2424/** 2425 * cvmx_npei_pcie_credit_cnt 2426 * 2427 * NPEI_PCIE_CREDIT_CNT = NPEI PCIE Credit Count 2428 * 2429 * Contains the number of credits for the pcie port FIFOs used by the NPEI. 2430 * This value needs to be set BEFORE PCIe traffic 2431 * flow from NPEI to PCIE Ports starts. A write to this register will cause 2432 * the credit counts in the NPEI for the two 2433 * PCIE ports to be reset to the value in this register. 2434 */ 2435union cvmx_npei_pcie_credit_cnt { 2436 u64 u64; 2437 struct cvmx_npei_pcie_credit_cnt_s { 2438 u64 reserved_48_63 : 16; 2439 u64 p1_ccnt : 8; 2440 u64 p1_ncnt : 8; 2441 u64 p1_pcnt : 8; 2442 u64 p0_ccnt : 8; 2443 u64 p0_ncnt : 8; 2444 u64 p0_pcnt : 8; 2445 } s; 2446 struct cvmx_npei_pcie_credit_cnt_s cn52xx; 2447 struct cvmx_npei_pcie_credit_cnt_s cn56xx; 2448}; 2449 2450typedef union cvmx_npei_pcie_credit_cnt cvmx_npei_pcie_credit_cnt_t; 2451 2452/** 2453 * cvmx_npei_pcie_msi_rcv 2454 * 2455 * NPEI_PCIE_MSI_RCV = NPEI PCIe MSI Receive 2456 * 2457 * Register where MSI writes are directed from the PCIe. 2458 */ 2459union cvmx_npei_pcie_msi_rcv { 2460 u64 u64; 2461 struct cvmx_npei_pcie_msi_rcv_s { 2462 u64 reserved_8_63 : 56; 2463 u64 intr : 8; 2464 } s; 2465 struct cvmx_npei_pcie_msi_rcv_s cn52xx; 2466 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1; 2467 struct cvmx_npei_pcie_msi_rcv_s cn56xx; 2468 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1; 2469}; 2470 2471typedef union cvmx_npei_pcie_msi_rcv cvmx_npei_pcie_msi_rcv_t; 2472 2473/** 2474 * cvmx_npei_pcie_msi_rcv_b1 2475 * 2476 * NPEI_PCIE_MSI_RCV_B1 = NPEI PCIe MSI Receive Byte 1 2477 * 2478 * Register where MSI writes are directed from the PCIe. 2479 */ 2480union cvmx_npei_pcie_msi_rcv_b1 { 2481 u64 u64; 2482 struct cvmx_npei_pcie_msi_rcv_b1_s { 2483 u64 reserved_16_63 : 48; 2484 u64 intr : 8; 2485 u64 reserved_0_7 : 8; 2486 } s; 2487 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx; 2488 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1; 2489 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx; 2490 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1; 2491}; 2492 2493typedef union cvmx_npei_pcie_msi_rcv_b1 cvmx_npei_pcie_msi_rcv_b1_t; 2494 2495/** 2496 * cvmx_npei_pcie_msi_rcv_b2 2497 * 2498 * NPEI_PCIE_MSI_RCV_B2 = NPEI PCIe MSI Receive Byte 2 2499 * 2500 * Register where MSI writes are directed from the PCIe. 2501 */ 2502union cvmx_npei_pcie_msi_rcv_b2 { 2503 u64 u64; 2504 struct cvmx_npei_pcie_msi_rcv_b2_s { 2505 u64 reserved_24_63 : 40; 2506 u64 intr : 8; 2507 u64 reserved_0_15 : 16; 2508 } s; 2509 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx; 2510 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1; 2511 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx; 2512 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1; 2513}; 2514 2515typedef union cvmx_npei_pcie_msi_rcv_b2 cvmx_npei_pcie_msi_rcv_b2_t; 2516 2517/** 2518 * cvmx_npei_pcie_msi_rcv_b3 2519 * 2520 * NPEI_PCIE_MSI_RCV_B3 = NPEI PCIe MSI Receive Byte 3 2521 * 2522 * Register where MSI writes are directed from the PCIe. 2523 */ 2524union cvmx_npei_pcie_msi_rcv_b3 { 2525 u64 u64; 2526 struct cvmx_npei_pcie_msi_rcv_b3_s { 2527 u64 reserved_32_63 : 32; 2528 u64 intr : 8; 2529 u64 reserved_0_23 : 24; 2530 } s; 2531 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx; 2532 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1; 2533 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx; 2534 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1; 2535}; 2536 2537typedef union cvmx_npei_pcie_msi_rcv_b3 cvmx_npei_pcie_msi_rcv_b3_t; 2538 2539/** 2540 * cvmx_npei_pkt#_cnts 2541 * 2542 * NPEI_PKT[0..31]_CNTS = NPEI Packet ring# Counts 2543 * 2544 * The counters for output rings. 2545 */ 2546union cvmx_npei_pktx_cnts { 2547 u64 u64; 2548 struct cvmx_npei_pktx_cnts_s { 2549 u64 reserved_54_63 : 10; 2550 u64 timer : 22; 2551 u64 cnt : 32; 2552 } s; 2553 struct cvmx_npei_pktx_cnts_s cn52xx; 2554 struct cvmx_npei_pktx_cnts_s cn56xx; 2555}; 2556 2557typedef union cvmx_npei_pktx_cnts cvmx_npei_pktx_cnts_t; 2558 2559/** 2560 * cvmx_npei_pkt#_in_bp 2561 * 2562 * NPEI_PKT[0..31]_IN_BP = NPEI Packet ring# Input Backpressure 2563 * 2564 * The counters and thresholds for input packets to apply backpressure to 2565 * processing of the packets. 2566 */ 2567union cvmx_npei_pktx_in_bp { 2568 u64 u64; 2569 struct cvmx_npei_pktx_in_bp_s { 2570 u64 wmark : 32; 2571 u64 cnt : 32; 2572 } s; 2573 struct cvmx_npei_pktx_in_bp_s cn52xx; 2574 struct cvmx_npei_pktx_in_bp_s cn56xx; 2575}; 2576 2577typedef union cvmx_npei_pktx_in_bp cvmx_npei_pktx_in_bp_t; 2578 2579/** 2580 * cvmx_npei_pkt#_instr_baddr 2581 * 2582 * NPEI_PKT[0..31]_INSTR_BADDR = NPEI Packet ring# Instruction Base Address 2583 * 2584 * Start of Instruction for input packets. 2585 */ 2586union cvmx_npei_pktx_instr_baddr { 2587 u64 u64; 2588 struct cvmx_npei_pktx_instr_baddr_s { 2589 u64 addr : 61; 2590 u64 reserved_0_2 : 3; 2591 } s; 2592 struct cvmx_npei_pktx_instr_baddr_s cn52xx; 2593 struct cvmx_npei_pktx_instr_baddr_s cn56xx; 2594}; 2595 2596typedef union cvmx_npei_pktx_instr_baddr cvmx_npei_pktx_instr_baddr_t; 2597 2598/** 2599 * cvmx_npei_pkt#_instr_baoff_dbell 2600 * 2601 * NPEI_PKT[0..31]_INSTR_BAOFF_DBELL = NPEI Packet ring# Instruction Base 2602 * Address Offset and Doorbell 2603 * 2604 * The doorbell and base address offset for next read. 2605 */ 2606union cvmx_npei_pktx_instr_baoff_dbell { 2607 u64 u64; 2608 struct cvmx_npei_pktx_instr_baoff_dbell_s { 2609 u64 aoff : 32; 2610 u64 dbell : 32; 2611 } s; 2612 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx; 2613 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx; 2614}; 2615 2616typedef union cvmx_npei_pktx_instr_baoff_dbell 2617 cvmx_npei_pktx_instr_baoff_dbell_t; 2618 2619/** 2620 * cvmx_npei_pkt#_instr_fifo_rsize 2621 * 2622 * NPEI_PKT[0..31]_INSTR_FIFO_RSIZE = NPEI Packet ring# Instruction FIFO and 2623 * Ring Size. 2624 * 2625 * Fifo field and ring size for Instructions. 2626 */ 2627union cvmx_npei_pktx_instr_fifo_rsize { 2628 u64 u64; 2629 struct cvmx_npei_pktx_instr_fifo_rsize_s { 2630 u64 max : 9; 2631 u64 rrp : 9; 2632 u64 wrp : 9; 2633 u64 fcnt : 5; 2634 u64 rsize : 32; 2635 } s; 2636 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx; 2637 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx; 2638}; 2639 2640typedef union cvmx_npei_pktx_instr_fifo_rsize cvmx_npei_pktx_instr_fifo_rsize_t; 2641 2642/** 2643 * cvmx_npei_pkt#_instr_header 2644 * 2645 * NPEI_PKT[0..31]_INSTR_HEADER = NPEI Packet ring# Instruction Header. 2646 * 2647 * VAlues used to build input packet header. 2648 */ 2649union cvmx_npei_pktx_instr_header { 2650 u64 u64; 2651 struct cvmx_npei_pktx_instr_header_s { 2652 u64 reserved_44_63 : 20; 2653 u64 pbp : 1; 2654 u64 reserved_38_42 : 5; 2655 u64 rparmode : 2; 2656 u64 reserved_35_35 : 1; 2657 u64 rskp_len : 7; 2658 u64 reserved_22_27 : 6; 2659 u64 use_ihdr : 1; 2660 u64 reserved_16_20 : 5; 2661 u64 par_mode : 2; 2662 u64 reserved_13_13 : 1; 2663 u64 skp_len : 7; 2664 u64 reserved_0_5 : 6; 2665 } s; 2666 struct cvmx_npei_pktx_instr_header_s cn52xx; 2667 struct cvmx_npei_pktx_instr_header_s cn56xx; 2668}; 2669 2670typedef union cvmx_npei_pktx_instr_header cvmx_npei_pktx_instr_header_t; 2671 2672/** 2673 * cvmx_npei_pkt#_slist_baddr 2674 * 2675 * NPEI_PKT[0..31]_SLIST_BADDR = NPEI Packet ring# Scatter List Base Address 2676 * 2677 * Start of Scatter List for output packet pointers - MUST be 16 byte aligned 2678 */ 2679union cvmx_npei_pktx_slist_baddr { 2680 u64 u64; 2681 struct cvmx_npei_pktx_slist_baddr_s { 2682 u64 addr : 60; 2683 u64 reserved_0_3 : 4; 2684 } s; 2685 struct cvmx_npei_pktx_slist_baddr_s cn52xx; 2686 struct cvmx_npei_pktx_slist_baddr_s cn56xx; 2687}; 2688 2689typedef union cvmx_npei_pktx_slist_baddr cvmx_npei_pktx_slist_baddr_t; 2690 2691/** 2692 * cvmx_npei_pkt#_slist_baoff_dbell 2693 * 2694 * NPEI_PKT[0..31]_SLIST_BAOFF_DBELL = NPEI Packet ring# Scatter List Base 2695 * Address Offset and Doorbell 2696 * 2697 * The doorbell and base address offset for next read. 2698 */ 2699union cvmx_npei_pktx_slist_baoff_dbell { 2700 u64 u64; 2701 struct cvmx_npei_pktx_slist_baoff_dbell_s { 2702 u64 aoff : 32; 2703 u64 dbell : 32; 2704 } s; 2705 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx; 2706 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx; 2707}; 2708 2709typedef union cvmx_npei_pktx_slist_baoff_dbell 2710 cvmx_npei_pktx_slist_baoff_dbell_t; 2711 2712/** 2713 * cvmx_npei_pkt#_slist_fifo_rsize 2714 * 2715 * NPEI_PKT[0..31]_SLIST_FIFO_RSIZE = NPEI Packet ring# Scatter List FIFO and 2716 * Ring Size. 2717 * 2718 * The number of scatter pointer pairs in the scatter list. 2719 */ 2720union cvmx_npei_pktx_slist_fifo_rsize { 2721 u64 u64; 2722 struct cvmx_npei_pktx_slist_fifo_rsize_s { 2723 u64 reserved_32_63 : 32; 2724 u64 rsize : 32; 2725 } s; 2726 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx; 2727 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx; 2728}; 2729 2730typedef union cvmx_npei_pktx_slist_fifo_rsize cvmx_npei_pktx_slist_fifo_rsize_t; 2731 2732/** 2733 * cvmx_npei_pkt_cnt_int 2734 * 2735 * NPEI_PKT_CNT_INT = NPI Packet Counter Interrupt 2736 * 2737 * The packets rings that are interrupting because of Packet Counters. 2738 */ 2739union cvmx_npei_pkt_cnt_int { 2740 u64 u64; 2741 struct cvmx_npei_pkt_cnt_int_s { 2742 u64 reserved_32_63 : 32; 2743 u64 port : 32; 2744 } s; 2745 struct cvmx_npei_pkt_cnt_int_s cn52xx; 2746 struct cvmx_npei_pkt_cnt_int_s cn56xx; 2747}; 2748 2749typedef union cvmx_npei_pkt_cnt_int cvmx_npei_pkt_cnt_int_t; 2750 2751/** 2752 * cvmx_npei_pkt_cnt_int_enb 2753 * 2754 * NPEI_PKT_CNT_INT_ENB = NPI Packet Counter Interrupt Enable 2755 * 2756 * Enable for the packets rings that are interrupting because of Packet Counters. 2757 */ 2758union cvmx_npei_pkt_cnt_int_enb { 2759 u64 u64; 2760 struct cvmx_npei_pkt_cnt_int_enb_s { 2761 u64 reserved_32_63 : 32; 2762 u64 port : 32; 2763 } s; 2764 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx; 2765 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx; 2766}; 2767 2768typedef union cvmx_npei_pkt_cnt_int_enb cvmx_npei_pkt_cnt_int_enb_t; 2769 2770/** 2771 * cvmx_npei_pkt_data_out_es 2772 * 2773 * NPEI_PKT_DATA_OUT_ES = NPEI's Packet Data Out Endian Swap 2774 * 2775 * The Endian Swap for writing Data Out. 2776 */ 2777union cvmx_npei_pkt_data_out_es { 2778 u64 u64; 2779 struct cvmx_npei_pkt_data_out_es_s { 2780 u64 es : 64; 2781 } s; 2782 struct cvmx_npei_pkt_data_out_es_s cn52xx; 2783 struct cvmx_npei_pkt_data_out_es_s cn56xx; 2784}; 2785 2786typedef union cvmx_npei_pkt_data_out_es cvmx_npei_pkt_data_out_es_t; 2787 2788/** 2789 * cvmx_npei_pkt_data_out_ns 2790 * 2791 * NPEI_PKT_DATA_OUT_NS = NPEI's Packet Data Out No Snoop 2792 * 2793 * The NS field for the TLP when writing packet data. 2794 */ 2795union cvmx_npei_pkt_data_out_ns { 2796 u64 u64; 2797 struct cvmx_npei_pkt_data_out_ns_s { 2798 u64 reserved_32_63 : 32; 2799 u64 nsr : 32; 2800 } s; 2801 struct cvmx_npei_pkt_data_out_ns_s cn52xx; 2802 struct cvmx_npei_pkt_data_out_ns_s cn56xx; 2803}; 2804 2805typedef union cvmx_npei_pkt_data_out_ns cvmx_npei_pkt_data_out_ns_t; 2806 2807/** 2808 * cvmx_npei_pkt_data_out_ror 2809 * 2810 * NPEI_PKT_DATA_OUT_ROR = NPEI's Packet Data Out Relaxed Ordering 2811 * 2812 * The ROR field for the TLP when writing Packet Data. 2813 */ 2814union cvmx_npei_pkt_data_out_ror { 2815 u64 u64; 2816 struct cvmx_npei_pkt_data_out_ror_s { 2817 u64 reserved_32_63 : 32; 2818 u64 ror : 32; 2819 } s; 2820 struct cvmx_npei_pkt_data_out_ror_s cn52xx; 2821 struct cvmx_npei_pkt_data_out_ror_s cn56xx; 2822}; 2823 2824typedef union cvmx_npei_pkt_data_out_ror cvmx_npei_pkt_data_out_ror_t; 2825 2826/** 2827 * cvmx_npei_pkt_dpaddr 2828 * 2829 * NPEI_PKT_DPADDR = NPEI's Packet Data Pointer Addr 2830 * 2831 * Used to detemine address and attributes for packet data writes. 2832 */ 2833union cvmx_npei_pkt_dpaddr { 2834 u64 u64; 2835 struct cvmx_npei_pkt_dpaddr_s { 2836 u64 reserved_32_63 : 32; 2837 u64 dptr : 32; 2838 } s; 2839 struct cvmx_npei_pkt_dpaddr_s cn52xx; 2840 struct cvmx_npei_pkt_dpaddr_s cn56xx; 2841}; 2842 2843typedef union cvmx_npei_pkt_dpaddr cvmx_npei_pkt_dpaddr_t; 2844 2845/** 2846 * cvmx_npei_pkt_in_bp 2847 * 2848 * NPEI_PKT_IN_BP = NPEI Packet Input Backpressure 2849 * 2850 * Which input rings have backpressure applied. 2851 */ 2852union cvmx_npei_pkt_in_bp { 2853 u64 u64; 2854 struct cvmx_npei_pkt_in_bp_s { 2855 u64 reserved_32_63 : 32; 2856 u64 bp : 32; 2857 } s; 2858 struct cvmx_npei_pkt_in_bp_s cn52xx; 2859 struct cvmx_npei_pkt_in_bp_s cn56xx; 2860}; 2861 2862typedef union cvmx_npei_pkt_in_bp cvmx_npei_pkt_in_bp_t; 2863 2864/** 2865 * cvmx_npei_pkt_in_done#_cnts 2866 * 2867 * NPEI_PKT_IN_DONE[0..31]_CNTS = NPEI Instruction Done ring# Counts 2868 * 2869 * Counters for instructions completed on Input rings. 2870 */ 2871union cvmx_npei_pkt_in_donex_cnts { 2872 u64 u64; 2873 struct cvmx_npei_pkt_in_donex_cnts_s { 2874 u64 reserved_32_63 : 32; 2875 u64 cnt : 32; 2876 } s; 2877 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx; 2878 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx; 2879}; 2880 2881typedef union cvmx_npei_pkt_in_donex_cnts cvmx_npei_pkt_in_donex_cnts_t; 2882 2883/** 2884 * cvmx_npei_pkt_in_instr_counts 2885 * 2886 * NPEI_PKT_IN_INSTR_COUNTS = NPEI Packet Input Instrutction Counts 2887 * 2888 * Keeps track of the number of instructions read into the FIFO and Packets 2889 * sent to IPD. 2890 */ 2891union cvmx_npei_pkt_in_instr_counts { 2892 u64 u64; 2893 struct cvmx_npei_pkt_in_instr_counts_s { 2894 u64 wr_cnt : 32; 2895 u64 rd_cnt : 32; 2896 } s; 2897 struct cvmx_npei_pkt_in_instr_counts_s cn52xx; 2898 struct cvmx_npei_pkt_in_instr_counts_s cn56xx; 2899}; 2900 2901typedef union cvmx_npei_pkt_in_instr_counts cvmx_npei_pkt_in_instr_counts_t; 2902 2903/** 2904 * cvmx_npei_pkt_in_pcie_port 2905 * 2906 * NPEI_PKT_IN_PCIE_PORT = NPEI's Packet In To PCIe Port Assignment 2907 * 2908 * Assigns Packet Input rings to PCIe ports. 2909 */ 2910union cvmx_npei_pkt_in_pcie_port { 2911 u64 u64; 2912 struct cvmx_npei_pkt_in_pcie_port_s { 2913 u64 pp : 64; 2914 } s; 2915 struct cvmx_npei_pkt_in_pcie_port_s cn52xx; 2916 struct cvmx_npei_pkt_in_pcie_port_s cn56xx; 2917}; 2918 2919typedef union cvmx_npei_pkt_in_pcie_port cvmx_npei_pkt_in_pcie_port_t; 2920 2921/** 2922 * cvmx_npei_pkt_input_control 2923 * 2924 * NPEI_PKT_INPUT_CONTROL = NPEI's Packet Input Control 2925 * 2926 * Control for reads for gather list and instructions. 2927 */ 2928union cvmx_npei_pkt_input_control { 2929 u64 u64; 2930 struct cvmx_npei_pkt_input_control_s { 2931 u64 reserved_23_63 : 41; 2932 u64 pkt_rr : 1; 2933 u64 pbp_dhi : 13; 2934 u64 d_nsr : 1; 2935 u64 d_esr : 2; 2936 u64 d_ror : 1; 2937 u64 use_csr : 1; 2938 u64 nsr : 1; 2939 u64 esr : 2; 2940 u64 ror : 1; 2941 } s; 2942 struct cvmx_npei_pkt_input_control_s cn52xx; 2943 struct cvmx_npei_pkt_input_control_s cn56xx; 2944}; 2945 2946typedef union cvmx_npei_pkt_input_control cvmx_npei_pkt_input_control_t; 2947 2948/** 2949 * cvmx_npei_pkt_instr_enb 2950 * 2951 * NPEI_PKT_INSTR_ENB = NPEI's Packet Instruction Enable 2952 * 2953 * Enables the instruction fetch for a Packet-ring. 2954 */ 2955union cvmx_npei_pkt_instr_enb { 2956 u64 u64; 2957 struct cvmx_npei_pkt_instr_enb_s { 2958 u64 reserved_32_63 : 32; 2959 u64 enb : 32; 2960 } s; 2961 struct cvmx_npei_pkt_instr_enb_s cn52xx; 2962 struct cvmx_npei_pkt_instr_enb_s cn56xx; 2963}; 2964 2965typedef union cvmx_npei_pkt_instr_enb cvmx_npei_pkt_instr_enb_t; 2966 2967/** 2968 * cvmx_npei_pkt_instr_rd_size 2969 * 2970 * NPEI_PKT_INSTR_RD_SIZE = NPEI Instruction Read Size 2971 * 2972 * The number of instruction allowed to be read at one time. 2973 */ 2974union cvmx_npei_pkt_instr_rd_size { 2975 u64 u64; 2976 struct cvmx_npei_pkt_instr_rd_size_s { 2977 u64 rdsize : 64; 2978 } s; 2979 struct cvmx_npei_pkt_instr_rd_size_s cn52xx; 2980 struct cvmx_npei_pkt_instr_rd_size_s cn56xx; 2981}; 2982 2983typedef union cvmx_npei_pkt_instr_rd_size cvmx_npei_pkt_instr_rd_size_t; 2984 2985/** 2986 * cvmx_npei_pkt_instr_size 2987 * 2988 * NPEI_PKT_INSTR_SIZE = NPEI's Packet Instruction Size 2989 * 2990 * Determines if instructions are 64 or 32 byte in size for a Packet-ring. 2991 */ 2992union cvmx_npei_pkt_instr_size { 2993 u64 u64; 2994 struct cvmx_npei_pkt_instr_size_s { 2995 u64 reserved_32_63 : 32; 2996 u64 is_64b : 32; 2997 } s; 2998 struct cvmx_npei_pkt_instr_size_s cn52xx; 2999 struct cvmx_npei_pkt_instr_size_s cn56xx; 3000};
3001 3002typedef union cvmx_npei_pkt_instr_size cvmx_npei_pkt_instr_size_t; 3003 3004/** 3005 * cvmx_npei_pkt_int_levels 3006 * 3007 * 0x90F0 reserved NPEI_PKT_PCIE_PORT2 3008 * 3009 * 3010 * NPEI_PKT_INT_LEVELS = NPEI's Packet Interrupt Levels 3011 * 3012 * Output packet interrupt levels. 3013 */ 3014union cvmx_npei_pkt_int_levels { 3015 u64 u64; 3016 struct cvmx_npei_pkt_int_levels_s { 3017 u64 reserved_54_63 : 10; 3018 u64 time : 22; 3019 u64 cnt : 32; 3020 } s; 3021 struct cvmx_npei_pkt_int_levels_s cn52xx; 3022 struct cvmx_npei_pkt_int_levels_s cn56xx; 3023}; 3024 3025typedef union cvmx_npei_pkt_int_levels cvmx_npei_pkt_int_levels_t; 3026 3027/** 3028 * cvmx_npei_pkt_iptr 3029 * 3030 * NPEI_PKT_IPTR = NPEI's Packet Info Poitner 3031 * 3032 * Controls using the Info-Pointer to store length and data. 3033 */ 3034union cvmx_npei_pkt_iptr { 3035 u64 u64; 3036 struct cvmx_npei_pkt_iptr_s { 3037 u64 reserved_32_63 : 32; 3038 u64 iptr : 32; 3039 } s; 3040 struct cvmx_npei_pkt_iptr_s cn52xx; 3041 struct cvmx_npei_pkt_iptr_s cn56xx; 3042}; 3043 3044typedef union cvmx_npei_pkt_iptr cvmx_npei_pkt_iptr_t; 3045 3046/** 3047 * cvmx_npei_pkt_out_bmode 3048 * 3049 * NPEI_PKT_OUT_BMODE = NPEI's Packet Out Byte Mode 3050 * 3051 * Control the updating of the NPEI_PKT#_CNT register. 3052 */ 3053union cvmx_npei_pkt_out_bmode { 3054 u64 u64; 3055 struct cvmx_npei_pkt_out_bmode_s { 3056 u64 reserved_32_63 : 32; 3057 u64 bmode : 32; 3058 } s; 3059 struct cvmx_npei_pkt_out_bmode_s cn52xx; 3060 struct cvmx_npei_pkt_out_bmode_s cn56xx; 3061}; 3062 3063typedef union cvmx_npei_pkt_out_bmode cvmx_npei_pkt_out_bmode_t; 3064 3065/** 3066 * cvmx_npei_pkt_out_enb 3067 * 3068 * NPEI_PKT_OUT_ENB = NPEI's Packet Output Enable 3069 * 3070 * Enables the output packet engines. 3071 */ 3072union cvmx_npei_pkt_out_enb { 3073 u64 u64; 3074 struct cvmx_npei_pkt_out_enb_s { 3075 u64 reserved_32_63 : 32; 3076 u64 enb : 32; 3077 } s; 3078 struct cvmx_npei_pkt_out_enb_s cn52xx; 3079 struct cvmx_npei_pkt_out_enb_s cn56xx; 3080}; 3081 3082typedef union cvmx_npei_pkt_out_enb cvmx_npei_pkt_out_enb_t; 3083 3084/** 3085 * cvmx_npei_pkt_output_wmark 3086 * 3087 * NPEI_PKT_OUTPUT_WMARK = NPEI's Packet Output Water Mark 3088 * 3089 * Value that when the NPEI_PKT#_SLIST_BAOFF_DBELL[DBELL] value is less then 3090 * that backpressure for the rings will be applied. 3091 */ 3092union cvmx_npei_pkt_output_wmark { 3093 u64 u64; 3094 struct cvmx_npei_pkt_output_wmark_s { 3095 u64 reserved_32_63 : 32; 3096 u64 wmark : 32; 3097 } s; 3098 struct cvmx_npei_pkt_output_wmark_s cn52xx; 3099 struct cvmx_npei_pkt_output_wmark_s cn56xx; 3100}; 3101 3102typedef union cvmx_npei_pkt_output_wmark cvmx_npei_pkt_output_wmark_t; 3103 3104/** 3105 * cvmx_npei_pkt_pcie_port 3106 * 3107 * NPEI_PKT_PCIE_PORT = NPEI's Packet To PCIe Port Assignment 3108 * 3109 * Assigns Packet Ports to PCIe ports. 3110 */ 3111union cvmx_npei_pkt_pcie_port { 3112 u64 u64; 3113 struct cvmx_npei_pkt_pcie_port_s { 3114 u64 pp : 64; 3115 } s; 3116 struct cvmx_npei_pkt_pcie_port_s cn52xx; 3117 struct cvmx_npei_pkt_pcie_port_s cn56xx; 3118}; 3119 3120typedef union cvmx_npei_pkt_pcie_port cvmx_npei_pkt_pcie_port_t; 3121 3122/** 3123 * cvmx_npei_pkt_port_in_rst 3124 * 3125 * NPEI_PKT_PORT_IN_RST = NPEI Packet Port In Reset 3126 * 3127 * Vector bits related to ring-port for ones that are reset. 3128 */ 3129union cvmx_npei_pkt_port_in_rst { 3130 u64 u64; 3131 struct cvmx_npei_pkt_port_in_rst_s { 3132 u64 in_rst : 32; 3133 u64 out_rst : 32; 3134 } s; 3135 struct cvmx_npei_pkt_port_in_rst_s cn52xx; 3136 struct cvmx_npei_pkt_port_in_rst_s cn56xx; 3137}; 3138 3139typedef union cvmx_npei_pkt_port_in_rst cvmx_npei_pkt_port_in_rst_t; 3140 3141/** 3142 * cvmx_npei_pkt_slist_es 3143 * 3144 * NPEI_PKT_SLIST_ES = NPEI's Packet Scatter List Endian Swap 3145 * 3146 * The Endian Swap for Scatter List Read. 3147 */ 3148union cvmx_npei_pkt_slist_es { 3149 u64 u64; 3150 struct cvmx_npei_pkt_slist_es_s { 3151 u64 es : 64; 3152 } s; 3153 struct cvmx_npei_pkt_slist_es_s cn52xx; 3154 struct cvmx_npei_pkt_slist_es_s cn56xx; 3155}; 3156 3157typedef union cvmx_npei_pkt_slist_es cvmx_npei_pkt_slist_es_t; 3158 3159/** 3160 * cvmx_npei_pkt_slist_id_size 3161 * 3162 * NPEI_PKT_SLIST_ID_SIZE = NPEI Packet Scatter List Info and Data Size 3163 * 3164 * The Size of the information and data fields pointed to by Scatter List 3165 * pointers. 3166 */ 3167union cvmx_npei_pkt_slist_id_size { 3168 u64 u64; 3169 struct cvmx_npei_pkt_slist_id_size_s { 3170 u64 reserved_23_63 : 41; 3171 u64 isize : 7; 3172 u64 bsize : 16; 3173 } s; 3174 struct cvmx_npei_pkt_slist_id_size_s cn52xx; 3175 struct cvmx_npei_pkt_slist_id_size_s cn56xx; 3176}; 3177 3178typedef union cvmx_npei_pkt_slist_id_size cvmx_npei_pkt_slist_id_size_t; 3179 3180/** 3181 * cvmx_npei_pkt_slist_ns 3182 * 3183 * NPEI_PKT_SLIST_NS = NPEI's Packet Scatter List No Snoop 3184 * 3185 * The NS field for the TLP when fetching Scatter List. 3186 */ 3187union cvmx_npei_pkt_slist_ns { 3188 u64 u64; 3189 struct cvmx_npei_pkt_slist_ns_s { 3190 u64 reserved_32_63 : 32; 3191 u64 nsr : 32; 3192 } s; 3193 struct cvmx_npei_pkt_slist_ns_s cn52xx; 3194 struct cvmx_npei_pkt_slist_ns_s cn56xx; 3195}; 3196 3197typedef union cvmx_npei_pkt_slist_ns cvmx_npei_pkt_slist_ns_t; 3198 3199/** 3200 * cvmx_npei_pkt_slist_ror 3201 * 3202 * NPEI_PKT_SLIST_ROR = NPEI's Packet Scatter List Relaxed Ordering 3203 * 3204 * The ROR field for the TLP when fetching Scatter List. 3205 */ 3206union cvmx_npei_pkt_slist_ror { 3207 u64 u64; 3208 struct cvmx_npei_pkt_slist_ror_s { 3209 u64 reserved_32_63 : 32; 3210 u64 ror : 32; 3211 } s; 3212 struct cvmx_npei_pkt_slist_ror_s cn52xx; 3213 struct cvmx_npei_pkt_slist_ror_s cn56xx; 3214}; 3215 3216typedef union cvmx_npei_pkt_slist_ror cvmx_npei_pkt_slist_ror_t; 3217 3218/** 3219 * cvmx_npei_pkt_time_int 3220 * 3221 * NPEI_PKT_TIME_INT = NPEI Packet Timer Interrupt 3222 * 3223 * The packets rings that are interrupting because of Packet Timers. 3224 */ 3225union cvmx_npei_pkt_time_int { 3226 u64 u64; 3227 struct cvmx_npei_pkt_time_int_s { 3228 u64 reserved_32_63 : 32; 3229 u64 port : 32; 3230 } s; 3231 struct cvmx_npei_pkt_time_int_s cn52xx; 3232 struct cvmx_npei_pkt_time_int_s cn56xx; 3233}; 3234 3235typedef union cvmx_npei_pkt_time_int cvmx_npei_pkt_time_int_t; 3236 3237/** 3238 * cvmx_npei_pkt_time_int_enb 3239 * 3240 * NPEI_PKT_TIME_INT_ENB = NPEI Packet Timer Interrupt Enable 3241 * 3242 * The packets rings that are interrupting because of Packet Timers. 3243 */ 3244union cvmx_npei_pkt_time_int_enb { 3245 u64 u64; 3246 struct cvmx_npei_pkt_time_int_enb_s { 3247 u64 reserved_32_63 : 32; 3248 u64 port : 32; 3249 } s; 3250 struct cvmx_npei_pkt_time_int_enb_s cn52xx; 3251 struct cvmx_npei_pkt_time_int_enb_s cn56xx; 3252}; 3253 3254typedef union cvmx_npei_pkt_time_int_enb cvmx_npei_pkt_time_int_enb_t; 3255 3256/** 3257 * cvmx_npei_rsl_int_blocks 3258 * 3259 * NPEI_RSL_INT_BLOCKS = NPEI RSL Interrupt Blocks Register 3260 * 3261 * Reading this register will return a vector with a bit set '1' for a 3262 * corresponding RSL block 3263 * that presently has an interrupt pending. The Field Description below 3264 * supplies the name of the 3265 * register that software should read to find out why that intterupt bit is set. 3266 */ 3267union cvmx_npei_rsl_int_blocks { 3268 u64 u64; 3269 struct cvmx_npei_rsl_int_blocks_s { 3270 u64 reserved_31_63 : 33; 3271 u64 iob : 1; 3272 u64 lmc1 : 1; 3273 u64 agl : 1; 3274 u64 reserved_24_27 : 4; 3275 u64 asxpcs1 : 1; 3276 u64 asxpcs0 : 1; 3277 u64 reserved_21_21 : 1; 3278 u64 pip : 1; 3279 u64 spx1 : 1; 3280 u64 spx0 : 1; 3281 u64 lmc0 : 1; 3282 u64 l2c : 1; 3283 u64 usb1 : 1; 3284 u64 rad : 1; 3285 u64 usb : 1; 3286 u64 pow : 1; 3287 u64 tim : 1; 3288 u64 pko : 1; 3289 u64 ipd : 1; 3290 u64 reserved_8_8 : 1; 3291 u64 zip : 1; 3292 u64 dfa : 1; 3293 u64 fpa : 1; 3294 u64 key : 1; 3295 u64 npei : 1; 3296 u64 gmx1 : 1; 3297 u64 gmx0 : 1; 3298 u64 mio : 1; 3299 } s; 3300 struct cvmx_npei_rsl_int_blocks_s cn52xx; 3301 struct cvmx_npei_rsl_int_blocks_s cn52xxp1; 3302 struct cvmx_npei_rsl_int_blocks_s cn56xx; 3303 struct cvmx_npei_rsl_int_blocks_s cn56xxp1; 3304}; 3305 3306typedef union cvmx_npei_rsl_int_blocks cvmx_npei_rsl_int_blocks_t; 3307 3308/** 3309 * cvmx_npei_scratch_1 3310 * 3311 * NPEI_SCRATCH_1 = NPEI's Scratch 1 3312 * 3313 * A general purpose 64 bit register for SW use. 3314 */ 3315union cvmx_npei_scratch_1 { 3316 u64 u64; 3317 struct cvmx_npei_scratch_1_s { 3318 u64 data : 64; 3319 } s; 3320 struct cvmx_npei_scratch_1_s cn52xx; 3321 struct cvmx_npei_scratch_1_s cn52xxp1; 3322 struct cvmx_npei_scratch_1_s cn56xx; 3323 struct cvmx_npei_scratch_1_s cn56xxp1; 3324}; 3325 3326typedef union cvmx_npei_scratch_1 cvmx_npei_scratch_1_t; 3327 3328/** 3329 * cvmx_npei_state1 3330 * 3331 * NPEI_STATE1 = NPEI State 1 3332 * 3333 * State machines in NPEI. For debug. 3334 */ 3335union cvmx_npei_state1 { 3336 u64 u64; 3337 struct cvmx_npei_state1_s { 3338 u64 cpl1 : 12; 3339 u64 cpl0 : 12; 3340 u64 arb : 1; 3341 u64 csr : 39; 3342 } s; 3343 struct cvmx_npei_state1_s cn52xx; 3344 struct cvmx_npei_state1_s cn52xxp1; 3345 struct cvmx_npei_state1_s cn56xx; 3346 struct cvmx_npei_state1_s cn56xxp1; 3347}; 3348 3349typedef union cvmx_npei_state1 cvmx_npei_state1_t; 3350 3351/** 3352 * cvmx_npei_state2 3353 * 3354 * NPEI_STATE2 = NPEI State 2 3355 * 3356 * State machines in NPEI. For debug. 3357 */ 3358union cvmx_npei_state2 { 3359 u64 u64; 3360 struct cvmx_npei_state2_s { 3361 u64 reserved_48_63 : 16; 3362 u64 npei : 1; 3363 u64 rac : 1; 3364 u64 csm1 : 15; 3365 u64 csm0 : 15; 3366 u64 nnp0 : 8; 3367 u64 nnd : 8; 3368 } s; 3369 struct cvmx_npei_state2_s cn52xx; 3370 struct cvmx_npei_state2_s cn52xxp1; 3371 struct cvmx_npei_state2_s cn56xx; 3372 struct cvmx_npei_state2_s cn56xxp1; 3373}; 3374 3375typedef union cvmx_npei_state2 cvmx_npei_state2_t; 3376 3377/** 3378 * cvmx_npei_state3 3379 * 3380 * NPEI_STATE3 = NPEI State 3 3381 * 3382 * State machines in NPEI. For debug. 3383 */ 3384union cvmx_npei_state3 { 3385 u64 u64; 3386 struct cvmx_npei_state3_s { 3387 u64 reserved_56_63 : 8; 3388 u64 psm1 : 15; 3389 u64 psm0 : 15; 3390 u64 nsm1 : 13; 3391 u64 nsm0 : 13; 3392 } s; 3393 struct cvmx_npei_state3_s cn52xx; 3394 struct cvmx_npei_state3_s cn52xxp1; 3395 struct cvmx_npei_state3_s cn56xx; 3396 struct cvmx_npei_state3_s cn56xxp1; 3397}; 3398 3399typedef union cvmx_npei_state3 cvmx_npei_state3_t; 3400 3401/** 3402 * cvmx_npei_win_rd_addr 3403 * 3404 * NPEI_WIN_RD_ADDR = NPEI Window Read Address Register 3405 * 3406 * The address to be read when the NPEI_WIN_RD_DATA register is read. 3407 */ 3408union cvmx_npei_win_rd_addr { 3409 u64 u64; 3410 struct cvmx_npei_win_rd_addr_s { 3411 u64 reserved_51_63 : 13; 3412 u64 ld_cmd : 2; 3413 u64 iobit : 1; 3414 u64 rd_addr : 48; 3415 } s; 3416 struct cvmx_npei_win_rd_addr_s cn52xx; 3417 struct cvmx_npei_win_rd_addr_s cn52xxp1; 3418 struct cvmx_npei_win_rd_addr_s cn56xx; 3419 struct cvmx_npei_win_rd_addr_s cn56xxp1; 3420}; 3421 3422typedef union cvmx_npei_win_rd_addr cvmx_npei_win_rd_addr_t; 3423 3424/** 3425 * cvmx_npei_win_rd_data 3426 * 3427 * NPEI_WIN_RD_DATA = NPEI Window Read Data Register 3428 * 3429 * Reading this register causes a window read operation to take place. 3430 * Address read is that contained in the NPEI_WIN_RD_ADDR 3431 * register. 3432 */ 3433union cvmx_npei_win_rd_data { 3434 u64 u64; 3435 struct cvmx_npei_win_rd_data_s { 3436 u64 rd_data : 64; 3437 } s; 3438 struct cvmx_npei_win_rd_data_s cn52xx; 3439 struct cvmx_npei_win_rd_data_s cn52xxp1; 3440 struct cvmx_npei_win_rd_data_s cn56xx; 3441 struct cvmx_npei_win_rd_data_s cn56xxp1; 3442}; 3443 3444typedef union cvmx_npei_win_rd_data cvmx_npei_win_rd_data_t; 3445 3446/** 3447 * cvmx_npei_win_wr_addr 3448 * 3449 * NPEI_WIN_WR_ADDR = NPEI Window Write Address Register 3450 * 3451 * Contains the address to be writen to when a write operation is started by 3452 * writing the 3453 * NPEI_WIN_WR_DATA register (see below). 3454 * 3455 * Notes: 3456 * Even though address bit [2] can be set, it should always be kept to '0'. 3457 * 3458 */ 3459union cvmx_npei_win_wr_addr { 3460 u64 u64; 3461 struct cvmx_npei_win_wr_addr_s { 3462 u64 reserved_49_63 : 15; 3463 u64 iobit : 1; 3464 u64 wr_addr : 46; 3465 u64 reserved_0_1 : 2; 3466 } s; 3467 struct cvmx_npei_win_wr_addr_s cn52xx; 3468 struct cvmx_npei_win_wr_addr_s cn52xxp1; 3469 struct cvmx_npei_win_wr_addr_s cn56xx; 3470 struct cvmx_npei_win_wr_addr_s cn56xxp1; 3471}; 3472 3473typedef union cvmx_npei_win_wr_addr cvmx_npei_win_wr_addr_t; 3474 3475/** 3476 * cvmx_npei_win_wr_data 3477 * 3478 * NPEI_WIN_WR_DATA = NPEI Window Write Data Register 3479 * 3480 * Contains the data to write to the address located in the NPEI_WIN_WR_ADDR 3481 * Register. 3482 * Writing the least-significant-byte of this register will cause a write 3483 * operation to take place. 3484 */ 3485union cvmx_npei_win_wr_data { 3486 u64 u64; 3487 struct cvmx_npei_win_wr_data_s { 3488 u64 wr_data : 64; 3489 } s; 3490 struct cvmx_npei_win_wr_data_s cn52xx; 3491 struct cvmx_npei_win_wr_data_s cn52xxp1; 3492 struct cvmx_npei_win_wr_data_s cn56xx; 3493 struct cvmx_npei_win_wr_data_s cn56xxp1; 3494}; 3495 3496typedef union cvmx_npei_win_wr_data cvmx_npei_win_wr_data_t; 3497 3498/** 3499 * cvmx_npei_win_wr_mask 3500 * 3501 * NPEI_WIN_WR_MASK = NPEI Window Write Mask Register 3502 * 3503 * Contains the mask for the data in the NPEI_WIN_WR_DATA Register. 3504 */ 3505union cvmx_npei_win_wr_mask { 3506 u64 u64; 3507 struct cvmx_npei_win_wr_mask_s { 3508 u64 reserved_8_63 : 56; 3509 u64 wr_mask : 8; 3510 } s; 3511 struct cvmx_npei_win_wr_mask_s cn52xx; 3512 struct cvmx_npei_win_wr_mask_s cn52xxp1; 3513 struct cvmx_npei_win_wr_mask_s cn56xx; 3514 struct cvmx_npei_win_wr_mask_s cn56xxp1; 3515}; 3516 3517typedef union cvmx_npei_win_wr_mask cvmx_npei_win_wr_mask_t; 3518 3519/** 3520 * cvmx_npei_window_ctl 3521 * 3522 * NPEI_WINDOW_CTL = NPEI's Window Control 3523 * 3524 * The name of this register is misleading. The timeout value is used for BAR0 3525 * access from PCIE0 and PCIE1. 3526 * Any access to the regigisters on the RML will timeout as 0xFFFF clock cycle. 3527 * At time of timeout the next 3528 * RML access will start, and interrupt will be set, and in the case of reads 3529 * no data will be returned. 3530 * 3531 * The value of this register should be set to a minimum of 0x200000 to ensure 3532 * that a timeout to an RML register 3533 * occurs on the RML 0xFFFF timer before the timeout for a BAR0 access from 3534 * the PCIE#. 3535 */ 3536union cvmx_npei_window_ctl { 3537 u64 u64; 3538 struct cvmx_npei_window_ctl_s { 3539 u64 reserved_32_63 : 32; 3540 u64 time : 32; 3541 } s; 3542 struct cvmx_npei_window_ctl_s cn52xx; 3543 struct cvmx_npei_window_ctl_s cn52xxp1; 3544 struct cvmx_npei_window_ctl_s cn56xx; 3545 struct cvmx_npei_window_ctl_s cn56xxp1; 3546}; 3547 3548typedef union cvmx_npei_window_ctl cvmx_npei_window_ctl_t; 3549 3550#endif 3551