LXR uboot/arch/riscv/include/asm/csr.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2015 Regents of the University of California
   4 *
   5 * Taken from Linux arch/riscv/include/asm/csr.h
   6 */
   7
   8#ifndef _ASM_RISCV_CSR_H
   9#define _ASM_RISCV_CSR_H
  10
  11#include <asm/asm.h>
  12#include <linux/const.h>
  13
  14/* Status register flags */
  15#define SR_SIE          _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
  16#define SR_SPIE         _AC(0x00000020, UL) /* Previous Supervisor IE */
  17#define SR_SPP          _AC(0x00000100, UL) /* Previously Supervisor */
  18#ifdef CONFIG_RISCV_PRIV_1_9
  19#define SR_PUM          _AC(0x00040000, UL) /* Protect User Memory Access */
  20#else
  21#define SR_SUM          _AC(0x00040000, UL) /* Supervisor User Memory Access */
  22#endif
  23
  24#define SR_FS           _AC(0x00006000, UL) /* Floating-point Status */
  25#define SR_FS_OFF       _AC(0x00000000, UL)
  26#define SR_FS_INITIAL   _AC(0x00002000, UL)
  27#define SR_FS_CLEAN     _AC(0x00004000, UL)
  28#define SR_FS_DIRTY     _AC(0x00006000, UL)
  29
  30#define SR_XS           _AC(0x00018000, UL) /* Extension Status */
  31#define SR_XS_OFF       _AC(0x00000000, UL)
  32#define SR_XS_INITIAL   _AC(0x00008000, UL)
  33#define SR_XS_CLEAN     _AC(0x00010000, UL)
  34#define SR_XS_DIRTY     _AC(0x00018000, UL)
  35
  36#ifdef CONFIG_RISCV_PRIV_1_9
  37#define SR_VM           _AC(0x1F000000, UL) /* Virtualization Management */
  38#define SR_VM_MODE_BARE _AC(0x00000000, UL) /* No translation or protection */
  39#define SR_VM_MODE_BB   _AC(0x01000000, UL) /* Single base-and-bound */
  40/* Separate instruction and data base-and-bound */
  41#define SR_VM_MODE_BBID _AC(0x02000000, UL)
  42#ifndef CONFIG_64BIT
  43#define SR_VM_MODE_32   _AC(0x08000000, UL)
  44#define SR_VM_MODE      SR_VM_MODE_32
  45#else
  46#define SR_VM_MODE_39   _AC(0x09000000, UL)
  47#define SR_VM_MODE_48   _AC(0x0A000000, UL)
  48#define SR_VM_MODE      SR_VM_MODE_39
  49#endif
  50#endif
  51
  52#ifndef CONFIG_64BIT
  53#define SR_SD           _AC(0x80000000, UL) /* FS/XS dirty */
  54#else
  55#define SR_SD           _AC(0x8000000000000000, UL) /* FS/XS dirty */
  56#endif
  57
  58/* SATP flags */
  59#ifndef CONFIG_RISCV_PRIV_1_9
  60#ifndef CONFIG_64BIT
  61#define SATP_PPN        _AC(0x003FFFFF, UL)
  62#define SATP_MODE_32    _AC(0x80000000, UL)
  63#define SATP_MODE       SATP_MODE_32
  64#else
  65#define SATP_PPN        _AC(0x00000FFFFFFFFFFF, UL)
  66#define SATP_MODE_39    _AC(0x8000000000000000, UL)
  67#define SATP_MODE       SATP_MODE_39
  68#endif
  69#endif
  70
  71/* SCAUSE */
  72#define SCAUSE_IRQ_FLAG         (_AC(1, UL) << (__riscv_xlen - 1))
  73
  74#define IRQ_U_SOFT              0
  75#define IRQ_S_SOFT              1
  76#define IRQ_M_SOFT              3
  77#define IRQ_U_TIMER             4
  78#define IRQ_S_TIMER             5
  79#define IRQ_M_TIMER             7
  80#define IRQ_U_EXT               8
  81#define IRQ_S_EXT               9
  82#define IRQ_M_EXT               11
  83
  84#define EXC_INST_MISALIGNED     0
  85#define EXC_INST_ACCESS         1
  86#define EXC_BREAKPOINT          3
  87#define EXC_LOAD_ACCESS         5
  88#define EXC_STORE_ACCESS        7
  89#define EXC_SYSCALL             8
  90#define EXC_INST_PAGE_FAULT     12
  91#define EXC_LOAD_PAGE_FAULT     13
  92#define EXC_STORE_PAGE_FAULT    15
  93
  94/* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */
  95#define MIE_MSIE                (_AC(0x1, UL) << IRQ_M_SOFT)
  96#define SIE_SSIE                (_AC(0x1, UL) << IRQ_S_SOFT)
  97#define SIE_STIE                (_AC(0x1, UL) << IRQ_S_TIMER)
  98#define SIE_SEIE                (_AC(0x1, UL) << IRQ_S_EXT)
  99
 100#define CSR_FCSR                0x003
 101#define CSR_CYCLE               0xc00
 102#define CSR_TIME                0xc01
 103#define CSR_INSTRET             0xc02
 104#define CSR_SSTATUS             0x100
 105#define CSR_SIE                 0x104
 106#define CSR_STVEC               0x105
 107#define CSR_SCOUNTEREN          0x106
 108#define CSR_SSCRATCH            0x140
 109#define CSR_SEPC                0x141
 110#define CSR_SCAUSE              0x142
 111#define CSR_STVAL               0x143
 112#define CSR_SIP                 0x144
 113#ifdef CONFIG_RISCV_PRIV_1_9
 114#define CSR_SPTBR               0x180
 115#else
 116#define CSR_SATP                0x180
 117#endif
 118#define CSR_MSTATUS             0x300
 119#define CSR_MISA                0x301
 120#define CSR_MIE                 0x304
 121#define CSR_MTVEC               0x305
 122#ifdef CONFIG_RISCV_PRIV_1_9
 123#define CSR_MUCOUNTEREN         0x320
 124#define CSR_MSCOUNTEREN         0x321
 125#define CSR_MHCOUNTEREN         0x322
 126#else
 127#define CSR_MCOUNTEREN          0x306
 128#endif
 129#define CSR_MSCRATCH            0x340
 130#define CSR_MEPC                0x341
 131#define CSR_MCAUSE              0x342
 132#define CSR_MTVAL               0x343
 133#define CSR_MIP                 0x344
 134#ifdef CONFIG_RISCV_PRIV_1_9
 135#define CSR_MBASE               0x380
 136#define CSR_MBOUND              0x381
 137#define CSR_MIBASE              0x382
 138#define CSR_MIBOUND             0x383
 139#define CSR_MDBASE              0x384
 140#define CSR_MDBOUND             0x385
 141#endif
 142#define CSR_CYCLEH              0xc80
 143#define CSR_TIMEH               0xc81
 144#define CSR_INSTRETH            0xc82
 145#define CSR_MHARTID             0xf14
 146
 147#ifndef __ASSEMBLY__
 148
 149#define csr_swap(csr, val)                                      \
 150({                                                              \
 151        unsigned long __v = (unsigned long)(val);               \
 152        __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
 153                              : "=r" (__v) : "rK" (__v)         \
 154                              : "memory");                      \
 155        __v;                                                    \
 156})
 157
 158#define csr_read(csr)                                           \
 159({                                                              \
 160        register unsigned long __v;                             \
 161        __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)        \
 162                              : "=r" (__v) :                    \
 163                              : "memory");                      \
 164        __v;                                                    \
 165})
 166
 167#define csr_write(csr, val)                                     \
 168({                                                              \
 169        unsigned long __v = (unsigned long)(val);               \
 170        __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"     \
 171                              : : "rK" (__v)                    \
 172                              : "memory");                      \
 173})
 174
 175#define csr_read_set(csr, val)                                  \
 176({                                                              \
 177        unsigned long __v = (unsigned long)(val);               \
 178        __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
 179                              : "=r" (__v) : "rK" (__v)         \
 180                              : "memory");                      \
 181        __v;                                                    \
 182})
 183
 184#define csr_set(csr, val)                                       \
 185({                                                              \
 186        unsigned long __v = (unsigned long)(val);               \
 187        __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"     \
 188                              : : "rK" (__v)                    \
 189                              : "memory");                      \
 190})
 191
 192#define csr_read_clear(csr, val)                                \
 193({                                                              \
 194        unsigned long __v = (unsigned long)(val);               \
 195        __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
 196                              : "=r" (__v) : "rK" (__v)         \
 197                              : "memory");                      \
 198        __v;                                                    \
 199})
 200
 201#define csr_clear(csr, val)                                     \
 202({                                                              \
 203        unsigned long __v = (unsigned long)(val);               \
 204        __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"     \
 205                              : : "rK" (__v)                    \
 206                              : "memory");                      \
 207})
 208
 209#endif /* __ASSEMBLY__ */
 210
 211#endif /* _ASM_RISCV_CSR_H */
 212