LXR uboot/board/egnite/ethernut5/ethernut5.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2011
   4 * egnite GmbH <info@egnite.de>
   5 *
   6 * (C) Copyright 2010
   7 * Ole Reinhardt <ole.reinhardt@thermotemp.de>
   8 */
   9
  10/*
  11 * Ethernut 5 general board support
  12 *
  13 * Ethernut is an open source hardware and software project for
  14 * embedded Ethernet devices. Hardware layouts and CAD files are
  15 * freely available under BSD-like license.
  16 *
  17 * Ethernut 5 is the first member of the Ethernut board family
  18 * with U-Boot and Linux support. This implementation is based
  19 * on the original work done by Ole Reinhardt, but heavily modified
  20 * to support additional features and the latest board revision 5.0F.
  21 *
  22 * Main board components are by default:
  23 *
  24 * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash
  25 * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM
  26 * 512 MBytes Micron MT29F4G08ABADA NAND Flash
  27 * 4 MBytes Atmel AT45DB321D DataFlash
  28 * SMSC LAN8710 Ethernet PHY
  29 * Atmel ATmega168 MCU used for power management
  30 * Linear Technology LTC4411 PoE controller
  31 *
  32 * U-Boot relevant board interfaces are:
  33 *
  34 * 100 Mbit Ethernet with IEEE 802.3af PoE
  35 * RS-232 serial port
  36 * USB host and device
  37 * MMC/SD-Card slot
  38 * Expansion port with I2C, SPI and more...
  39 *
  40 * Typically the U-Boot image is loaded from serial DataFlash into
  41 * SDRAM by the samboot boot loader, which is located in internal
  42 * NOR Flash and provides all essential initializations like CPU
  43 * and peripheral clocks and, of course, the SDRAM configuration.
  44 *
  45 * For testing purposes it is also possibly to directly transfer
  46 * the image into SDRAM via JTAG. A tested configuration exists
  47 * for the Turtelizer 2 hardware dongle and the OpenOCD software.
  48 * In this case the latter will do the basic hardware configuration
  49 * via its reset-init script.
  50 *
  51 * For additional information visit the project home page at
  52 * http://www.ethernut.de/
  53 */
  54
  55#include <common.h>
  56#include <init.h>
  57#include <net.h>
  58#include <netdev.h>
  59#include <miiphy.h>
  60#include <i2c.h>
  61#include <mmc.h>
  62#include <atmel_mci.h>
  63#include <asm/global_data.h>
  64
  65#include <asm/arch/at91sam9260.h>
  66#include <asm/arch/at91sam9260_matrix.h>
  67#include <asm/arch/at91sam9_smc.h>
  68#include <asm/arch/at91_common.h>
  69#include <asm/arch/clk.h>
  70#include <asm/arch/gpio.h>
  71#include <asm/io.h>
  72#include <asm/gpio.h>
  73
  74#include "ethernut5_pwrman.h"
  75
  76DECLARE_GLOBAL_DATA_PTR;
  77
  78/*
  79 * This is called last during early initialization. Most of the basic
  80 * hardware interfaces are up and running.
  81 *
  82 * The SDRAM hardware has been configured by the first stage boot loader.
  83 * We only need to announce its size, using u-boot's memory check.
  84 */
  85int dram_init(void)
  86{
  87        gd->ram_size = get_ram_size(
  88                        (void *)CONFIG_SYS_SDRAM_BASE,
  89                        CONFIG_SYS_SDRAM_SIZE);
  90        return 0;
  91}
  92
  93#ifdef CONFIG_CMD_NAND
  94static void ethernut5_nand_hw_init(void)
  95{
  96        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  97        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  98        unsigned long csa;
  99
 100        /* Assign CS3 to NAND/SmartMedia Interface */
 101        csa = readl(&matrix->ebicsa);
 102        csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
 103        writel(csa, &matrix->ebicsa);
 104
 105        /* Configure SMC CS3 for NAND/SmartMedia */
 106        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
 107                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 108                &smc->cs[3].setup);
 109        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
 110                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
 111                &smc->cs[3].pulse);
 112        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
 113                &smc->cs[3].cycle);
 114        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 115                AT91_SMC_MODE_EXNW_DISABLE |
 116                AT91_SMC_MODE_DBW_8 |
 117                AT91_SMC_MODE_TDF_CYCLE(2),
 118                &smc->cs[3].mode);
 119
 120#ifdef CONFIG_SYS_NAND_READY_PIN
 121        /* Ready pin is optional. */
 122        at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 123#endif
 124        gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 125}
 126#endif
 127
 128/*
 129 * This is called first during late initialization.
 130 */
 131int board_init(void)
 132{
 133        at91_periph_clk_enable(ATMEL_ID_PIOA);
 134        at91_periph_clk_enable(ATMEL_ID_PIOB);
 135        at91_periph_clk_enable(ATMEL_ID_PIOC);
 136
 137        /* Set adress of boot parameters. */
 138        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 139        /* Initialize UARTs and power management. */
 140        ethernut5_power_init();
 141#ifdef CONFIG_CMD_NAND
 142        ethernut5_nand_hw_init();
 143#endif
 144        return 0;
 145}
 146
 147#ifdef CONFIG_MACB
 148/*
 149 * This is optionally called last during late initialization.
 150 */
 151int board_eth_init(struct bd_info *bis)
 152{
 153        const char *devname;
 154        unsigned short mode;
 155
 156        at91_periph_clk_enable(ATMEL_ID_EMAC0);
 157
 158        /* Need to reset PHY via power management. */
 159        ethernut5_phy_reset();
 160        /* Set peripheral pins. */
 161        at91_macb_hw_init();
 162        /* Basic EMAC initialization. */
 163        if (macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, CONFIG_PHY_ID))
 164                return -1;
 165        /*
 166         * Early board revisions have a pull-down at the PHY's MODE0
 167         * strap pin, which forces the PHY into power down. Here we
 168         * switch to all-capable mode.
 169         */
 170        devname = miiphy_get_current_dev();
 171        if (miiphy_read(devname, 0, 18, &mode) == 0) {
 172                /* Set mode[2:0] to 0b111. */
 173                mode |= 0x00E0;
 174                miiphy_write(devname, 0, 18, mode);
 175                /* Soft reset overrides strap pins. */
 176                miiphy_write(devname, 0, MII_BMCR, BMCR_RESET);
 177        }
 178        /* Sync environment with network devices, needed for nfsroot. */
 179        return eth_init();
 180}
 181#endif
 182
 183#ifdef CONFIG_GENERIC_ATMEL_MCI
 184int board_mmc_init(struct bd_info *bd)
 185{
 186        at91_periph_clk_enable(ATMEL_ID_MCI);
 187
 188        /* Initialize MCI hardware. */
 189        at91_mci_hw_init();
 190        /* Register the device. */
 191        return atmel_mci_init((void *)ATMEL_BASE_MCI);
 192}
 193
 194int board_mmc_getcd(struct mmc *mmc)
 195{
 196        return !at91_get_pio_value(CONFIG_SYS_MMC_CD_PIN);
 197}
 198#endif
 199