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10#include <common.h>
11#include <env.h>
12#include <errno.h>
13#include <init.h>
14#include <net.h>
15#include <serial.h>
16#include <asm/global_data.h>
17#include <linux/libfdt.h>
18#include <spl.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/hardware.h>
21#include <asm/arch/omap.h>
22#include <asm/arch/ddr_defs.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/mmc_host_def.h>
26#include <asm/arch/sys_proto.h>
27#include <asm/arch/mem.h>
28#include <asm/arch/mux.h>
29#include <asm/io.h>
30#include <asm/emif.h>
31#include <asm/gpio.h>
32#include <i2c.h>
33#include <miiphy.h>
34#include <cpsw.h>
35#include <power/tps65910.h>
36#include <watchdog.h>
37#include "board.h"
38
39DECLARE_GLOBAL_DATA_PTR;
40
41
42#define DIP_S1 44
43#define MPCIE_SW 100
44
45static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
46
47static int baltos_set_console(void)
48{
49 int val, i, dips = 0;
50 char buf[7];
51
52 for (i = 0; i < 4; i++) {
53 sprintf(buf, "dip_s%d", i + 1);
54
55 if (gpio_request(DIP_S1 + i, buf)) {
56 printf("failed to export GPIO %d\n", DIP_S1 + i);
57 return 0;
58 }
59
60 if (gpio_direction_input(DIP_S1 + i)) {
61 printf("failed to set GPIO %d direction\n", DIP_S1 + i);
62 return 0;
63 }
64
65 val = gpio_get_value(DIP_S1 + i);
66 dips |= val << i;
67 }
68
69 printf("DIPs: 0x%1x\n", (~dips) & 0xf);
70
71 if ((dips & 0xf) == 0xe)
72 env_set("console", "ttyUSB0,115200n8");
73
74 return 0;
75}
76
77static int read_eeprom(BSP_VS_HWPARAM *header)
78{
79 i2c_set_bus_num(1);
80
81
82 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
83 puts("Could not probe the EEPROM; something fundamentally "
84 "wrong on the I2C bus.\n");
85 return -ENODEV;
86 }
87
88
89 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
90 sizeof(BSP_VS_HWPARAM))) {
91 puts("Could not read the EEPROM; something fundamentally"
92 " wrong on the I2C bus.\n");
93 return -EIO;
94 }
95
96 if (header->Magic != 0xDEADBEEF) {
97
98 printf("Incorrect magic number (0x%x) in EEPROM\n",
99 header->Magic);
100
101
102 header->SystemId = 211;
103 header->MAC1[0] = 0x00;
104 header->MAC1[1] = 0x00;
105 header->MAC1[2] = 0x00;
106 header->MAC1[3] = 0x00;
107 header->MAC1[4] = 0x00;
108 header->MAC1[5] = 0x01;
109
110 header->MAC2[0] = 0x00;
111 header->MAC2[1] = 0x00;
112 header->MAC2[2] = 0x00;
113 header->MAC2[3] = 0x00;
114 header->MAC2[4] = 0x00;
115 header->MAC2[5] = 0x02;
116
117 header->MAC3[0] = 0x00;
118 header->MAC3[1] = 0x00;
119 header->MAC3[2] = 0x00;
120 header->MAC3[3] = 0x00;
121 header->MAC3[4] = 0x00;
122 header->MAC3[5] = 0x03;
123 }
124
125 return 0;
126}
127
128#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
129
130static const struct ddr_data ddr3_baltos_data = {
131 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
132 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
133 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
134 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
135};
136
137static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
138 .cmd0csratio = MT41K256M16HA125E_RATIO,
139 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
140
141 .cmd1csratio = MT41K256M16HA125E_RATIO,
142 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
143
144 .cmd2csratio = MT41K256M16HA125E_RATIO,
145 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
146};
147
148static struct emif_regs ddr3_baltos_emif_reg_data = {
149 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
150 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
151 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
152 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
153 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
154 .zq_config = MT41K256M16HA125E_ZQ_CFG,
155 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
156};
157
158#ifdef CONFIG_SPL_OS_BOOT
159int spl_start_uboot(void)
160{
161
162 return (serial_tstc() && serial_getc() == 'c');
163}
164#endif
165
166#define OSC (V_OSCK/1000000)
167const struct dpll_params dpll_ddr = {
168 266, OSC-1, 1, -1, -1, -1, -1};
169const struct dpll_params dpll_ddr_evm_sk = {
170 303, OSC-1, 1, -1, -1, -1, -1};
171const struct dpll_params dpll_ddr_baltos = {
172 400, OSC-1, 1, -1, -1, -1, -1};
173
174void am33xx_spl_board_init(void)
175{
176 int mpu_vdd;
177 int sil_rev;
178
179
180 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
181
182
183
184
185
186
187
188 i2c_set_bus_num(1);
189
190 printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED);
191
192 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
193 puts("i2c: cannot access TPS65910\n");
194 return;
195 }
196
197
198
199
200
201 sil_rev = readl(&cdev->deviceid) >> 28;
202 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
203 dpll_mpu_opp100.m);
204
205
206 tps65910_set_i2c_control();
207
208
209 if (tps65910_voltage_update(MPU, mpu_vdd))
210 return;
211
212
213 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
214 return;
215
216
217 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
218
219
220 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
221
222 writel(0x000010ff, PRM_DEVICE_INST + 4);
223}
224
225const struct dpll_params *get_dpll_ddr_params(void)
226{
227 enable_i2c1_pin_mux();
228 i2c_set_bus_num(1);
229
230 return &dpll_ddr_baltos;
231}
232
233void set_uart_mux_conf(void)
234{
235 enable_uart0_pin_mux();
236}
237
238void set_mux_conf_regs(void)
239{
240 enable_board_pin_mux();
241}
242
243const struct ctrl_ioregs ioregs_baltos = {
244 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
245 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
246 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
247 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
248 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
249};
250
251void sdram_init(void)
252{
253 config_ddr(400, &ioregs_baltos,
254 &ddr3_baltos_data,
255 &ddr3_baltos_cmd_ctrl_data,
256 &ddr3_baltos_emif_reg_data, 0);
257}
258#endif
259
260
261
262
263int board_init(void)
264{
265#if defined(CONFIG_HW_WATCHDOG)
266 hw_watchdog_init();
267#endif
268
269 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
270#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
271 gpmc_init();
272#endif
273 return 0;
274}
275
276int ft_board_setup(void *blob, struct bd_info *bd)
277{
278 int node, ret;
279 unsigned char mac_addr[6];
280 BSP_VS_HWPARAM header;
281
282
283 if (read_eeprom(&header))
284 return 0;
285
286
287 mac_addr[0] = header.MAC1[0];
288 mac_addr[1] = header.MAC1[1];
289 mac_addr[2] = header.MAC1[2];
290 mac_addr[3] = header.MAC1[3];
291 mac_addr[4] = header.MAC1[4];
292 mac_addr[5] = header.MAC1[5];
293
294
295 node = fdt_path_offset(blob, "ethernet0");
296 if (node < 0) {
297 printf("no ethernet0 path offset\n");
298 return -ENODEV;
299 }
300
301 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
302 if (ret) {
303 printf("error setting mac-address property\n");
304 return -ENODEV;
305 }
306
307
308 mac_addr[0] = header.MAC2[0];
309 mac_addr[1] = header.MAC2[1];
310 mac_addr[2] = header.MAC2[2];
311 mac_addr[3] = header.MAC2[3];
312 mac_addr[4] = header.MAC2[4];
313 mac_addr[5] = header.MAC2[5];
314
315 node = fdt_path_offset(blob, "ethernet1");
316 if (node < 0) {
317 printf("no ethernet1 path offset\n");
318 return -ENODEV;
319 }
320
321 ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
322 if (ret) {
323 printf("error setting mac-address property\n");
324 return -ENODEV;
325 }
326
327 printf("\nFDT was successfully setup\n");
328
329 return 0;
330}
331
332static struct module_pin_mux pcie_sw_pin_mux[] = {
333 {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},
334 {-1},
335};
336
337static struct module_pin_mux dip_pin_mux[] = {
338 {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},
339 {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )},
340 {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )},
341 {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )},
342 {-1},
343};
344
345#ifdef CONFIG_BOARD_LATE_INIT
346int board_late_init(void)
347{
348#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
349 BSP_VS_HWPARAM header;
350 char model[4];
351
352
353 if (read_eeprom(&header)) {
354 strcpy(model, "211");
355 } else {
356 sprintf(model, "%d", header.SystemId);
357 if (header.SystemId == 215) {
358 configure_module_pin_mux(dip_pin_mux);
359 baltos_set_console();
360 }
361 }
362
363
364 configure_module_pin_mux(pcie_sw_pin_mux);
365 if (gpio_request(MPCIE_SW, "mpcie_sw")) {
366 printf("failed to export GPIO %d\n", MPCIE_SW);
367 return -ENODEV;
368 }
369 if (gpio_direction_output(MPCIE_SW, 1)) {
370 printf("failed to set GPIO %d direction\n", MPCIE_SW);
371 return -ENODEV;
372 }
373
374 env_set("board_name", model);
375#endif
376
377 return 0;
378}
379#endif
380
381#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
382 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
383static void cpsw_control(int enabled)
384{
385
386
387 return;
388}
389
390static struct cpsw_slave_data cpsw_slaves[] = {
391 {
392 .slave_reg_ofs = 0x208,
393 .sliver_reg_ofs = 0xd80,
394 .phy_addr = 0,
395 },
396 {
397 .slave_reg_ofs = 0x308,
398 .sliver_reg_ofs = 0xdc0,
399 .phy_addr = 7,
400 },
401};
402
403static struct cpsw_platform_data cpsw_data = {
404 .mdio_base = CPSW_MDIO_BASE,
405 .cpsw_base = CPSW_BASE,
406 .mdio_div = 0xff,
407 .channels = 8,
408 .cpdma_reg_ofs = 0x800,
409 .slaves = 2,
410 .slave_data = cpsw_slaves,
411 .active_slave = 1,
412 .ale_reg_ofs = 0xd00,
413 .ale_entries = 1024,
414 .host_port_reg_ofs = 0x108,
415 .hw_stats_reg_ofs = 0x900,
416 .bd_ram_ofs = 0x2000,
417 .mac_control = (1 << 5),
418 .control = cpsw_control,
419 .host_port_num = 0,
420 .version = CPSW_CTRL_VERSION_2,
421};
422#endif
423
424#if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
425 && defined(CONFIG_SPL_BUILD)) || \
426 ((defined(CONFIG_DRIVER_TI_CPSW) || \
427 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
428 !defined(CONFIG_SPL_BUILD))
429int board_eth_init(struct bd_info *bis)
430{
431 int rv, n = 0;
432 uint8_t mac_addr[6];
433 uint32_t mac_hi, mac_lo;
434
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439
440
441
442
443 mac_lo = readl(&cdev->macid1l);
444 mac_hi = readl(&cdev->macid1h);
445 mac_addr[0] = mac_hi & 0xFF;
446 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
447 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
448 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
449 mac_addr[4] = mac_lo & 0xFF;
450 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
451
452#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
453 (defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
454 if (!env_get("ethaddr")) {
455 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
456
457 if (is_valid_ethaddr(mac_addr))
458 eth_env_set_enetaddr("ethaddr", mac_addr);
459 }
460
461#ifdef CONFIG_DRIVER_TI_CPSW
462 writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
463 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
464 rv = cpsw_register(&cpsw_data);
465 if (rv < 0)
466 printf("Error %d registering CPSW switch\n", rv);
467 else
468 n += rv;
469#endif
470
471
472
473
474
475
476
477
478#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
479#define AR8051_PHY_DEBUG_DATA_REG 0x1e
480#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
481#define AR8051_RGMII_TX_CLK_DLY 0x100
482 const char *devname;
483 devname = miiphy_get_current_dev();
484
485 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
486 AR8051_DEBUG_RGMII_CLK_DLY_REG);
487 miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
488 AR8051_RGMII_TX_CLK_DLY);
489#endif
490 return n;
491}
492#endif
493
