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14#include <common.h>
15#include <clk.h>
16#include <cpu_func.h>
17#include <dm.h>
18#include <log.h>
19#include <malloc.h>
20#include <miiphy.h>
21#include <net.h>
22#include <wait_bit.h>
23#include <asm/cache.h>
24#include <dm/device_compat.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/iopoll.h>
28
29#include "ftgmac100.h"
30
31
32#define ETH_ZLEN 60
33
34
35#define FTGMAC100_RBSR_DEFAULT 0x640
36
37
38#define PKTBUFSTX 4
39
40
41#define FTGMAC100_TX_TIMEOUT_MS 1000
42
43
44#define FTGMAC100_MDIO_TIMEOUT_USEC 10000
45
46
47
48
49
50
51#define MDC_CYCTHR 0x34
52
53
54
55
56enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
59};
60
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76
77
78struct ftgmac100_data {
79 struct ftgmac100 *iobase;
80
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
83 int tx_index;
84 int rx_index;
85
86 u32 phy_addr;
87 struct phy_device *phydev;
88 struct mii_dev *bus;
89 u32 phy_mode;
90 u32 max_speed;
91
92 struct clk_bulk clks;
93
94
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
97};
98
99
100
101
102static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
103 int reg_addr)
104{
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
107 int phycr;
108 int data;
109 int ret;
110
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
116
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
120 if (ret) {
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 bus->name, phy_addr, reg_addr);
123 return ret;
124 }
125
126 data = readl(&ftgmac100->phydata);
127
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
129}
130
131static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
133{
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
136 int phycr;
137 int data;
138 int ret;
139
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
145
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
148
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
152 if (ret) {
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 bus->name, phy_addr, reg_addr);
155 }
156
157 return ret;
158}
159
160static int ftgmac100_mdio_init(struct udevice *dev)
161{
162 struct ftgmac100_data *priv = dev_get_priv(dev);
163 struct mii_dev *bus;
164 int ret;
165
166 bus = mdio_alloc();
167 if (!bus)
168 return -ENOMEM;
169
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
172 bus->priv = priv;
173
174 ret = mdio_register_seq(bus, dev_seq(dev));
175 if (ret) {
176 free(bus);
177 return ret;
178 }
179
180 priv->bus = bus;
181
182 return 0;
183}
184
185static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
186{
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
189 u32 maccr;
190
191 if (!phydev->link) {
192 dev_err(phydev->dev, "No link\n");
193 return -EREMOTEIO;
194 }
195
196
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
201
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
204
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
207
208 if (phydev->duplex)
209 maccr |= FTGMAC100_MACCR_FULLDUP;
210
211
212 writel(maccr, &ftgmac100->maccr);
213
214 return 0;
215}
216
217static int ftgmac100_phy_init(struct udevice *dev)
218{
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
221 int ret;
222
223 if (IS_ENABLED(CONFIG_DM_MDIO))
224 phydev = dm_eth_phy_connect(dev);
225 else
226 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
227
228 if (!phydev)
229 return -ENODEV;
230
231 phydev->supported &= PHY_GBIT_FEATURES;
232 if (priv->max_speed) {
233 ret = phy_set_supported(phydev, priv->max_speed);
234 if (ret)
235 return ret;
236 }
237 phydev->advertising = phydev->supported;
238 priv->phydev = phydev;
239 phy_config(phydev);
240
241 return 0;
242}
243
244
245
246
247static void ftgmac100_reset(struct ftgmac100_data *priv)
248{
249 struct ftgmac100 *ftgmac100 = priv->iobase;
250
251 debug("%s()\n", __func__);
252
253 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
254
255 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
256 ;
257}
258
259
260
261
262static int ftgmac100_set_mac(struct ftgmac100_data *priv,
263 const unsigned char *mac)
264{
265 struct ftgmac100 *ftgmac100 = priv->iobase;
266 unsigned int maddr = mac[0] << 8 | mac[1];
267 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
268
269 debug("%s(%x %x)\n", __func__, maddr, laddr);
270
271 writel(maddr, &ftgmac100->mac_madr);
272 writel(laddr, &ftgmac100->mac_ladr);
273
274 return 0;
275}
276
277
278
279
280static int ftgmac100_get_mac(struct ftgmac100_data *priv,
281 unsigned char *mac)
282{
283 struct ftgmac100 *ftgmac100 = priv->iobase;
284 unsigned int maddr = readl(&ftgmac100->mac_madr);
285 unsigned int laddr = readl(&ftgmac100->mac_ladr);
286
287 debug("%s(%x %x)\n", __func__, maddr, laddr);
288
289 mac[0] = (maddr >> 8) & 0xff;
290 mac[1] = maddr & 0xff;
291 mac[2] = (laddr >> 24) & 0xff;
292 mac[3] = (laddr >> 16) & 0xff;
293 mac[4] = (laddr >> 8) & 0xff;
294 mac[5] = laddr & 0xff;
295
296 return 0;
297}
298
299
300
301
302static void ftgmac100_stop(struct udevice *dev)
303{
304 struct ftgmac100_data *priv = dev_get_priv(dev);
305 struct ftgmac100 *ftgmac100 = priv->iobase;
306
307 debug("%s()\n", __func__);
308
309 writel(0, &ftgmac100->maccr);
310
311 phy_shutdown(priv->phydev);
312}
313
314static int ftgmac100_start(struct udevice *dev)
315{
316 struct eth_pdata *plat = dev_get_plat(dev);
317 struct ftgmac100_data *priv = dev_get_priv(dev);
318 struct ftgmac100 *ftgmac100 = priv->iobase;
319 struct phy_device *phydev = priv->phydev;
320 unsigned int maccr;
321 ulong start, end;
322 int ret;
323 int i;
324
325 debug("%s()\n", __func__);
326
327 ftgmac100_reset(priv);
328
329
330 ftgmac100_set_mac(priv, plat->enetaddr);
331
332
333 writel(0, &ftgmac100->ier);
334
335
336 priv->tx_index = 0;
337 priv->rx_index = 0;
338
339 for (i = 0; i < PKTBUFSTX; i++) {
340 priv->txdes[i].txdes3 = 0;
341 priv->txdes[i].txdes0 = 0;
342 }
343 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
344
345 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
346 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
347 flush_dcache_range(start, end);
348
349 for (i = 0; i < PKTBUFSRX; i++) {
350 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
351 priv->rxdes[i].rxdes0 = 0;
352 }
353 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
354
355 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
356 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
357 flush_dcache_range(start, end);
358
359
360 writel((u32)priv->txdes, &ftgmac100->txr_badr);
361
362
363 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
364
365
366 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
367
368
369 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
370
371
372 maccr = FTGMAC100_MACCR_TXMAC_EN |
373 FTGMAC100_MACCR_RXMAC_EN |
374 FTGMAC100_MACCR_TXDMA_EN |
375 FTGMAC100_MACCR_RXDMA_EN |
376 FTGMAC100_MACCR_CRC_APD |
377 FTGMAC100_MACCR_FULLDUP |
378 FTGMAC100_MACCR_RX_RUNT |
379 FTGMAC100_MACCR_RX_BROADPKT;
380
381 writel(maccr, &ftgmac100->maccr);
382
383 ret = phy_startup(phydev);
384 if (ret) {
385 dev_err(phydev->dev, "Could not start PHY\n");
386 return ret;
387 }
388
389 ret = ftgmac100_phy_adjust_link(priv);
390 if (ret) {
391 dev_err(phydev->dev, "Could not adjust link\n");
392 return ret;
393 }
394
395 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
396 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
397
398 return 0;
399}
400
401static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
402{
403 struct ftgmac100_data *priv = dev_get_priv(dev);
404 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
405 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
406 ulong des_end = des_start +
407 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
408
409
410 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
411 flush_dcache_range(des_start, des_end);
412
413
414 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
415
416 return 0;
417}
418
419
420
421
422static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
423{
424 struct ftgmac100_data *priv = dev_get_priv(dev);
425 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
426 unsigned short rxlen;
427 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
428 ulong des_end = des_start +
429 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
430 ulong data_start = curr_des->rxdes3;
431 ulong data_end;
432
433 invalidate_dcache_range(des_start, des_end);
434
435 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
436 return -EAGAIN;
437
438 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
439 FTGMAC100_RXDES0_CRC_ERR |
440 FTGMAC100_RXDES0_FTL |
441 FTGMAC100_RXDES0_RUNT |
442 FTGMAC100_RXDES0_RX_ODD_NB)) {
443 return -EAGAIN;
444 }
445
446 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
447
448 debug("%s(): RX buffer %d, %x received\n",
449 __func__, priv->rx_index, rxlen);
450
451
452 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
453 invalidate_dcache_range(data_start, data_end);
454 *packetp = (uchar *)data_start;
455
456 return rxlen;
457}
458
459static u32 ftgmac100_read_txdesc(const void *desc)
460{
461 const struct ftgmac100_txdes *txdes = desc;
462 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
463 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
464
465 invalidate_dcache_range(des_start, des_end);
466
467 return txdes->txdes0;
468}
469
470BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
471
472
473
474
475static int ftgmac100_send(struct udevice *dev, void *packet, int length)
476{
477 struct ftgmac100_data *priv = dev_get_priv(dev);
478 struct ftgmac100 *ftgmac100 = priv->iobase;
479 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
480 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
481 ulong des_end = des_start +
482 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
483 ulong data_start;
484 ulong data_end;
485 int rc;
486
487 invalidate_dcache_range(des_start, des_end);
488
489 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
490 dev_err(dev, "no TX descriptor available\n");
491 return -EPERM;
492 }
493
494 debug("%s(%x, %x)\n", __func__, (int)packet, length);
495
496 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
497
498 curr_des->txdes3 = (unsigned int)packet;
499
500
501 data_start = curr_des->txdes3;
502 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
503 flush_dcache_range(data_start, data_end);
504
505
506 curr_des->txdes0 &= priv->txdes0_edotr_mask;
507 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
508 FTGMAC100_TXDES0_LTS |
509 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
510 FTGMAC100_TXDES0_TXDMA_OWN ;
511
512
513 flush_dcache_range(des_start, des_end);
514
515
516 writel(1, &ftgmac100->txpd);
517
518 rc = wait_for_bit_ftgmac100_txdone(curr_des,
519 FTGMAC100_TXDES0_TXDMA_OWN, false,
520 FTGMAC100_TX_TIMEOUT_MS, true);
521 if (rc)
522 return rc;
523
524 debug("%s(): packet sent\n", __func__);
525
526
527 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
528
529 return 0;
530}
531
532static int ftgmac100_write_hwaddr(struct udevice *dev)
533{
534 struct eth_pdata *pdata = dev_get_plat(dev);
535 struct ftgmac100_data *priv = dev_get_priv(dev);
536
537 return ftgmac100_set_mac(priv, pdata->enetaddr);
538}
539
540static int ftgmac_read_hwaddr(struct udevice *dev)
541{
542 struct eth_pdata *pdata = dev_get_plat(dev);
543 struct ftgmac100_data *priv = dev_get_priv(dev);
544
545 return ftgmac100_get_mac(priv, pdata->enetaddr);
546}
547
548static int ftgmac100_of_to_plat(struct udevice *dev)
549{
550 struct eth_pdata *pdata = dev_get_plat(dev);
551 struct ftgmac100_data *priv = dev_get_priv(dev);
552
553 pdata->iobase = dev_read_addr(dev);
554
555 pdata->phy_interface = dev_read_phy_mode(dev);
556 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
557 return -EINVAL;
558
559 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
560
561 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
562 priv->rxdes0_edorr_mask = BIT(30);
563 priv->txdes0_edotr_mask = BIT(30);
564 } else {
565 priv->rxdes0_edorr_mask = BIT(15);
566 priv->txdes0_edotr_mask = BIT(15);
567 }
568
569 return clk_get_bulk(dev, &priv->clks);
570}
571
572static int ftgmac100_probe(struct udevice *dev)
573{
574 struct eth_pdata *pdata = dev_get_plat(dev);
575 struct ftgmac100_data *priv = dev_get_priv(dev);
576 int ret;
577
578 priv->iobase = (struct ftgmac100 *)pdata->iobase;
579 priv->phy_mode = pdata->phy_interface;
580 priv->max_speed = pdata->max_speed;
581 priv->phy_addr = 0;
582
583#ifdef CONFIG_PHY_ADDR
584 priv->phy_addr = CONFIG_PHY_ADDR;
585#endif
586
587 ret = clk_enable_bulk(&priv->clks);
588 if (ret)
589 goto out;
590
591
592
593
594
595 if (!IS_ENABLED(CONFIG_DM_MDIO)) {
596 ret = ftgmac100_mdio_init(dev);
597 if (ret) {
598 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
599 goto out;
600 }
601 }
602
603 ret = ftgmac100_phy_init(dev);
604 if (ret) {
605 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
606 goto out;
607 }
608
609 ftgmac_read_hwaddr(dev);
610
611out:
612 if (ret)
613 clk_release_bulk(&priv->clks);
614
615 return ret;
616}
617
618static int ftgmac100_remove(struct udevice *dev)
619{
620 struct ftgmac100_data *priv = dev_get_priv(dev);
621
622 free(priv->phydev);
623 mdio_unregister(priv->bus);
624 mdio_free(priv->bus);
625 clk_release_bulk(&priv->clks);
626
627 return 0;
628}
629
630static const struct eth_ops ftgmac100_ops = {
631 .start = ftgmac100_start,
632 .send = ftgmac100_send,
633 .recv = ftgmac100_recv,
634 .stop = ftgmac100_stop,
635 .free_pkt = ftgmac100_free_pkt,
636 .write_hwaddr = ftgmac100_write_hwaddr,
637};
638
639static const struct udevice_id ftgmac100_ids[] = {
640 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
641 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
642 { .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
643 { }
644};
645
646U_BOOT_DRIVER(ftgmac100) = {
647 .name = "ftgmac100",
648 .id = UCLASS_ETH,
649 .of_match = ftgmac100_ids,
650 .of_to_plat = ftgmac100_of_to_plat,
651 .probe = ftgmac100_probe,
652 .remove = ftgmac100_remove,
653 .ops = &ftgmac100_ops,
654 .priv_auto = sizeof(struct ftgmac100_data),
655 .plat_auto = sizeof(struct eth_pdata),
656 .flags = DM_FLAG_ALLOC_PRIV_DMA,
657};
658
