uboot/drivers/video/bridge/anx6345.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
   4 */
   5
   6#include <common.h>
   7#include <dm.h>
   8#include <errno.h>
   9#include <i2c.h>
  10#include <edid.h>
  11#include <log.h>
  12#include <video_bridge.h>
  13#include <linux/delay.h>
  14#include "../anx98xx-edp.h"
  15
  16#define DP_MAX_LINK_RATE                0x001
  17#define DP_MAX_LANE_COUNT               0x002
  18#define DP_MAX_LANE_COUNT_MASK          0x1f
  19
  20struct anx6345_priv {
  21        u8 edid[EDID_SIZE];
  22};
  23
  24static int anx6345_write(struct udevice *dev, unsigned int addr_off,
  25                         unsigned char reg_addr, unsigned char value)
  26{
  27        uint8_t buf[2];
  28        struct i2c_msg msg;
  29        int ret;
  30
  31        msg.addr = addr_off;
  32        msg.flags = 0;
  33        buf[0] = reg_addr;
  34        buf[1] = value;
  35        msg.buf = buf;
  36        msg.len = 2;
  37        ret = dm_i2c_xfer(dev, &msg, 1);
  38        if (ret) {
  39                debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
  40                      __func__, reg_addr, value, ret);
  41                return ret;
  42        }
  43
  44        return 0;
  45}
  46
  47static int anx6345_read(struct udevice *dev, unsigned int addr_off,
  48                        unsigned char reg_addr, unsigned char *value)
  49{
  50        uint8_t addr, val;
  51        struct i2c_msg msg[2];
  52        int ret;
  53
  54        msg[0].addr = addr_off;
  55        msg[0].flags = 0;
  56        addr = reg_addr;
  57        msg[0].buf = &addr;
  58        msg[0].len = 1;
  59        msg[1].addr = addr_off;
  60        msg[1].flags = I2C_M_RD;
  61        msg[1].buf = &val;
  62        msg[1].len = 1;
  63        ret = dm_i2c_xfer(dev, msg, 2);
  64        if (ret) {
  65                debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
  66                      __func__, (int)reg_addr, value, ret);
  67                return ret;
  68        }
  69        *value = val;
  70
  71        return 0;
  72}
  73
  74static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
  75                            unsigned char value)
  76{
  77        struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
  78
  79        return anx6345_write(dev, chip->chip_addr, reg_addr, value);
  80}
  81
  82static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
  83                           unsigned char *value)
  84{
  85        struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
  86
  87        return anx6345_read(dev, chip->chip_addr, reg_addr, value);
  88}
  89
  90static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
  91                            unsigned char value)
  92{
  93        struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
  94
  95        return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
  96}
  97
  98static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
  99                           unsigned char *value)
 100{
 101        struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
 102
 103        return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
 104}
 105
 106static int anx6345_set_backlight(struct udevice *dev, int percent)
 107{
 108        return -ENOSYS;
 109}
 110
 111static int anx6345_aux_wait(struct udevice *dev)
 112{
 113        int ret = -ETIMEDOUT;
 114        u8 v;
 115        int retries = 1000;
 116
 117        do {
 118                anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
 119                if (!(v & ANX9804_AUX_EN)) {
 120                        ret = 0;
 121                        break;
 122                }
 123                udelay(100);
 124        } while (retries--);
 125
 126        if (ret) {
 127                debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
 128                return ret;
 129        }
 130
 131        ret = -ETIMEDOUT;
 132        retries = 1000;
 133        do {
 134                anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
 135                if (v & ANX9804_RPLY_RECEIV) {
 136                        ret = 0;
 137                        break;
 138                }
 139                udelay(100);
 140        } while (retries--);
 141
 142        if (ret) {
 143                debug("%s: timed out waiting to receive reply\n", __func__);
 144                return ret;
 145        }
 146
 147        /* Clear RPLY_RECEIV bit */
 148        anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
 149
 150        anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
 151        if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
 152                debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
 153                ret = -EIO;
 154        }
 155
 156        return ret;
 157}
 158
 159static void anx6345_aux_addr(struct udevice *dev, u32 addr)
 160{
 161        u8 val;
 162
 163        val = addr & 0xff;
 164        anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
 165        val = (addr >> 8) & 0xff;
 166        anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
 167        val = (addr >> 16) & 0x0f;
 168        anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
 169}
 170
 171static int anx6345_aux_transfer(struct udevice *dev, u8 req,
 172                                u32 addr, u8 *buf, size_t len)
 173{
 174        int i, ret;
 175        u8 ctrl1 = req;
 176        u8 ctrl2 = ANX9804_AUX_EN;
 177
 178        if (len > 16)
 179                return -E2BIG;
 180
 181        if (len)
 182                ctrl1 |= ANX9804_AUX_LENGTH(len);
 183        else
 184                ctrl2 |= ANX9804_ADDR_ONLY;
 185
 186        if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
 187                for (i = 0; i < len; i++)
 188                        anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
 189        }
 190
 191        anx6345_aux_addr(dev, addr);
 192        anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
 193        anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
 194        ret = anx6345_aux_wait(dev);
 195        if (ret) {
 196                debug("AUX transaction timed out\n");
 197                return ret;
 198        }
 199
 200        if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
 201                for (i = 0; i < len; i++)
 202                        anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
 203        }
 204
 205        return 0;
 206}
 207
 208static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
 209                                u8 offset, size_t count, u8 *buf)
 210{
 211        int i, ret;
 212        size_t cur_cnt;
 213        u8 cur_offset;
 214
 215        for (i = 0; i < count; i += 16) {
 216                cur_cnt = (count - i) > 16 ? 16 : count - i;
 217                cur_offset = offset + i;
 218                ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
 219                                           chip_addr, &cur_offset, 1);
 220                if (ret) {
 221                        debug("%s: failed to set i2c offset: %d\n",
 222                              __func__, ret);
 223                        return ret;
 224                }
 225                ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
 226                                           chip_addr, buf + i, cur_cnt);
 227                if (ret) {
 228                        debug("%s: failed to read from i2c device: %d\n",
 229                              __func__, ret);
 230                        return ret;
 231                }
 232        }
 233
 234        return 0;
 235}
 236
 237static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
 238{
 239        int ret;
 240
 241        ret = anx6345_aux_transfer(dev,
 242                                   ANX9804_AUX_TX_COMM_READ |
 243                                   ANX9804_AUX_TX_COMM_DP_TRANSACTION,
 244                                   reg, val, 1);
 245        if (ret) {
 246                debug("Failed to read DPCD\n");
 247                return ret;
 248        }
 249
 250        return 0;
 251}
 252
 253static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
 254{
 255        struct anx6345_priv *priv = dev_get_priv(dev);
 256
 257        if (size > EDID_SIZE)
 258                size = EDID_SIZE;
 259        memcpy(buf, priv->edid, size);
 260
 261        return size;
 262}
 263
 264static int anx6345_attach(struct udevice *dev)
 265{
 266        /* No-op */
 267        return 0;
 268}
 269
 270static int anx6345_enable(struct udevice *dev)
 271{
 272        u8 chipid, colordepth, lanes, data_rate, c;
 273        int ret, i, bpp;
 274        struct display_timing timing;
 275        struct anx6345_priv *priv = dev_get_priv(dev);
 276
 277        /* Deassert reset and enable power */
 278        ret = video_bridge_set_active(dev, true);
 279        if (ret)
 280                return ret;
 281
 282        /* Reset */
 283        anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
 284        mdelay(100);
 285        anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
 286
 287        /* Write 0 to the powerdown reg (powerup everything) */
 288        anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
 289
 290        ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
 291        if (ret)
 292                debug("%s: read id failed: %d\n", __func__, ret);
 293
 294        switch (chipid) {
 295        case 0x63:
 296                debug("ANX63xx detected.\n");
 297                break;
 298        default:
 299                debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
 300                return -ENODEV;
 301        }
 302
 303        for (i = 0; i < 100; i++) {
 304                anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
 305                anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
 306                anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
 307                if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
 308                        break;
 309
 310                mdelay(5);
 311        }
 312        if (i == 100)
 313                debug("Error anx6345 clock is not stable\n");
 314
 315        /* Set a bunch of analog related register values */
 316        anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
 317        anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
 318        anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
 319
 320        /* Force HPD */
 321        anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
 322                         ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
 323
 324        /* Power up and configure lanes */
 325        anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
 326        anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
 327        anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
 328        anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
 329        anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
 330
 331        /* Reset AUX CH */
 332        anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
 333                         ANX9804_RST_CTRL2_AUX);
 334        anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
 335
 336        /* Powerdown audio and some other unused bits */
 337        anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
 338        anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
 339        anx6345_write_r0(dev, 0xa7, 0x00);
 340
 341        anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
 342        if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
 343                debug("Failed to parse EDID\n");
 344                return -EIO;
 345        }
 346        debug("%s: panel found: %dx%d, bpp %d\n", __func__,
 347              timing.hactive.typ, timing.vactive.typ, bpp);
 348        if (bpp == 6)
 349                colordepth = 0x00; /* 6 bit */
 350        else
 351                colordepth = 0x10; /* 8 bit */
 352        anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
 353
 354        if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
 355                debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
 356                return -EIO;
 357        }
 358        debug("%s: data_rate: %d\n", __func__, (int)data_rate);
 359        if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
 360                debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
 361                return -EIO;
 362        }
 363        lanes &= DP_MAX_LANE_COUNT_MASK;
 364        debug("%s: lanes: %d\n", __func__, (int)lanes);
 365
 366        /* Set data-rate / lanes */
 367        anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
 368        anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
 369
 370        /* Link training */
 371        anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
 372                         ANX9804_LINK_TRAINING_CTRL_EN);
 373        mdelay(5);
 374        for (i = 0; i < 100; i++) {
 375                anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
 376                if ((chipid == 0x63) && (c & 0x80) == 0)
 377                        break;
 378
 379                mdelay(5);
 380        }
 381        if (i == 100) {
 382                debug("Error anx6345 link training timeout\n");
 383                return -ENODEV;
 384        }
 385
 386        /* Enable */
 387        anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
 388                         ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
 389        /* Force stream valid */
 390        anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
 391                         ANX9804_SYS_CTRL3_F_HPD |
 392                         ANX9804_SYS_CTRL3_HPD_CTRL |
 393                         ANX9804_SYS_CTRL3_F_VALID |
 394                         ANX9804_SYS_CTRL3_VALID_CTRL);
 395
 396        return 0;
 397}
 398
 399static int anx6345_probe(struct udevice *dev)
 400{
 401        if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
 402                return -EPROTONOSUPPORT;
 403
 404        return anx6345_enable(dev);
 405}
 406
 407struct video_bridge_ops anx6345_ops = {
 408        .attach = anx6345_attach,
 409        .set_backlight = anx6345_set_backlight,
 410        .read_edid = anx6345_read_edid,
 411};
 412
 413static const struct udevice_id anx6345_ids[] = {
 414        { .compatible = "analogix,anx6345", },
 415        { }
 416};
 417
 418U_BOOT_DRIVER(analogix_anx6345) = {
 419        .name   = "analogix_anx6345",
 420        .id     = UCLASS_VIDEO_BRIDGE,
 421        .of_match = anx6345_ids,
 422        .probe  = anx6345_probe,
 423        .ops    = &anx6345_ops,
 424        .priv_auto      = sizeof(struct anx6345_priv),
 425};
 426