1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2012 Atmel Corporation 4 * Copyright (C) 2019 Stefan Roese <sr@denx.de> 5 * 6 * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) 7 */ 8 9#ifndef __CONFIG_H__ 10#define __CONFIG_H__ 11 12#ifndef __ASSEMBLY__ 13#include <linux/bitops.h> 14#endif 15 16/* ARM asynchronous clock */ 17#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 18#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 19 20/* SDRAM */ 21#define CONFIG_SYS_SDRAM_BASE 0x20000000 22#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 23 24/* NAND flash */ 25#define CONFIG_SYS_MAX_NAND_DEVICE 1 26#define CONFIG_SYS_NAND_BASE 0x40000000 27#define CONFIG_SYS_NAND_DBW_8 1 28/* our ALE is AD21 */ 29#define CONFIG_SYS_NAND_MASK_ALE BIT(21) 30/* our CLE is AD22 */ 31#define CONFIG_SYS_NAND_MASK_CLE BIT(22) 32#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 33#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 34 35/* SPL */ 36 37#define CONFIG_SYS_MONITOR_LEN (512 << 10) 38 39#define CONFIG_SYS_MASTER_CLOCK 132096000 40#define CONFIG_SYS_AT91_PLLA 0x20c73f03 41#define CONFIG_SYS_MCKR 0x1301 42#define CONFIG_SYS_MCKR_CSS 0x1302 43 44#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 45#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 46#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 47 48#endif 49