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9#ifndef __QE_H__
10#define __QE_H__
11
12#include "common.h"
13#ifdef CONFIG_U_QE
14#include <linux/immap_qe.h>
15#endif
16
17#define QE_NUM_OF_BRGS 16
18#define UCC_MAX_NUM 8
19
20#define QE_DATAONLY_BASE 0
21#define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
22
23struct udevice;
24
25
26
27typedef enum qe_snum_state {
28 QE_SNUM_STATE_USED,
29 QE_SNUM_STATE_FREE
30} qe_snum_state_e;
31
32typedef struct qe_snum {
33 u8 num;
34 qe_snum_state_e state;
35} qe_snum_t;
36
37
38
39#define QE_RISC_ALLOCATION_RISC1 0x1
40#define QE_RISC_ALLOCATION_RISC2 0x2
41#define QE_RISC_ALLOCATION_RISC3 0x4
42#define QE_RISC_ALLOCATION_RISC4 0x8
43#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
44 QE_RISC_ALLOCATION_RISC2)
45#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
46 QE_RISC_ALLOCATION_RISC2 | \
47 QE_RISC_ALLOCATION_RISC3 | \
48 QE_RISC_ALLOCATION_RISC4)
49
50
51
52#define QE_CR_FLG 0x00010000
53#define QE_RESET 0x80000000
54#define QE_INIT_TX_RX 0x00000000
55#define QE_INIT_RX 0x00000001
56#define QE_INIT_TX 0x00000002
57#define QE_ENTER_HUNT_MODE 0x00000003
58#define QE_STOP_TX 0x00000004
59#define QE_GRACEFUL_STOP_TX 0x00000005
60#define QE_RESTART_TX 0x00000006
61#define QE_SWITCH_COMMAND 0x00000007
62#define QE_SET_GROUP_ADDRESS 0x00000008
63#define QE_INSERT_CELL 0x00000009
64#define QE_ATM_TRANSMIT 0x0000000a
65#define QE_CELL_POOL_GET 0x0000000b
66#define QE_CELL_POOL_PUT 0x0000000c
67#define QE_IMA_HOST_CMD 0x0000000d
68#define QE_ATM_MULTI_THREAD_INIT 0x00000011
69#define QE_ASSIGN_PAGE 0x00000012
70#define QE_START_FLOW_CONTROL 0x00000014
71#define QE_STOP_FLOW_CONTROL 0x00000015
72#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
73#define QE_GRACEFUL_STOP_RX 0x0000001a
74#define QE_RESTART_RX 0x0000001b
75
76
77
78#define QE_CR_SUBBLOCK_INVALID 0x00000000
79#define QE_CR_SUBBLOCK_USB 0x03200000
80#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
81#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
82#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
83#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
84#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
85#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
86#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
87#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
88#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
89#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
90#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
91#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
92#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
93#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
94#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
95#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
96#define QE_CR_SUBBLOCK_MCC1 0x03800000
97#define QE_CR_SUBBLOCK_MCC2 0x03a00000
98#define QE_CR_SUBBLOCK_MCC3 0x03000000
99#define QE_CR_SUBBLOCK_IDMA1 0x02800000
100#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
101#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
102#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
103#define QE_CR_SUBBLOCK_HPAC 0x01e00000
104#define QE_CR_SUBBLOCK_SPI1 0x01400000
105#define QE_CR_SUBBLOCK_SPI2 0x01600000
106#define QE_CR_SUBBLOCK_RAND 0x01c00000
107#define QE_CR_SUBBLOCK_TIMER 0x01e00000
108#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
109
110
111
112#define QE_CR_PROTOCOL_UNSPECIFIED 0x00
113#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
114#define QE_CR_PROTOCOL_ATM_POS 0x0A
115#define QE_CR_PROTOCOL_ETHERNET 0x0C
116#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
117#define QE_CR_PROTOCOL_SHIFT 6
118
119
120
121#define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
122
123
124
125typedef enum comm_dir {
126 COMM_DIR_NONE = 0,
127 COMM_DIR_RX = 1,
128 COMM_DIR_TX = 2,
129 COMM_DIR_RX_AND_TX = 3
130} comm_dir_e;
131
132
133
134typedef enum qe_clock {
135 QE_CLK_NONE = 0,
136 QE_BRG1,
137 QE_BRG2,
138 QE_BRG3,
139 QE_BRG4,
140 QE_BRG5,
141 QE_BRG6,
142 QE_BRG7,
143 QE_BRG8,
144 QE_BRG9,
145 QE_BRG10,
146 QE_BRG11,
147 QE_BRG12,
148 QE_BRG13,
149 QE_BRG14,
150 QE_BRG15,
151 QE_BRG16,
152 QE_CLK1,
153 QE_CLK2,
154 QE_CLK3,
155 QE_CLK4,
156 QE_CLK5,
157 QE_CLK6,
158 QE_CLK7,
159 QE_CLK8,
160 QE_CLK9,
161 QE_CLK10,
162 QE_CLK11,
163 QE_CLK12,
164 QE_CLK13,
165 QE_CLK14,
166 QE_CLK15,
167 QE_CLK16,
168 QE_CLK17,
169 QE_CLK18,
170 QE_CLK19,
171 QE_CLK20,
172 QE_CLK21,
173 QE_CLK22,
174 QE_CLK23,
175 QE_CLK24,
176 QE_CLK_DUMMY
177} qe_clock_e;
178
179
180
181#define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
182#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
183
184
185
186#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
187
188
189
190#define QE_BRGC_ENABLE 0x00010000
191#define QE_BRGC_DIVISOR_SHIFT 1
192#define QE_BRGC_DIVISOR_MAX 0xFFF
193#define QE_BRGC_DIV16 1
194
195
196
197#define QE_SDSR_BER1 0x02000000
198#define QE_SDSR_BER2 0x01000000
199
200#define QE_SDMR_GLB_1_MSK 0x80000000
201#define QE_SDMR_ADR_SEL 0x20000000
202#define QE_SDMR_BER1_MSK 0x02000000
203#define QE_SDMR_BER2_MSK 0x01000000
204#define QE_SDMR_EB1_MSK 0x00800000
205#define QE_SDMR_ER1_MSK 0x00080000
206#define QE_SDMR_ER2_MSK 0x00040000
207#define QE_SDMR_CEN_MASK 0x0000E000
208#define QE_SDMR_SBER_1 0x00000200
209#define QE_SDMR_SBER_2 0x00000200
210#define QE_SDMR_EB1_PR_MASK 0x000000C0
211#define QE_SDMR_ER1_PR 0x00000008
212
213#define QE_SDMR_CEN_SHIFT 13
214#define QE_SDMR_EB1_PR_SHIFT 6
215
216#define QE_SDTM_MSNUM_SHIFT 24
217
218#define QE_SDEBCR_BA_MASK 0x01FFFFFF
219
220
221#define QE_CP_CERCR_MEE 0x8000
222#define QE_CP_CERCR_IEE 0x4000
223#define QE_CP_CERCR_CIR 0x0800
224
225
226#define QE_IRAM_IADD_AIE 0x80000000
227#define QE_IRAM_IADD_BADDR 0x00080000
228#define QE_IRAM_READY 0x80000000
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233
234
235struct qe_firmware {
236 struct qe_header {
237 u32 length;
238 u8 magic[3];
239 u8 version;
240 } header;
241 u8 id[62];
242 u8 split;
243 u8 count;
244 struct {
245 u16 model;
246 u8 major;
247 u8 minor;
248 } __attribute__ ((packed)) soc;
249 u8 padding[4];
250 u64 extended_modes;
251 u32 vtraps[8];
252 u8 reserved[4];
253 struct qe_microcode {
254 u8 id[32];
255 u32 traps[16];
256 u32 eccr;
257 u32 iram_offset;
258 u32 count;
259 u32 code_offset;
260 u8 major;
261 u8 minor;
262 u8 revision;
263 u8 padding;
264 u8 reserved[4];
265 } __attribute__ ((packed)) microcode[1];
266
267
268} __attribute__ ((packed));
269
270struct qe_firmware_info {
271 char id[64];
272 u32 vtraps[8];
273 u64 extended_modes;
274};
275
276void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
277void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
278uint qe_muram_alloc(uint size, uint align);
279void *qe_muram_addr(uint offset);
280int qe_get_snum(void);
281void qe_put_snum(u8 snum);
282void qe_init(uint qe_base);
283void qe_reset(void);
284void qe_assign_page(uint snum, uint para_ram_base);
285int qe_set_brg(uint brg, uint rate);
286int qe_set_mii_clk_src(int ucc_num);
287int qe_upload_firmware(const struct qe_firmware *firmware);
288struct qe_firmware_info *qe_get_firmware_info(void);
289void ft_qe_setup(void *blob);
290void qe_init(uint qe_base);
291void qe_reset(void);
292
293#ifdef CONFIG_U_QE
294void u_qe_init(void);
295int u_qe_upload_firmware(const struct qe_firmware *firmware);
296void u_qe_resume(void);
297int u_qe_firmware_resume(const struct qe_firmware *firmware,
298 qe_map_t *qe_immrr);
299#endif
300
301#if defined(CONFIG_PINCTRL)
302int par_io_of_config(struct udevice *dev);
303#endif
304#endif
305