LXR uboot/include/usb/fotg210.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Faraday USB 2.0 OTG Controller
   4 *
   5 * (C) Copyright 2010 Faraday Technology
   6 * Dante Su <dantesu@faraday-tech.com>
   7 */
   8
   9#ifndef _FOTG210_H
  10#define _FOTG210_H
  11
  12struct fotg210_regs {
  13        /* USB Host Controller */
  14        struct {
  15                uint32_t data[4];
  16        } hccr;                 /* 0x00 - 0x0f: hccr */
  17        struct {
  18                uint32_t data[9];
  19        } hcor;                 /* 0x10 - 0x33: hcor */
  20        uint32_t rsvd1[3];
  21        uint32_t miscr; /* 0x40: Miscellaneous Register */
  22        uint32_t rsvd2[15];
  23        /* USB OTG Controller */
  24        uint32_t otgcsr;/* 0x80: OTG Control Status Register */
  25        uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
  26        uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
  27        uint32_t rsvd3[13];
  28        uint32_t isr;   /* 0xC0: Global Interrupt Status Register */
  29        uint32_t imr;   /* 0xC4: Global Interrupt Mask Register */
  30        uint32_t rsvd4[14];
  31        /* USB Device Controller */
  32        uint32_t dev_ctrl;/* 0x100: Device Control Register */
  33        uint32_t dev_addr;/* 0x104: Device Address Register */
  34        uint32_t dev_test;/* 0x108: Device Test Register */
  35        uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
  36        uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
  37        uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
  38        uint32_t rsvd5[2];
  39        uint32_t cxfifo;/* 0x120: CX FIFO Register */
  40        uint32_t idle;  /* 0x124: IDLE Counter Register */
  41        uint32_t rsvd6[2];
  42        uint32_t gimr;  /* 0x130: Group Interrupt Mask Register */
  43        uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
  44        uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
  45        uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
  46        uint32_t gisr;  /* 0x140: Group Interrupt Status Register */
  47        uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
  48        uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
  49        uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
  50        uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
  51        uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
  52        uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
  53        uint32_t rsvd7[1];
  54        uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
  55        uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
  56        uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
  57        uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
  58        uint32_t fifomap;/* 0x1a8: FIFO Map Register */
  59        uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
  60        uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
  61        uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
  62        uint32_t rsvd8[1];
  63        uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
  64        uint32_t dma_addr; /* 0x1cc: DMA Address Register */
  65        uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */
  66};
  67
  68/* Miscellaneous Register */
  69#define MISCR_SUSPEND  (1 << 6) /* Put transceiver in suspend mode */
  70#define MISCR_EOF2(x)  (((x) & 0x3) << 4) /* EOF 2 Timing */
  71#define MISCR_EOF1(x)  (((x) & 0x3) << 2) /* EOF 1 Timing */
  72#define MISCR_ASST(x)  (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
  73
  74/* OTG Control Status Register */
  75#define OTGCSR_SPD_HIGH     (2 << 22) /* Speed of the attached device (host) */
  76#define OTGCSR_SPD_LOW      (1 << 22)
  77#define OTGCSR_SPD_FULL     (0 << 22)
  78#define OTGCSR_SPD_MASK     (3 << 22)
  79#define OTGCSR_SPD_SHIFT    22
  80#define OTGCSR_SPD(x)       (((x) >> 22) & 0x03)
  81#define OTGCSR_DEV_A        (0 << 21) /* Acts as A-device */
  82#define OTGCSR_DEV_B        (1 << 21) /* Acts as B-device */
  83#define OTGCSR_ROLE_H       (0 << 20) /* Acts as Host */
  84#define OTGCSR_ROLE_D       (1 << 20) /* Acts as Device */
  85#define OTGCSR_A_VBUS_VLD   (1 << 19) /* A-device VBUS Valid */
  86#define OTGCSR_A_SESS_VLD   (1 << 18) /* A-device Session Valid */
  87#define OTGCSR_B_SESS_VLD   (1 << 17) /* B-device Session Valid */
  88#define OTGCSR_B_SESS_END   (1 << 16) /* B-device Session End */
  89#define OTGCSR_HFT_LONG     (1 << 11) /* HDISCON noise filter = 270 us*/
  90#define OTGCSR_HFT          (0 << 11) /* HDISCON noise filter = 135 us*/
  91#define OTGCSR_VFT_LONG     (1 << 10) /* VBUS noise filter = 472 us*/
  92#define OTGCSR_VFT          (0 << 10) /* VBUS noise filter = 135 us*/
  93#define OTGCSR_IDFT_LONG    (1 << 9)  /* ID noise filter = 4 ms*/
  94#define OTGCSR_IDFT         (0 << 9)  /* ID noise filter = 3 ms*/
  95#define OTGCSR_A_SRPR_VBUS  (0 << 8)  /* A-device: SRP responds to VBUS */
  96#define OTGCSR_A_SRPR_DATA  (1 << 8)  /* A-device: SRP responds to DATA-LINE */
  97#define OTGCSR_A_SRP_EN     (1 << 7)  /* A-device SRP detection enabled */
  98#define OTGCSR_A_HNP        (1 << 6)  /* Set role=A-device with HNP enabled */
  99#define OTGCSR_A_BUSDROP    (1 << 5)  /* A-device drop bus (power-down) */
 100#define OTGCSR_A_BUSREQ     (1 << 4)  /* A-device request bus */
 101#define OTGCSR_B_VBUS_DISC  (1 << 2)  /* B-device discharges VBUS */
 102#define OTGCSR_B_HNP        (1 << 1)  /* B-device enable HNP */
 103#define OTGCSR_B_BUSREQ     (1 << 0)  /* B-device request bus */
 104
 105/* OTG Interrupt Status Register */
 106#define OTGISR_APRM         (1 << 12) /* Mini-A plug removed */
 107#define OTGISR_BPRM         (1 << 11) /* Mini-B plug removed */
 108#define OTGISR_OVD          (1 << 10) /* over-current detected */
 109#define OTGISR_IDCHG        (1 << 9)  /* ID(A/B) changed */
 110#define OTGISR_RLCHG        (1 << 8)  /* Role(Host/Device) changed */
 111#define OTGISR_BSESSEND     (1 << 6)  /* B-device Session End */
 112#define OTGISR_AVBUSERR     (1 << 5)  /* A-device VBUS Error */
 113#define OTGISR_ASRP         (1 << 4)  /* A-device SRP detected */
 114#define OTGISR_BSRP         (1 << 0)  /* B-device SRP complete */
 115
 116/* OTG Interrupt Enable Register */
 117#define OTGIER_APRM         (1 << 12) /* Mini-A plug removed */
 118#define OTGIER_BPRM         (1 << 11) /* Mini-B plug removed */
 119#define OTGIER_OVD          (1 << 10) /* over-current detected */
 120#define OTGIER_IDCHG        (1 << 9)  /* ID(A/B) changed */
 121#define OTGIER_RLCHG        (1 << 8)  /* Role(Host/Device) changed */
 122#define OTGIER_BSESSEND     (1 << 6)  /* B-device Session End */
 123#define OTGIER_AVBUSERR     (1 << 5)  /* A-device VBUS Error */
 124#define OTGIER_ASRP         (1 << 4)  /* A-device SRP detected */
 125#define OTGIER_BSRP         (1 << 0)  /* B-device SRP complete */
 126
 127/* Global Interrupt Status Register (W1C) */
 128#define ISR_HOST            (1 << 2)  /* USB Host interrupt */
 129#define ISR_OTG             (1 << 1)  /* USB OTG interrupt */
 130#define ISR_DEV             (1 << 0)  /* USB Device interrupt */
 131#define ISR_MASK            0x07
 132
 133/* Global Interrupt Mask Register */
 134#define IMR_IRQLH           (1 << 3)  /* Interrupt triggered at level-high */
 135#define IMR_IRQLL           (0 << 3)  /* Interrupt triggered at level-low */
 136#define IMR_HOST            (1 << 2)  /* USB Host interrupt */
 137#define IMR_OTG             (1 << 1)  /* USB OTG interrupt */
 138#define IMR_DEV             (1 << 0)  /* USB Device interrupt */
 139#define IMR_MASK            0x0f
 140
 141/* Device Control Register */
 142#define DEVCTRL_FS_FORCED   (1 << 9)  /* Forced to be Full-Speed Mode */
 143#define DEVCTRL_HS          (1 << 6)  /* High Speed Mode */
 144#define DEVCTRL_FS          (0 << 6)  /* Full Speed Mode */
 145#define DEVCTRL_EN          (1 << 5)  /* Chip Enable */
 146#define DEVCTRL_RESET       (1 << 4)  /* Chip Software Reset */
 147#define DEVCTRL_SUSPEND     (1 << 3)  /* Enter Suspend Mode */
 148#define DEVCTRL_GIRQ_EN     (1 << 2)  /* Global Interrupt Enabled */
 149#define DEVCTRL_HALFSPD     (1 << 1)  /* Half speed mode for FPGA test */
 150#define DEVCTRL_RWAKEUP     (1 << 0)  /* Enable remote wake-up */
 151
 152/* Device Address Register */
 153#define DEVADDR_CONF        (1 << 7)  /* SET_CONFIGURATION has been executed */
 154#define DEVADDR_ADDR(x)     ((x) & 0x7f)
 155#define DEVADDR_ADDR_MASK   0x7f
 156
 157/* Device Test Register */
 158#define DEVTEST_NOSOF       (1 << 6)  /* Do not generate SOF */
 159#define DEVTEST_TST_MODE    (1 << 5)  /* Enter Test Mode */
 160#define DEVTEST_TST_NOTS    (1 << 4)  /* Do not toggle sequence */
 161#define DEVTEST_TST_NOCRC   (1 << 3)  /* Do not append CRC */
 162#define DEVTEST_TST_CLREA   (1 << 2)  /* Clear External Side Address */
 163#define DEVTEST_TST_CXLP    (1 << 1)  /* EP0 loopback test */
 164#define DEVTEST_TST_CLRFF   (1 << 0)  /* Clear FIFO */
 165
 166/* SOF Frame Number Register */
 167#define SOFFNR_UFN(x)       (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */
 168#define SOFFNR_FNR(x)       ((x) & 0x7ff) /* SOF Frame Number */
 169
 170/* SOF Mask Timer Register */
 171#define SOFMTR_TMR(x)       ((x) & 0xffff)
 172
 173/* PHY Test Mode Selector Register */
 174#define PHYTMSR_TST_PKT     (1 << 4) /* Packet send test */
 175#define PHYTMSR_TST_SE0NAK  (1 << 3) /* High-Speed quiescent state */
 176#define PHYTMSR_TST_KSTA    (1 << 2) /* High-Speed K state */
 177#define PHYTMSR_TST_JSTA    (1 << 1) /* High-Speed J state */
 178#define PHYTMSR_UNPLUG      (1 << 0) /* Enable soft-detachment */
 179
 180/* CX FIFO Register */
 181#define CXFIFO_BYTES(x)     (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */
 182#define CXFIFO_FIFOE(x)     (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */
 183#define CXFIFO_FIFOE_FIFO0  (1 << 8)
 184#define CXFIFO_FIFOE_FIFO1  (1 << 9)
 185#define CXFIFO_FIFOE_FIFO2  (1 << 10)
 186#define CXFIFO_FIFOE_FIFO3  (1 << 11)
 187#define CXFIFO_FIFOE_MASK   (0x0f << 8)
 188#define CXFIFO_CXFIFOE      (1 << 5) /* CX FIFO empty */
 189#define CXFIFO_CXFIFOF      (1 << 4) /* CX FIFO full */
 190#define CXFIFO_CXFIFOCLR    (1 << 3) /* CX FIFO clear */
 191#define CXFIFO_CXSTALL      (1 << 2) /* CX Stall */
 192#define CXFIFO_TSTPKTFIN    (1 << 1) /* Test packet data transfer finished */
 193#define CXFIFO_CXFIN        (1 << 0) /* CX data transfer finished */
 194
 195/* IDLE Counter Register */
 196#define IDLE_MS(x)          ((x) & 0x07) /* PHY suspend delay = x ms */
 197
 198/* Group Interrupt Mask(Disable) Register */
 199#define GIMR_GRP2           (1 << 2) /* Disable interrupt group 2 */
 200#define GIMR_GRP1           (1 << 1) /* Disable interrupt group 1 */
 201#define GIMR_GRP0           (1 << 0) /* Disable interrupt group 0 */
 202#define GIMR_MASK           0x07
 203
 204/* Group Interrupt Mask(Disable) Register 0 (CX) */
 205#define GIMR0_CXABORT       (1 << 5) /* CX command abort interrupt */
 206#define GIMR0_CXERR         (1 << 4) /* CX command error interrupt */
 207#define GIMR0_CXEND         (1 << 3) /* CX command end interrupt */
 208#define GIMR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
 209#define GIMR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
 210#define GIMR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
 211#define GIMR0_MASK          0x3f
 212
 213/* Group Interrupt Mask(Disable) Register 1 (FIFO) */
 214#define GIMR1_FIFO_IN(x)    (1 << (((x) & 3) + 16))    /* FIFOx IN */
 215#define GIMR1_FIFO_TX(x)    GIMR1_FIFO_IN(x)
 216#define GIMR1_FIFO_OUT(x)   (1 << (((x) & 3) * 2))     /* FIFOx OUT */
 217#define GIMR1_FIFO_SPK(x)   (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */
 218#define GIMR1_FIFO_RX(x)    (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x))
 219#define GIMR1_MASK          0xf00ff
 220
 221/* Group Interrupt Mask(Disable) Register 2 (Device) */
 222#define GIMR2_WAKEUP        (1 << 10) /* Device waked up */
 223#define GIMR2_IDLE          (1 << 9)  /* Device idle */
 224#define GIMR2_DMAERR        (1 << 8)  /* DMA error */
 225#define GIMR2_DMAFIN        (1 << 7)  /* DMA finished */
 226#define GIMR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
 227#define GIMR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
 228#define GIMR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
 229#define GIMR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
 230#define GIMR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
 231#define GIMR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
 232#define GIMR2_RESET         (1 << 0)  /* Reset Interrupt */
 233#define GIMR2_MASK          0x7ff
 234
 235/* Group Interrupt Status Register */
 236#define GISR_GRP2           (1 << 2) /* Interrupt group 2 */
 237#define GISR_GRP1           (1 << 1) /* Interrupt group 1 */
 238#define GISR_GRP0           (1 << 0) /* Interrupt group 0 */
 239
 240/* Group Interrupt Status Register 0 (CX) */
 241#define GISR0_CXABORT       (1 << 5) /* CX command abort interrupt */
 242#define GISR0_CXERR         (1 << 4) /* CX command error interrupt */
 243#define GISR0_CXEND         (1 << 3) /* CX command end interrupt */
 244#define GISR0_CXOUT         (1 << 2) /* EP0-OUT packet interrupt */
 245#define GISR0_CXIN          (1 << 1) /* EP0-IN packet interrupt */
 246#define GISR0_CXSETUP       (1 << 0) /* EP0-SETUP packet interrupt */
 247
 248/* Group Interrupt Status Register 1 (FIFO) */
 249#define GISR1_IN_FIFO(x)    (1 << (((x) & 0x03) + 16))    /* FIFOx IN */
 250#define GISR1_OUT_FIFO(x)   (1 << (((x) & 0x03) * 2))     /* FIFOx OUT */
 251#define GISR1_SPK_FIFO(x)   (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */
 252#define GISR1_RX_FIFO(x)    (3 << (((x) & 0x03) * 2))     /* FIFOx OUT/SPK */
 253
 254/* Group Interrupt Status Register 2 (Device) */
 255#define GISR2_WAKEUP        (1 << 10) /* Device waked up */
 256#define GISR2_IDLE          (1 << 9)  /* Device idle */
 257#define GISR2_DMAERR        (1 << 8)  /* DMA error */
 258#define GISR2_DMAFIN        (1 << 7)  /* DMA finished */
 259#define GISR2_ZLPRX         (1 << 6)  /* Zero-Length-Packet Rx Interrupt */
 260#define GISR2_ZLPTX         (1 << 5)  /* Zero-Length-Packet Tx Interrupt */
 261#define GISR2_ISOCABT       (1 << 4)  /* ISOC Abort Interrupt */
 262#define GISR2_ISOCERR       (1 << 3)  /* ISOC Error Interrupt */
 263#define GISR2_RESUME        (1 << 2)  /* Resume state change Interrupt */
 264#define GISR2_SUSPEND       (1 << 1)  /* Suspend state change Interrupt */
 265#define GISR2_RESET         (1 << 0)  /* Reset Interrupt */
 266
 267/* Receive Zero-Length-Packet Register */
 268#define RXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP rx interrupt */
 269
 270/* Transfer Zero-Length-Packet Register */
 271#define TXZLP_EP(x)         (1 << ((x) - 1)) /* EPx ZLP tx interrupt */
 272
 273/* ISOC Error/Abort Status Register */
 274#define ISOEASR_EP(x)       (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */
 275
 276/* IN Endpoint Register */
 277#define IEP_SENDZLP         (1 << 15)     /* Send Zero-Length-Packet */
 278#define IEP_TNRHB(x)        (((x) & 0x03) << 13) \
 279        /* Transaction Number for High-Bandwidth EP(ISOC) */
 280#define IEP_RESET           (1 << 12)     /* Reset Toggle Sequence */
 281#define IEP_STALL           (1 << 11)     /* Stall */
 282#define IEP_MAXPS(x)        ((x) & 0x7ff) /* Max. packet size */
 283
 284/* OUT Endpoint Register */
 285#define OEP_RESET           (1 << 12)     /* Reset Toggle Sequence */
 286#define OEP_STALL           (1 << 11)     /* Stall */
 287#define OEP_MAXPS(x)        ((x) & 0x7ff) /* Max. packet size */
 288
 289/* Endpoint Map Register (EP1 ~ EP4) */
 290#define EPMAP14_SET_IN(ep, fifo) \
 291        ((fifo) & 3) << (((ep) - 1) << 3 + 0)
 292#define EPMAP14_SET_OUT(ep, fifo) \
 293        ((fifo) & 3) << (((ep) - 1) << 3 + 4)
 294#define EPMAP14_SET(ep, in, out) \
 295        do { \
 296                EPMAP14_SET_IN(ep, in); \
 297                EPMAP14_SET_OUT(ep, out); \
 298        } while (0)
 299
 300#define EPMAP14_DEFAULT     0x33221100 /* EP1->FIFO0, EP2->FIFO1... */
 301
 302/* Endpoint Map Register (EP5 ~ EP8) */
 303#define EPMAP58_SET_IN(ep, fifo) \
 304        ((fifo) & 3) << (((ep) - 5) << 3 + 0)
 305#define EPMAP58_SET_OUT(ep, fifo) \
 306        ((fifo) & 3) << (((ep) - 5) << 3 + 4)
 307#define EPMAP58_SET(ep, in, out) \
 308        do { \
 309                EPMAP58_SET_IN(ep, in); \
 310                EPMAP58_SET_OUT(ep, out); \
 311        } while (0)
 312
 313#define EPMAP58_DEFAULT     0x00000000 /* All EPx->FIFO0 */
 314
 315/* FIFO Map Register */
 316#define FIFOMAP_BIDIR       (2 << 4)
 317#define FIFOMAP_IN          (1 << 4)
 318#define FIFOMAP_OUT         (0 << 4)
 319#define FIFOMAP_DIR_MASK    0x30
 320#define FIFOMAP_EP(x)       ((x) & 0x0f)
 321#define FIFOMAP_EP_MASK     0x0f
 322#define FIFOMAP_CFG_MASK    0x3f
 323#define FIFOMAP_DEFAULT     0x04030201 /* FIFO0->EP1, FIFO1->EP2... */
 324#define FIFOMAP(fifo, cfg)  (((cfg) & 0x3f) << (((fifo) & 3) << 3))
 325
 326/* FIFO Configuration Register */
 327#define FIFOCFG_EN          (1 << 5)
 328#define FIFOCFG_BLKSZ_1024  (1 << 4)
 329#define FIFOCFG_BLKSZ_512   (0 << 4)
 330#define FIFOCFG_3BLK        (2 << 2)
 331#define FIFOCFG_2BLK        (1 << 2)
 332#define FIFOCFG_1BLK        (0 << 2)
 333#define FIFOCFG_NBLK_MASK   3
 334#define FIFOCFG_NBLK_SHIFT  2
 335#define FIFOCFG_INTR        (3 << 0)
 336#define FIFOCFG_BULK        (2 << 0)
 337#define FIFOCFG_ISOC        (1 << 0)
 338#define FIFOCFG_RSVD        (0 << 0)  /* Reserved */
 339#define FIFOCFG_TYPE_MASK   3
 340#define FIFOCFG_TYPE_SHIFT  0
 341#define FIFOCFG_CFG_MASK    0x3f
 342#define FIFOCFG(fifo, cfg)  (((cfg) & 0x3f) << (((fifo) & 3) << 3))
 343
 344/* FIFO Control Status Register */
 345#define FIFOCSR_RESET       (1 << 12) /* FIFO Reset */
 346#define FIFOCSR_BYTES(x)    ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */
 347
 348/* DMA Target FIFO Register */
 349#define DMAFIFO_CX          (1 << 4) /* DMA FIFO = CX FIFO */
 350#define DMAFIFO_FIFO(x)     (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */
 351
 352/* DMA Control Register */
 353#define DMACTRL_LEN(x)      (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */
 354#define DMACTRL_LEN_SHIFT   8
 355#define DMACTRL_CLRFF       (1 << 4) /* Clear FIFO upon DMA abort */
 356#define DMACTRL_ABORT       (1 << 3) /* DMA abort */
 357#define DMACTRL_IO2IO       (1 << 2) /* IO to IO */
 358#define DMACTRL_FIFO2MEM    (0 << 1) /* FIFO to Memory */
 359#define DMACTRL_MEM2FIFO    (1 << 1) /* Memory to FIFO */
 360#define DMACTRL_START       (1 << 0) /* DMA start */
 361
 362#endif
 363