1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2013-2015 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef __ARCH_FSL_LSCH2_IMMAP_H__ 7#define __ARCH_FSL_LSCH2_IMMAP_H__ 8 9#include <fsl_immap.h> 10#ifndef __ASSEMBLY__ 11#include <linux/bitops.h> 12#endif 13 14#define CONFIG_SYS_DCSRBAR 0x20000000 15#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000) 16 17#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 19#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) 20#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 21#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 23#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) 24#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) 26#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) 27#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 28#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 29#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 30#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) 31#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) 32#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) 33#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) 34#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) 35#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) 36#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 37#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 38#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) 39#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000) 40#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200) 41 42#define CONFIG_SYS_BMAN_NUM_PORTALS 10 43#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000 44#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \ 45 CONFIG_SYS_BMAN_MEM_BASE) 46#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000 47#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000 48#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000 49#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 50#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 51#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 52 CONFIG_SYS_BMAN_CENA_SIZE) 53#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 54#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80 55#define CONFIG_SYS_QMAN_NUM_PORTALS 10 56#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000 57#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 58#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000 59#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000 60#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000 61#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 62#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 63#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 64 CONFIG_SYS_QMAN_CENA_SIZE) 65#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 66#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680 67 68#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000 69 70#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 71#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 72#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 73#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000) 74 75#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 76 77#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 78#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 79 80#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) 81#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) 82#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) 83#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) 84 85#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) 86 87#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 88 89#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) 90 91#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 92 93#define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) 94#define QMAN_CQSIDR_REG 0x20a80 95 96#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL 97#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL 98#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL 99/* LUT registers */ 100#ifdef CONFIG_ARCH_LS1012A 101#define PCIE_LUT_BASE 0xC0000 102#else 103#define PCIE_LUT_BASE 0x10000 104#endif 105#define PCIE_LUT_LCTRL0 0x7F8 106#define PCIE_LUT_DBG 0x7FC 107 108/* TZ Address Space Controller Definitions */ 109#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 110#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 111#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 112#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 113#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 114#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 115#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 116#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 117#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 118#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 119#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 120#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 121#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 122 123#define TP_ITYP_AV 0x00000001 /* Initiator available */ 124#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 125#define TP_ITYP_TYPE_ARM 0x0 126#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 127#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */ 128#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 129#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 130#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 131#define TY_ITYP_VER_A7 0x1 132#define TY_ITYP_VER_A53 0x2 133#define TY_ITYP_VER_A57 0x3 134#define TY_ITYP_VER_A72 0x4 135 136#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ 137#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 138#define TP_INIT_PER_CLUSTER 4 139 140#ifndef CONFIG_SYS_CCSRBAR 141#define CONFIG_SYS_CCSRBAR 0x01000000 142#endif 143 144#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 145#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 146#endif 147 148#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 149#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0x01000000 150#endif 151 152#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 153 CONFIG_SYS_CCSRBAR_PHYS_LOW) 154 155struct sys_info { 156 unsigned long freq_processor[CONFIG_MAX_CPUS]; 157 /* frequency of platform PLL */ 158 unsigned long freq_systembus; 159 unsigned long freq_ddrbus; 160 unsigned long freq_localbus; 161 unsigned long freq_cga_m2; 162#ifdef CONFIG_SYS_DPAA_FMAN 163 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; 164#endif 165 unsigned long freq_qman; 166}; 167 168#define CFG_SYS_FSL_FM1_OFFSET 0xa00000 169 170#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 171#define CFG_SYS_FSL_FM1_ADDR \ 172 (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET) 173#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \ 174 (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET) 175 176#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull 177#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull 178#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET 179#define FSL_SEC_JR1_OFFSET 0x720000ull 180#define FSL_SEC_JR2_OFFSET 0x730000ull 181#define FSL_SEC_JR3_OFFSET 0x740000ull 182#define CFG_SYS_FSL_SEC_ADDR \ 183 (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) 184#define CFG_SYS_FSL_JR0_ADDR \ 185 (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) 186#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) 187#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) 188#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) 189#define FSL_SEC_JR3_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR3_OFFSET) 190 191/* Device Configuration and Pin Control */ 192#define DCFG_DCSR_PORCR1 0x0 193#define DCFG_DCSR_ECCCR2 0x524 194#define DISABLE_PFE_ECC BIT(13) 195 196struct ccsr_gur { 197 u32 porsr1; /* POR status 1 */ 198#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 199 u32 porsr2; /* POR status 2 */ 200 u8 res_008[0x20-0x8]; 201 u32 gpporcr1; /* General-purpose POR configuration */ 202 u32 gpporcr2; 203#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25 204#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F 205#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20 206#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F 207 u32 dcfg_fusesr; /* Fuse status register */ 208 u8 res_02c[0x70-0x2c]; 209 u32 devdisr; /* Device disable control */ 210#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000 211#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000 212#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000 213#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000 214#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000 215#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000 216#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000 217#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000 218#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000 219#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000 220#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000 221#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000 222 u32 devdisr2; /* Device disable control 2 */ 223 u32 devdisr3; /* Device disable control 3 */ 224 u32 devdisr4; /* Device disable control 4 */ 225 u32 devdisr5; /* Device disable control 5 */ 226 u32 devdisr6; /* Device disable control 6 */ 227 u32 devdisr7; /* Device disable control 7 */ 228 u8 res_08c[0x94-0x8c]; 229 u32 coredisru; /* uppper portion for support of 64 cores */ 230 u32 coredisrl; /* lower portion for support of 64 cores */ 231 u8 res_09c[0xa0-0x9c]; 232 u32 pvr; /* Processor version */ 233 u32 svr; /* System version */ 234 u32 mvr; /* Manufacturing version */ 235 u8 res_0ac[0xb0-0xac]; 236 u32 rstcr; /* Reset control */ 237 u32 rstrqpblsr; /* Reset request preboot loader status */ 238 u8 res_0b8[0xc0-0xb8]; 239 u32 rstrqmr1; /* Reset request mask */ 240 u8 res_0c4[0xc8-0xc4]; 241 u32 rstrqsr1; /* Reset request status */ 242 u8 res_0cc[0xd4-0xcc]; 243 u32 rstrqwdtmrl; /* Reset request WDT mask */ 244 u8 res_0d8[0xdc-0xd8]; 245 u32 rstrqwdtsrl; /* Reset request WDT status */ 246 u8 res_0e0[0xe4-0xe0]; 247 u32 brrl; /* Boot release */ 248 u8 res_0e8[0x100-0xe8]; 249 u32 rcwsr[16]; /* Reset control word status */ 250#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25 251#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f 252#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16 253#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f 254#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 255#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 256#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff 257#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 258#define RCW_SB_EN_REG_INDEX 7 259#define RCW_SB_EN_MASK 0x00200000 260 261 u8 res_140[0x200-0x140]; 262 u32 scratchrw[4]; /* Scratch Read/Write */ 263 u8 res_210[0x300-0x210]; 264 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 265 u8 res_310[0x400-0x310]; 266 u32 crstsr[12]; 267 u8 res_430[0x500-0x430]; 268 269 /* PCI Express n Logical I/O Device Number register */ 270 u32 dcfg_ccsr_pex1liodnr; 271 u32 dcfg_ccsr_pex2liodnr; 272 u32 dcfg_ccsr_pex3liodnr; 273 u32 dcfg_ccsr_pex4liodnr; 274 /* RIO n Logical I/O Device Number register */ 275 u32 dcfg_ccsr_rio1liodnr; 276 u32 dcfg_ccsr_rio2liodnr; 277 u32 dcfg_ccsr_rio3liodnr; 278 u32 dcfg_ccsr_rio4liodnr; 279 /* USB Logical I/O Device Number register */ 280 u32 dcfg_ccsr_usb1liodnr; 281 u32 dcfg_ccsr_usb2liodnr; 282 u32 dcfg_ccsr_usb3liodnr; 283 u32 dcfg_ccsr_usb4liodnr; 284 /* SD/MMC Logical I/O Device Number register */ 285 u32 dcfg_ccsr_sdmmc1liodnr; 286 u32 dcfg_ccsr_sdmmc2liodnr; 287 u32 dcfg_ccsr_sdmmc3liodnr; 288 u32 dcfg_ccsr_sdmmc4liodnr; 289 /* RIO Message Unit Logical I/O Device Number register */ 290 u32 dcfg_ccsr_riomaintliodnr; 291 292 u8 res_544[0x550-0x544]; 293 u32 sataliodnr[4]; 294 u8 res_560[0x570-0x560]; 295 296 u32 dcfg_ccsr_misc1liodnr; 297 u32 dcfg_ccsr_misc2liodnr; 298 u32 dcfg_ccsr_misc3liodnr; 299 u32 dcfg_ccsr_misc4liodnr; 300 u32 dcfg_ccsr_dma1liodnr; 301 u32 dcfg_ccsr_dma2liodnr; 302 u32 dcfg_ccsr_dma3liodnr; 303 u32 dcfg_ccsr_dma4liodnr; 304 u32 dcfg_ccsr_spare1liodnr; 305 u32 dcfg_ccsr_spare2liodnr; 306 u32 dcfg_ccsr_spare3liodnr; 307 u32 dcfg_ccsr_spare4liodnr; 308 u8 res_5a0[0x600-0x5a0]; 309 u32 dcfg_ccsr_pblsr; 310 311 u32 pamubypenr; 312 u32 dmacr1; 313 314 u8 res_60c[0x610-0x60c]; 315 u32 dcfg_ccsr_gensr1; 316 u32 dcfg_ccsr_gensr2; 317 u32 dcfg_ccsr_gensr3; 318 u32 dcfg_ccsr_gensr4; 319 u32 dcfg_ccsr_gencr1; 320 u32 dcfg_ccsr_gencr2; 321 u32 dcfg_ccsr_gencr3; 322 u32 dcfg_ccsr_gencr4; 323 u32 dcfg_ccsr_gencr5; 324 u32 dcfg_ccsr_gencr6; 325 u32 dcfg_ccsr_gencr7; 326 u8 res_63c[0x658-0x63c]; 327 u32 dcfg_ccsr_cgensr1; 328 u32 dcfg_ccsr_cgensr0; 329 u8 res_660[0x678-0x660]; 330 u32 dcfg_ccsr_cgencr1; 331 332 u32 dcfg_ccsr_cgencr0; 333 u8 res_680[0x700-0x680]; 334 u32 dcfg_ccsr_sriopstecr; 335 u32 dcfg_ccsr_dcsrcr; 336 337 u8 res_708[0x740-0x708]; /* add more registers when needed */ 338 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 339 struct { 340 u32 upper; 341 u32 lower; 342 } tp_cluster[16]; 343 u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */ 344 u32 dcfg_ccsr_qmbm_warmrst; 345 u8 res_a04[0xa20-0xa04]; /* add more registers when needed */ 346 u32 dcfg_ccsr_reserved0; 347 u32 dcfg_ccsr_reserved1; 348}; 349 350#define SCFG_QSPI_CLKSEL 0x40100000 351#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 352#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 353#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002 354#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 355#define SCFG_USBPWRFAULT_SHARED 0x00000001 356#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 357#define SCFG_USBPWRFAULT_USB3_SHIFT 4 358#define SCFG_USBPWRFAULT_USB2_SHIFT 2 359#define SCFG_USBPWRFAULT_USB1_SHIFT 0 360 361#define SCFG_BASE 0x01570000 362#define SCFG_USB3PRM1CR_USB1 0x070 363#define SCFG_USB3PRM2CR_USB1 0x074 364#define SCFG_USB3PRM1CR_USB2 0x07C 365#define SCFG_USB3PRM2CR_USB2 0x080 366#define SCFG_USB3PRM1CR_USB3 0x088 367#define SCFG_USB3PRM2CR_USB3 0x08c 368#define SCFG_USB_TXVREFTUNE 0x9 369#define SCFG_USB_SQRXTUNE_MASK 0x7 370#define SCFG_USB_PCSTXSWINGFULL 0x47 371#define SCFG_USB_PHY1 0x084F0000 372#define SCFG_USB_PHY2 0x08500000 373#define SCFG_USB_PHY3 0x08510000 374#define SCFG_USB_PHY_RX_OVRD_IN_HI 0x200c 375#define USB_PHY_RX_EQ_VAL_1 0x0000 376#define USB_PHY_RX_EQ_VAL_2 0x0080 377#define USB_PHY_RX_EQ_VAL_3 0x0380 378#define USB_PHY_RX_EQ_VAL_4 0x0b80 379 380#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 381#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 382#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 383#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 384#define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 385#define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 386#define SCFG_SNPCNFGCR_EDMASNP 0x00020000 387#define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 388#define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 389#define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 390#define SCFG_SNPCNFGCR_USB3WRSNP 0x00004000 391 392/* RGMIIPCR bit definitions*/ 393#define SCFG_RGMIIPCR_EN_AUTO BIT(3) 394#define SCFG_RGMIIPCR_SETSP_1000M BIT(2) 395#define SCFG_RGMIIPCR_SETSP_100M 0 396#define SCFG_RGMIIPCR_SETSP_10M BIT(1) 397#define SCFG_RGMIIPCR_SETFD BIT(0) 398 399/* PFEASBCR bit definitions */ 400#define SCFG_PFEASBCR_ARCACHE0 BIT(31) 401#define SCFG_PFEASBCR_AWCACHE0 BIT(30) 402#define SCFG_PFEASBCR_ARCACHE1 BIT(29) 403#define SCFG_PFEASBCR_AWCACHE1 BIT(28) 404#define SCFG_PFEASBCR_ARSNP BIT(27) 405#define SCFG_PFEASBCR_AWSNP BIT(26) 406 407/* WR_QoS1 PFE bit definitions */ 408#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24) 409#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20) 410 411/* RD_QoS1 PFE bit definitions */ 412#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24) 413#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20) 414 415/* Supplemental Configuration Unit */ 416struct ccsr_scfg { 417 u8 res_000[0x100-0x000]; 418 u32 usb2_icid; 419 u32 usb3_icid; 420 u8 res_108[0x114-0x108]; 421 u32 dma_icid; 422 u32 sata_icid; 423 u32 usb1_icid; 424 u32 qe_icid; 425 u32 sdhc_icid; 426 u32 edma_icid; 427 u32 etr_icid; 428 u32 core_sft_rst[4]; 429 u8 res_140[0x158-0x140]; 430 u32 altcbar; 431 u32 qspi_cfg; 432 u8 res_160[0x164 - 0x160]; 433 u32 wr_qos1; 434 u32 wr_qos2; 435 u32 rd_qos1; 436 u32 rd_qos2; 437 u8 res_174[0x180 - 0x174]; 438 u32 dmamcr; 439 u8 res_184[0x188-0x184]; 440 u32 gic_align; 441 u32 debug_icid; 442 u8 res_190[0x1a4-0x190]; 443 u32 snpcnfgcr; 444 u8 res_1a8[0x1ac-0x1a8]; 445 u32 intpcr; 446 u8 res_1b0[0x204-0x1b0]; 447 u32 coresrencr; 448 u8 res_208[0x220-0x208]; 449 u32 rvbar0_0; 450 u32 rvbar0_1; 451 u32 rvbar1_0; 452 u32 rvbar1_1; 453 u32 rvbar2_0; 454 u32 rvbar2_1; 455 u32 rvbar3_0; 456 u32 rvbar3_1; 457 u32 lpmcsr; 458 u8 res_244[0x400-0x244]; 459 u32 qspidqscr; 460 u32 ecgtxcmcr; 461 u32 sdhciovselcr; 462 u32 rcwpmuxcr0; 463 u32 usbdrvvbus_selcr; 464 u32 usbpwrfault_selcr; 465 u32 usb_refclk_selcr1; 466 u32 usb_refclk_selcr2; 467 u32 usb_refclk_selcr3; 468 u8 res_424[0x434 - 0x424]; 469 u32 rgmiipcr; 470 u32 res_438; 471 u32 rgmiipsr; 472 u32 pfepfcssr1; 473 u32 pfeintencr1; 474 u32 pfepfcssr2; 475 u32 pfeintencr2; 476 u32 pfeerrcr; 477 u32 pfeeerrintencr; 478 u32 pfeasbcr; 479 u32 pfebsbcr; 480 u8 res_460[0x484 - 0x460]; 481 u32 mdioselcr; 482 u8 res_468[0x600 - 0x488]; 483 u32 scratchrw[4]; 484 u8 res_610[0x680-0x610]; 485 u32 corebcr; 486 u8 res_684[0x1000-0x684]; 487 u32 pex1msiir; 488 u32 pex1msir; 489 u8 res_1008[0x2000-0x1008]; 490 u32 pex2; 491 u32 pex2msir; 492 u8 res_2008[0x3000-0x2008]; 493 u32 pex3msiir; 494 u32 pex3msir; 495}; 496 497/* Clocking */ 498struct ccsr_clk { 499 struct { 500 u32 clkcncsr; /* core cluster n clock control status */ 501 u8 res_004[0x0c]; 502 u32 clkcghwacsr; /* Clock generator n hardware accelerator */ 503 u8 res_014[0x0c]; 504 } clkcsr[4]; 505 u8 res_040[0x780]; /* 0x100 */ 506 struct { 507 u32 pllcngsr; 508 u8 res_804[0x1c]; 509 } pllcgsr[2]; 510 u8 res_840[0x1c0]; 511 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */ 512 u8 res_a04[0x1fc]; 513 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 514 u8 res_c04[0x1c]; 515 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 516 u8 res_c24[0x3dc]; 517}; 518 519/* System Counter */ 520struct sctr_regs { 521 u32 cntcr; 522 u32 cntsr; 523 u32 cntcv1; 524 u32 cntcv2; 525 u32 resv1[4]; 526 u32 cntfid0; 527 u32 cntfid1; 528 u32 resv2[1002]; 529 u32 counterid[12]; 530}; 531 532#define SRDS_MAX_LANES 4 533struct ccsr_serdes { 534 struct { 535 u32 rstctl; /* Reset Control Register */ 536#define SRDS_RSTCTL_RST 0x80000000 537#define SRDS_RSTCTL_RSTDONE 0x40000000 538#define SRDS_RSTCTL_RSTERR 0x20000000 539#define SRDS_RSTCTL_SWRST 0x10000000 540#define SRDS_RSTCTL_SDEN 0x00000020 541#define SRDS_RSTCTL_SDRST_B 0x00000040 542#define SRDS_RSTCTL_PLLRST_B 0x00000080 543 u32 pllcr0; /* PLL Control Register 0 */ 544#define SRDS_PLLCR0_POFF 0x80000000 545#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 546#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 547#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 548#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 549#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 550#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 551#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 552#define SRDS_PLLCR0_PLL_LCK 0x00800000 553#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 554#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 555#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 556#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 557#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 558#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 559#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 560 u32 pllcr1; /* PLL Control Register 1 */ 561#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 562 u32 res_0c; /* 0x00c */ 563 u32 pllcr3; 564 u32 pllcr4; 565 u32 pllcr5; /* 0x018 SerDes PLL1 Control 5 */ 566 u8 res_1c[0x20-0x1c]; 567 } bank[2]; 568 u8 res_40[0x90-0x40]; 569 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 570 u8 res_94[0xa0-0x94]; 571 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 572 u8 res_a4[0xb0-0xa4]; 573 u32 srdsgr0; /* 0xb0 General Register 0 */ 574 u8 res_b4[0x100-0xb4]; 575 struct { 576 u32 lnpssr0; /* 0x100, 0x120, 0x140, 0x160 */ 577 u8 res_104[0x120-0x104]; 578 } lnpssr[4]; /* Lane A, B, C, D */ 579 u8 res_180[0x200-0x180]; 580 u32 srdspccr0; /* 0x200 Protocol Configuration 0 */ 581 u32 srdspccr1; /* 0x204 Protocol Configuration 1 */ 582 u32 srdspccr2; /* 0x208 Protocol Configuration 2 */ 583 u32 srdspccr3; /* 0x20c Protocol Configuration 3 */ 584 u32 srdspccr4; /* 0x210 Protocol Configuration 4 */ 585 u32 srdspccr5; /* 0x214 Protocol Configuration 5 */ 586 u32 srdspccr6; /* 0x218 Protocol Configuration 6 */ 587 u32 srdspccr7; /* 0x21c Protocol Configuration 7 */ 588 u32 srdspccr8; /* 0x220 Protocol Configuration 8 */ 589 u32 srdspccr9; /* 0x224 Protocol Configuration 9 */ 590 u32 srdspccra; /* 0x228 Protocol Configuration A */ 591 u32 srdspccrb; /* 0x22c Protocol Configuration B */ 592 u8 res_230[0x800-0x230]; 593 struct { 594 u32 gcr0; /* 0x800 General Control Register 0 */ 595 u32 gcr1; /* 0x804 General Control Register 1 */ 596 u32 gcr2; /* 0x808 General Control Register 2 */ 597 u32 sscr0; 598 u32 recr0; /* 0x810 Receive Equalization Control */ 599 u32 recr1; 600 u32 tecr0; /* 0x818 Transmit Equalization Control */ 601 u32 sscr1; 602 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 603 u8 res_824[0x83c-0x824]; 604 u32 tcsr3; 605 } lane[4]; /* Lane A, B, C, D */ 606 u8 res_900[0x1000-0x900]; /* from 0x900 to 0xfff */ 607 struct { 608 u32 srdspexcr0; /* 0x1000, 0x1040, 0x1080 */ 609 u8 res_1004[0x1040-0x1004]; 610 } pcie[3]; 611 u8 res_10c0[0x1800-0x10c0]; 612 struct { 613 u8 res_1800[0x1804-0x1800]; 614 u32 srdssgmiicr1; /* 0x1804 SGMII Protocol Control 1 */ 615 u8 res_1808[0x180c-0x1808]; 616 u32 srdssgmiicr3; /* 0x180c SGMII Protocol Control 3 */ 617 } sgmii[4]; /* Lane A, B, C, D */ 618 u8 res_1840[0x1880-0x1840]; 619 struct { 620 u8 res_1880[0x1884-0x1880]; 621 u32 srdsqsgmiicr1; /* 0x1884 QSGMII Protocol Control 1 */ 622 u8 res_1888[0x188c-0x1888]; 623 u32 srdsqsgmiicr3; /* 0x188c QSGMII Protocol Control 3 */ 624 } qsgmii[2]; /* Lane A, B */ 625 u8 res_18a0[0x1980-0x18a0]; 626 struct { 627 u8 res_1980[0x1984-0x1980]; 628 u32 srdsxficr1; /* 0x1984 XFI Protocol Control 1 */ 629 u8 res_1988[0x198c-0x1988]; 630 u32 srdsxficr3; /* 0x198c XFI Protocol Control 3 */ 631 } xfi[2]; /* Lane A, B */ 632 u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ 633}; 634 635struct ccsr_gpio { 636 u32 gpdir; 637 u32 gpodr; 638 u32 gpdat; 639 u32 gpier; 640 u32 gpimr; 641 u32 gpicr; 642 u32 gpibe; 643}; 644 645/* MMU 500 */ 646#define SMMU_SCR0 (SMMU_BASE + 0x0) 647#define SMMU_SCR1 (SMMU_BASE + 0x4) 648#define SMMU_SCR2 (SMMU_BASE + 0x8) 649#define SMMU_SACR (SMMU_BASE + 0x10) 650#define SMMU_IDR0 (SMMU_BASE + 0x20) 651#define SMMU_IDR1 (SMMU_BASE + 0x24) 652 653#define SMMU_NSCR0 (SMMU_BASE + 0x400) 654#define SMMU_NSCR2 (SMMU_BASE + 0x408) 655#define SMMU_NSACR (SMMU_BASE + 0x410) 656 657#define SCR0_CLIENTPD_MASK 0x00000001 658#define SCR0_USFCFG_MASK 0x00000400 659 660#ifdef CONFIG_TFABOOT 661#define RCW_SRC_MASK (0xFF800000) 662#define RCW_SRC_BIT 23 663 664/* RCW SRC NAND */ 665#define RCW_SRC_NAND_MASK (0x100) 666#define RCW_SRC_NAND_VAL (0x100) 667#define NAND_RESERVED_MASK (0xFC) 668#define NAND_RESERVED_1 (0x0) 669#define NAND_RESERVED_2 (0x80) 670 671/* RCW SRC NOR */ 672#define RCW_SRC_NOR_MASK (0x1F0) 673#define NOR_8B_VAL (0x10) 674#define NOR_16B_VAL (0x20) 675#define SD_VAL (0x40) 676#define QSPI_VAL1 (0x44) 677#define QSPI_VAL2 (0x45) 678#endif 679 680uint get_svr(void); 681 682#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ 683