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6#ifndef _ASM_ARCH_CGC_H
7#define _ASM_ARCH_CGC_H
8
9enum cgc_clk {
10 DUMMY0_CLK,
11 DUMMY1_CLK,
12 LPOSC,
13 NIC_APCLK,
14 NIC_PERCLK,
15 XBAR_APCLK,
16 XBAR_BUSCLK,
17 AD_SLOWCLK,
18 SOSC,
19 SOSC_DIV1,
20 SOSC_DIV2,
21 SOSC_DIV3,
22 FRO,
23 FRO_DIV1,
24 FRO_DIV2,
25 FRO_DIV3,
26 PLL2,
27 PLL3,
28 PLL3_VCODIV,
29 PLL3_PFD0,
30 PLL3_PFD1,
31 PLL3_PFD2,
32 PLL3_PFD3,
33 PLL3_PFD0_DIV1,
34 PLL3_PFD0_DIV2,
35 PLL3_PFD1_DIV1,
36 PLL3_PFD1_DIV2,
37 PLL3_PFD2_DIV1,
38 PLL3_PFD2_DIV2,
39 PLL3_PFD3_DIV1,
40 PLL3_PFD3_DIV2,
41 LVDS,
42 LPAV_AXICLK,
43 LPAV_AHBCLK,
44 LPAV_BUSCLK,
45 PLL4,
46 PLL4_VCODIV,
47 PLL4_PFD0,
48 PLL4_PFD1,
49 PLL4_PFD2,
50 PLL4_PFD3,
51 PLL4_PFD0_DIV1,
52 PLL4_PFD0_DIV2,
53 PLL4_PFD1_DIV1,
54 PLL4_PFD1_DIV2,
55 PLL4_PFD2_DIV1,
56 PLL4_PFD2_DIV2,
57 PLL4_PFD3_DIV1,
58 PLL4_PFD3_DIV2,
59 CM33_BUSCLK,
60 PLL1_VCO_DIV,
61 PLL0_PFD2_DIV,
62 PLL0_PFD1_DIV,
63};
64
65struct cgc1_regs {
66 u32 verid;
67 u32 rsvd1[4];
68 u32 ca35clk;
69 u32 rsvd2[2];
70 u32 clkoutcfg;
71 u32 rsvd3[4];
72 u32 nicclk;
73 u32 xbarclk;
74 u32 rsvd4[21];
75 u32 clkdivrst;
76 u32 rsvd5[29];
77 u32 soscdiv;
78 u32 rsvd6[63];
79 u32 frodiv;
80 u32 rsvd7[189];
81 u32 pll2csr;
82 u32 rsvd8[3];
83 u32 pll2cfg;
84 u32 rsvd9;
85 u32 pll2denom;
86 u32 pll2num;
87 u32 pll2ss;
88 u32 rsvd10[55];
89 u32 pll3csr;
90 u32 pll3div_vco;
91 u32 pll3div_pfd0;
92 u32 pll3div_pfd1;
93 u32 pll3cfg;
94 u32 pll3pfdcfg;
95 u32 pll3denom;
96 u32 pll3num;
97 u32 pll3ss;
98 u32 pll3lock;
99 u32 rsvd11[54];
100 u32 enetstamp;
101 u32 rsvd12[67];
102 u32 pllusbcfg;
103 u32 rsvd13[59];
104 u32 aud_clk1;
105 u32 sai5_4_clk;
106 u32 tpm6_7clk;
107 u32 mqs1clk;
108 u32 rsvd14[60];
109 u32 lvdscfg;
110};
111
112struct cgc2_regs {
113 u32 verid;
114 u32 rsvd1[4];
115 u32 hificlk;
116 u32 rsvd2[2];
117 u32 clkoutcfg;
118 u32 rsvd3[6];
119 u32 niclpavclk;
120 u32 ddrclk;
121 u32 rsvd4[19];
122 u32 clkdivrst;
123 u32 rsvd5[29];
124 u32 soscdiv;
125 u32 rsvd6[63];
126 u32 frodiv;
127 u32 rsvd7[253];
128 u32 pll4csr;
129 u32 pll4div_vco;
130 u32 pll4div_pfd0;
131 u32 pll4div_pfd1;
132 u32 pll4cfg;
133 u32 pll4pfdcfg;
134 u32 pll4denom;
135 u32 pll4num;
136 u32 pll4ss;
137 u32 pll4lock;
138 u32 rsvd8[128];
139 u32 aud_clk2;
140 u32 sai7_6_clk;
141 u32 tpm8clk;
142 u32 rsvd9[1];
143 u32 spdifclk;
144 u32 rsvd10[59];
145 u32 lvdscfg;
146};
147
148u32 cgc_clk_get_rate(enum cgc_clk clk);
149void cgc1_pll3_init(ulong freq);
150void cgc1_pll2_init(ulong freq);
151void cgc1_soscdiv_init(void);
152void cgc1_init_core_clk(ulong freq);
153void cgc2_pll4_init(bool pll4_reset);
154void cgc2_ddrclk_config(u32 src, u32 div);
155void cgc2_ddrclk_wait_unlock(void);
156u32 cgc1_sosc_div(enum cgc_clk clk);
157void cgc1_enet_stamp_sel(u32 clk_src);
158void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd);
159void cgc2_pll4_pfddiv_config(enum cgc_clk pllpfddiv, u32 div);
160void cgc2_lpav_init(enum cgc_clk clk);
161#endif
162
