1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2014, Freescale Semiconductor 4 */ 5 6#ifndef _ASM_ARMV7_LS102XA_CONFIG_ 7#define _ASM_ARMV7_LS102XA_CONFIG_ 8 9#define OCRAM_BASE_ADDR 0x10000000 10#define OCRAM_SIZE 0x00010000 11#define OCRAM_BASE_S_ADDR 0x10010000 12#define OCRAM_S_SIZE 0x00010000 13 14#define CONFIG_SYS_DCSRBAR 0x20000000 15 16#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) 17#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000) 18 19#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) 20#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 21#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) 22#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) 23#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) 24#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) 25#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) 26#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) 27#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) 28#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) 29#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) 30#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) 31#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) 32#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) 33#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) 34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) 35#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) 36 37#define CFG_SYS_FSL_SEC_OFFSET 0x00700000 38#define CFG_SYS_FSL_JR0_OFFSET 0x00710000 39#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 40#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000 41 42#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 43#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 44 45#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000) 46 47#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) 48#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) 49#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000) 50 51#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000) 52 53#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) 54#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) 55 56#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) 57 58#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) 59#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) 60 61#define CONFIG_SYS_PCIE1_PHYS_BASE 0x4000000000ULL 62#define CONFIG_SYS_PCIE2_PHYS_BASE 0x4800000000ULL 63#define CONFIG_SYS_PCIE1_VIRT_ADDR 0x24000000UL 64#define CONFIG_SYS_PCIE2_VIRT_ADDR 0x34000000UL 65#define CONFIG_SYS_PCIE_MMAP_SIZE (192 * 1024 * 1024) /* 192M */ 66/* 67 * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR) 68 * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr. 69 */ 70#define CONFIG_SYS_PCIE1_PHYS_ADDR (CONFIG_SYS_PCIE1_PHYS_BASE + \ 71 CONFIG_SYS_PCIE1_VIRT_ADDR) 72#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \ 73 CONFIG_SYS_PCIE2_VIRT_ADDR) 74 75/* SATA */ 76#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) 77#ifdef CONFIG_DDR_SPD 78#define CONFIG_VERY_BIG_RAM 79#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) 80#endif 81 82#define DCU_LAYER_MAX_NUM 16 83 84#ifdef CONFIG_ARCH_LS1021A 85#else 86#error SoC not defined 87#endif 88 89#define FSL_IFC_COMPAT "fsl,ifc" 90#define FSL_QSPI_COMPAT "fsl,ls1021a-qspi" 91#define FSL_DSPI_COMPAT "fsl,ls1021a-v1.0-dspi" 92 93#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */ 94