1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. 4 */ 5 6#ifndef __ASM_ARCH_MX7_IMX_REGS_H__ 7#define __ASM_ARCH_MX7_IMX_REGS_H__ 8 9#define ARCH_MXC 10 11#define ROM_SW_INFO_ADDR 0x000001E8 12#define ROMCP_ARB_BASE_ADDR 0x00000000 13#define ROMCP_ARB_END_ADDR 0x00017FFF 14#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR 15#define CAAM_ARB_BASE_ADDR 0x00100000 16#define CAAM_ARB_END_ADDR 0x00107FFF 17#define GIC400_ARB_BASE_ADDR 0x31000000 18#define GIC400_ARB_END_ADDR 0x31007FFF 19#define APBH_DMA_ARB_BASE_ADDR 0x33000000 20#define APBH_DMA_ARB_END_ADDR 0x33007FFF 21#define M4_BOOTROM_BASE_ADDR 0x00180000 22 23#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 24#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 25#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 26 27/* GPV - PL301 configuration ports */ 28#define GPV0_BASE_ADDR 0x32000000 29#define GPV1_BASE_ADDR 0x32100000 30#define GPV2_BASE_ADDR 0x32200000 31#define GPV3_BASE_ADDR 0x32300000 32#define GPV4_BASE_ADDR 0x32400000 33#define GPV5_BASE_ADDR 0x32500000 34#define GPV6_BASE_ADDR 0x32600000 35#define GPV7_BASE_ADDR 0x32700000 36 37#define OCRAM_ARB_BASE_ADDR 0x00900000 38#define OCRAM_ARB_END_ADDR 0x0091FFFF 39#define OCRAM_EPDC_BASE_ADDR 0x00920000 40#define OCRAM_EPDC_END_ADDR 0x0093FFFF 41#define OCRAM_PXP_BASE_ADDR 0x00940000 42#define OCRAM_PXP_END_ADDR 0x00947FFF 43#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR 44#define IRAM_SIZE 0x00020000 45 46#define AIPS1_ARB_BASE_ADDR 0x30000000 47#define AIPS1_ARB_END_ADDR 0x303FFFFF 48#define AIPS2_ARB_BASE_ADDR 0x30400000 49#define AIPS2_ARB_END_ADDR 0x307FFFFF 50#define AIPS3_ARB_BASE_ADDR 0x30800000 51#define AIPS3_ARB_END_ADDR 0x30BFFFFF 52 53#define WEIM_ARB_BASE_ADDR 0x28000000 54#define WEIM_ARB_END_ADDR 0x2FFFFFFF 55 56#define QSPI0_ARB_BASE_ADDR 0x60000000 57#define QSPI0_ARB_END_ADDR 0x6FFFFFFF 58#define PCIE_ARB_BASE_ADDR 0x40000000 59#define PCIE_ARB_END_ADDR 0x4FFFFFFF 60#define PCIE_REG_BASE_ADDR 0x33800000 61#define PCIE_REG_END_ADDR 0x33803FFF 62 63#define MMDC0_ARB_BASE_ADDR 0x80000000 64#define MMDC0_ARB_END_ADDR 0xBFFFFFFF 65#define MMDC1_ARB_BASE_ADDR 0xC0000000 66#define MMDC1_ARB_END_ADDR 0xFFFFFFFF 67 68/* Cortex-A9 MPCore private memory region */ 69#define ARM_PERIPHBASE 0x31000000 70#define SCU_BASE_ADDR ARM_PERIPHBASE 71#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) 72#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) 73 74 75/* Defines for Blocks connected via AIPS (SkyBlue) */ 76#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 77#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 78#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 79 80/* DAP base-address */ 81#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR 82 83/* AIPS_TZ#1- On Platform */ 84#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) 85/* AIPS_TZ#1- Off Platform */ 86#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) 87 88#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR 89#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) 90#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) 91#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) 92#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) 93#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) 94#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) 95#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) 96#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) 97#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) 98#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) 99#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) 100#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) 101#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) 102#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR 103#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) 104#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) 105#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) 106#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) 107#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) 108#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) 109#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR 110#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) 111#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) 112#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) 113#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) 114#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) 115#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) 116#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) 117#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) 118#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) 119#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) 120#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) 121 122/* AIPS_TZ#2- On Platform */ 123#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) 124/* AIPS_TZ#2- Off Platform */ 125#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) 126#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) 127#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) 128#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) 129#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) 130#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) 131#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) 132#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) 133#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) 134#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) 135#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) 136#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) 137#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) 138#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) 139#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) 140#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR 141#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) 142#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) 143#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) 144#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) 145#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) 146#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) 147#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) 148#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) 149#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) 150#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) 151#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) 152#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) 153 154/* AIPS_TZ#3 - Global enable (0) */ 155#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) 156#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) 157#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) 158#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) 159#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) 160#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) 161#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) 162#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) 163#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) 164#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) 165#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) 166 167/* AIPS_TZ#3- On Platform */ 168#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) 169/* AIPS_TZ#3- Off Platform */ 170#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) 171#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR 172#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) 173#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) 174#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) 175#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) 176#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) 177#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) 178#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) 179#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) 180#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) 181#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) 182#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) 183#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) 184#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) 185#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) 186#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) 187#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) 188#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) 189#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) 190#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) 191#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 192#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 193#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 194#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 195#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) 196#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) 197#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) 198#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) 199#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) 200 201#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 202#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 203#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 204 205#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 206#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 207 208#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR 209#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR 210 211#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR 212#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR 213#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR 214#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR 215 216#define FEC_QUIRK_ENET_MAC 217#define SNVS_LPGPR 0x68 218#define CFG_SYS_FSL_SEC_OFFSET 0 219#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ 220 CFG_SYS_FSL_SEC_OFFSET) 221#define CFG_SYS_FSL_JR0_OFFSET 0x1000 222#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \ 223 CFG_SYS_FSL_JR0_OFFSET) 224#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 225#include <asm/mach-imx/regs-lcdif.h> 226#include <asm/types.h> 227#include <linux/bitops.h> 228 229extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 230 231/* System Reset Controller (SRC) */ 232struct src { 233 u32 scr; 234 u32 a7rcr0; 235 u32 a7rcr1; 236 u32 m4rcr; 237 u32 reserved1; 238 u32 ercr; 239 u32 reserved2; 240 u32 hsicphy_rcr; 241 u32 usbophy1_rcr; 242 u32 usbophy2_rcr; 243 u32 mipiphy_rcr; 244 u32 pciephy_rcr; 245 u32 reserved3[10]; 246 u32 sbmr1; 247 u32 srsr; 248 u32 reserved4[2]; 249 u32 sisr; 250 u32 simr; 251 u32 sbmr2; 252 u32 gpr1; 253 u32 gpr2; 254 u32 gpr3; 255 u32 gpr4; 256 u32 gpr5; 257 u32 gpr6; 258 u32 gpr7; 259 u32 gpr8; 260 u32 gpr9; 261 u32 gpr10; 262 u32 reserved5[985]; 263 u32 ddrc_rcr; 264}; 265 266#define src_base ((struct src *)SRC_BASE_ADDR) 267 268#define SRC_M4_REG_OFFSET 0xC 269#define SRC_M4C_NON_SCLR_RST_OFFSET 0 270#define SRC_M4C_NON_SCLR_RST_MASK BIT(0) 271#define SRC_M4_ENABLE_OFFSET 3 272#define SRC_M4_ENABLE_MASK BIT(3) 273 274#define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 275#define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) 276#define SRC_DDRC_RCR_DDRC_PRST_MASK (1 << 0) 277 278/* GPR0 Bit Fields */ 279#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u 280#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 281#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u 282#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 283#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u 284#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 285#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u 286#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 287#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u 288#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 289#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u 290#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 291#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u 292#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 293#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) 294#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 295/* GPR1 Bit Fields */ 296#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u 297#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 298#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u 299#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 300#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) 301#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u 302#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 303#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u 304#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 305#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) 306#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u 307#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 308#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u 309#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 310#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) 311#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u 312#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 313#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u 314#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 315#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) 316#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u 317#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 318#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u 319#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 320#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u 321#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 322#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u 323#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 324#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u 325#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 326#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u 327#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 328#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u 329#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 330#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u 331#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 332#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u 333#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 334#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u 335#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 336#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) 337#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u 338#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 339/* GPR2 Bit Fields */ 340#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u 341#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 342#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u 343#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 344#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u 345#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 346#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u 347#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 348#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u 349#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 350#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u 351#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 352#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u 353#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 354#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u 355#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 356#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u 357#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 358#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u 359#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 360#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u 361#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 362#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u 363#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 364#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u 365#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 366#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u 367#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 368#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u 369#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 370#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u 371#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 372#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u 373#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 374#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) 375#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u 376#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 377#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u 378#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 379#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u 380#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 381#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u 382#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 383#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u 384#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 385#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u 386#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 387#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u 388#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 389#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u 390#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 391/* GPR3 Bit Fields */ 392#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u 393#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 394#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u 395#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 396#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u 397#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 398#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u 399#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 400#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u 401#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 402#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u 403#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 404#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u 405#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 406#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u 407#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 408#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u 409#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 410#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u 411#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 412#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u 413#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 414#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u 415#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 416#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u 417#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 418#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u 419#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 420#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u 421#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 422#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u 423#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 424#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u 425#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 426#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u 427#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 428#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u 429#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 430#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u 431#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 432#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u 433#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 434#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u 435#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 436#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u 437#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 438#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u 439#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 440#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u 441#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 442#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u 443#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 444#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u 445#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 446#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u 447#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 448#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u 449#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 450#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u 451#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 452#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u 453#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 454#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u 455#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 456/* GPR4 Bit Fields */ 457#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u 458#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 459#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u 460#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 461#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u 462#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 463#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u 464#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 465#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u 466#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 467#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u 468#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 469#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u 470#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 471#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u 472#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 473#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u 474#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 475#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u 476#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 477#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u 478#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 479#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u 480#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 481#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u 482#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 483#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u 484#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 485#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u 486#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 487#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u 488#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 489#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u 490#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 491#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) 492#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u 493#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 494#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) 495/* GPR5 Bit Fields */ 496#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u 497#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 498#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u 499#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 500#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u 501#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 502#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u 503#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 504#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u 505#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 506#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u 507#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 508#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u 509#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 510#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u 511#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 512#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u 513#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 514#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u 515#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 516#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u 517#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 518#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u 519#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 520#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u 521#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 522#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u 523#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 524#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u 525#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 526#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u 527#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 528#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u 529#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 530/* GPR6 Bit Fields */ 531#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u 532#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 533#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u 534#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 535#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u 536#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 537#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u 538#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 539/* GPR7 Bit Fields */ 540#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u 541#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 542#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u 543#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 544#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u 545#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 546#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u 547#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 548#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u 549#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 550#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) 551#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u 552#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 553#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u 554#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 555#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u 556#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 557#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u 558#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 559#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u 560#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 561#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) 562#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u 563#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 564#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u 565#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 566/* GPR8 Bit Fields */ 567#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u 568#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 569#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) 570#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u 571#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 572/* GPR9 Bit Fields */ 573#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u 574#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 575#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu 576#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 577#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) 578/* GPR10 Bit Fields */ 579#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u 580#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 581#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u 582#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 583#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u 584#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 585#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u 586#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 587#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u 588#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 589#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) 590/* GPR11 Bit Fields */ 591#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u 592#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 593#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu 594#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 595#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) 596#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u 597#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 598#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u 599#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 600#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) 601#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u 602#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 603#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u 604#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 605#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) 606/* GPR12 Bit Fields */ 607#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u 608#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 609#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u 610#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 611#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u 612#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 613#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u 614#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 615#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u 616#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 617#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u 618#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 619#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) 620#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u 621#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 622#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) 623#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u 624#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 625#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) 626/* GPR13 Bit Fields */ 627#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u 628#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 629#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u 630#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 631#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u 632#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 633#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u 634#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 635#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u 636#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 637#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u 638#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 639#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u 640#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 641#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u 642#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 643#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u 644#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 645#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u 646#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 647#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u 648#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 649#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u 650#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 651#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u 652#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 653#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u 654#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 655#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u 656#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 657#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u 658#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 659#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u 660#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 661#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) 662#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u 663#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 664#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) 665#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u 666#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 667#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u 668#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 669#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u 670#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 671#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u 672#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 673/* GPR14 Bit Fields */ 674#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u 675#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 676#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u 677#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 678/* GPR15 Bit Fields */ 679#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u 680#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 681#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u 682#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 683#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu 684#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 685#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) 686#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u 687#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 688#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) 689/* GPR16 Bit Fields */ 690#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u 691#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 692#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) 693#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u 694#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 695#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u 696#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 697#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u 698#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 699#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u 700#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 701#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u 702#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 703#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) 704#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u 705#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 706#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u 707#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 708#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u 709#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 710#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u 711#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 712#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) 713#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u 714#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 715#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u 716#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 717#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u 718#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 719#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) 720#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u 721#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 722#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u 723#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 724#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u 725#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 726/* GPR17 Bit Fields */ 727#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu 728#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 729#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) 730#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u 731#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 732#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) 733/* GPR18 Bit Fields */ 734#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u 735#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 736#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) 737#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u 738#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 739#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) 740#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u 741#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 742#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) 743#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u 744#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 745#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) 746#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u 747#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 748#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u 749#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 750#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) 751#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u 752#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 753#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) 754#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u 755#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 756#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u 757#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 758#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u 759#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 760#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u 761#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 762/* GPR19 Bit Fields */ 763#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u 764#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 765#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u 766#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 767#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) 768#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u 769#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 770#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u 771#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 772/* GPR20 Bit Fields */ 773#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu 774#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 775#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) 776#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u 777#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 778#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) 779#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u 780#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 781#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) 782#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u 783#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 784#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u 785#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 786#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u 787#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 788#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) 789/* GPR21 Bit Fields */ 790#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u 791#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 792#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) 793#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u 794#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 795#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) 796#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u 797#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 798#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) 799#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u 800#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 801#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) 802#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u 803#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 804#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) 805#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u 806#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 807#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) 808#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u 809#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 810#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u 811#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 812/* GPR22 Bit Fields */ 813#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u 814#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 815#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) 816#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u 817#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 818#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u 819#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 820#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u 821#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 822#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u 823#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 824#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u 825#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 826#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u 827#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 828#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u 829#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 830 831#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) 832#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) 833#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) 834 835struct iomuxc { 836 u32 gpr[23]; 837 /* mux and pad registers */ 838}; 839 840struct iomuxc_gpr_base_regs { 841 u32 gpr[23]; /* 0x000 */ 842}; 843 844/* 845 * CSPI register definitions 846 */ 847#define MXC_SPI_BASE_ADDRESSES \ 848 ECSPI1_BASE_ADDR, \ 849 ECSPI2_BASE_ADDR, \ 850 ECSPI3_BASE_ADDR, \ 851 ECSPI4_BASE_ADDR 852 853#define CSU_INIT_SEC_LEVEL0 0x00FF00FF 854#define CSU_NUM_REGS 64 855 856struct ocotp_regs { 857 u32 ctrl; 858 u32 ctrl_set; 859 u32 ctrl_clr; 860 u32 ctrl_tog; 861 u32 timing; 862 u32 rsvd0[3]; 863 u32 data0; 864 u32 rsvd1[3]; 865 u32 data1; 866 u32 rsvd2[3]; 867 u32 data2; 868 u32 rsvd3[3]; 869 u32 data3; 870 u32 rsvd4[3]; 871 u32 read_ctrl; 872 u32 rsvd5[3]; 873 u32 read_fuse_data0; 874 u32 rsvd6[3]; 875 u32 read_fuse_data1; 876 u32 rsvd7[3]; 877 u32 read_fuse_data2; 878 u32 rsvd8[3]; 879 u32 read_fuse_data3; 880 u32 rsvd9[3]; 881 u32 sw_sticky; 882 u32 rsvd10[3]; 883 u32 scs; 884 u32 scs_set; 885 u32 scs_clr; 886 u32 scs_tog; 887 u32 crc_addr; 888 u32 rsvd11[3]; 889 u32 crc_value; 890 u32 rsvd12[3]; 891 u32 version; 892 u32 rsvd13[0xc3]; 893 894 struct fuse_bank { /* offset 0x400 */ 895 u32 fuse_regs[0x10]; 896 } bank[16]; 897}; 898 899struct fuse_bank0_regs { 900 u32 lock; 901 u32 rsvd0[3]; 902 u32 tester0; 903 u32 rsvd1[3]; 904 u32 tester1; 905 u32 rsvd2[3]; 906 u32 tester2; 907 u32 rsvd3[3]; 908}; 909 910struct fuse_bank1_regs { 911 u32 tester3; 912 u32 rsvd0[3]; 913 u32 tester4; 914 u32 rsvd1[3]; 915 u32 tester5; 916 u32 rsvd2[3]; 917 u32 cfg0; 918 u32 rsvd3[3]; 919}; 920 921struct fuse_bank2_regs { 922 u32 cfg1; 923 u32 rsvd0[3]; 924 u32 cfg2; 925 u32 rsvd1[3]; 926 u32 cfg3; 927 u32 rsvd2[3]; 928 u32 cfg4; 929 u32 rsvd3[3]; 930}; 931 932struct fuse_bank3_regs { 933 u32 mem_trim0; 934 u32 rsvd0[3]; 935 u32 mem_trim1; 936 u32 rsvd1[3]; 937 u32 ana0; 938 u32 rsvd2[3]; 939 u32 ana1; 940 u32 rsvd3[3]; 941}; 942 943struct fuse_bank8_regs { 944 u32 sjc_resp_low; 945 u32 rsvd0[3]; 946 u32 sjc_resp_high; 947 u32 rsvd1[3]; 948 u32 usb_id; 949 u32 rsvd2[3]; 950 u32 field_return; 951 u32 rsvd3[3]; 952}; 953 954struct fuse_bank9_regs { 955 u32 mac_addr0; 956 u32 rsvd0[3]; 957 u32 mac_addr1; 958 u32 rsvd1[3]; 959 u32 mac_addr2; 960 u32 rsvd2[7]; 961}; 962 963struct aipstz_regs { 964 u32 mprot0; 965 u32 mprot1; 966 u32 rsvd[0xe]; 967 u32 opacr0; 968 u32 opacr1; 969 u32 opacr2; 970 u32 opacr3; 971 u32 opacr4; 972}; 973 974struct wdog_regs { 975 u16 wcr; /* Control */ 976 u16 wsr; /* Service */ 977 u16 wrsr; /* Reset Status */ 978 u16 wicr; /* Interrupt Control */ 979 u16 wmcr; /* Miscellaneous Control */ 980}; 981 982struct dbg_monitor_regs { 983 u32 ctrl[4]; /* Control */ 984 u32 master_en[4]; /* Master enable */ 985 u32 irq[4]; /* IRQ */ 986 u32 trap_addr_low[4]; /* Trap address low */ 987 u32 trap_addr_high[4]; /* Trap address high */ 988 u32 trap_id[4]; /* Trap ID */ 989 u32 snvs_addr[4]; /* SNVS address */ 990 u32 snvs_data[4]; /* SNVS data */ 991 u32 snvs_info[4]; /* SNVS info */ 992 u32 version[4]; /* Version */ 993}; 994 995struct rdc_regs { 996 u32 vir; /* Version information */ 997 u32 reserved1[8]; 998 u32 stat; /* Status */ 999 u32 intctrl; /* Interrupt and Control */ 1000 u32 intstat; /* Interrupt Status */
1001 u32 reserved2[116]; 1002 u32 mda[27]; /* Master Domain Assignment */ 1003 u32 reserved3[101]; 1004 u32 pdap[118]; /* Peripheral Domain Access Permissions */ 1005 u32 reserved4[138]; 1006 struct { 1007 u32 mrsa; /* Memory Region Start Address */ 1008 u32 mrea; /* Memory Region End Address */ 1009 u32 mrc; /* Memory Region Control */ 1010 u32 mrvs; /* Memory Region Violation Status */ 1011 } mem_region[52]; 1012}; 1013 1014struct rdc_sema_regs { 1015 u8 gate[64]; /* Gate */ 1016 u16 rstgt; /* Reset Gate */ 1017}; 1018 1019#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR 1020 1021#define LCDIF_CTRL_SFTRST (1 << 31) 1022#define LCDIF_CTRL_CLKGATE (1 << 30) 1023#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) 1024#define LCDIF_CTRL_READ_WRITEB (1 << 28) 1025#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) 1026#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) 1027#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) 1028#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 1029#define LCDIF_CTRL_DVI_MODE (1 << 20) 1030#define LCDIF_CTRL_BYPASS_COUNT (1 << 19) 1031#define LCDIF_CTRL_VSYNC_MODE (1 << 18) 1032#define LCDIF_CTRL_DOTCLK_MODE (1 << 17) 1033#define LCDIF_CTRL_DATA_SELECT (1 << 16) 1034#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) 1035#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 1036#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) 1037#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 1038#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) 1039#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 1040#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) 1041#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) 1042#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) 1043#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) 1044#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) 1045#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 1046#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) 1047#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) 1048#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) 1049#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) 1050#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) 1051#define LCDIF_CTRL_LCDIF_MASTER (1 << 5) 1052#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) 1053#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) 1054#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) 1055#define LCDIF_CTRL_RUN (1 << 0) 1056 1057#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) 1058#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) 1059#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) 1060#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) 1061#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) 1062#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) 1063#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) 1064#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) 1065#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) 1066#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 1067#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) 1068#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) 1069#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) 1070#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) 1071#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) 1072#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) 1073#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) 1074#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) 1075#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) 1076#define LCDIF_CTRL1_MODE86 (1 << 1) 1077#define LCDIF_CTRL1_RESET (1 << 0) 1078 1079#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) 1080#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 1081#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) 1082#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) 1083#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) 1084#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) 1085#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) 1086#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) 1087#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) 1088#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 1089#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) 1090#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) 1091#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) 1092#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) 1093#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) 1094#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) 1095#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) 1096#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 1097#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) 1098#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) 1099#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) 1100#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) 1101#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) 1102#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) 1103#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) 1104#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) 1105#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) 1106#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) 1107#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 1108#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) 1109#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 1110 1111#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) 1112#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 1113#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) 1114#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 1115 1116#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff 1117#define LCDIF_CUR_BUF_ADDR_OFFSET 0 1118 1119#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff 1120#define LCDIF_NEXT_BUF_ADDR_OFFSET 0 1121 1122#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) 1123#define LCDIF_TIMING_CMD_HOLD_OFFSET 24 1124#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) 1125#define LCDIF_TIMING_CMD_SETUP_OFFSET 16 1126#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) 1127#define LCDIF_TIMING_DATA_HOLD_OFFSET 8 1128#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) 1129#define LCDIF_TIMING_DATA_SETUP_OFFSET 0 1130 1131#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) 1132#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) 1133#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) 1134#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) 1135#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) 1136#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) 1137#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) 1138#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) 1139#define LCDIF_VDCTRL0_HALF_LINE (1 << 19) 1140#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) 1141#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff 1142#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 1143 1144#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff 1145#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 1146 1147#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) 1148#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 1149#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff 1150#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 1151 1152#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) 1153#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) 1154#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) 1155#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 1156#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) 1157#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 1158 1159#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) 1160#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 1161#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) 1162#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff 1163#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 1164 1165 1166extern void check_cpu_temperature(void); 1167 1168extern void pcie_power_up(void); 1169extern void pcie_power_off(void); 1170 1171/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1172 * If boot from the other mode, USB0_PWD will keep reset value 1173 */ 1174#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ 1175 readl(USBOTG2_IPS_BASE_ADDR + 0x158)) 1176#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) 1177 1178struct bootrom_sw_info { 1179 u8 reserved_1; 1180 u8 boot_dev_instance; 1181 u8 boot_dev_type; 1182 u8 reserved_2; 1183 u32 arm_core_freq; 1184 u32 axi_freq; 1185 u32 ddr_freq; 1186 u32 gpt1_freq; 1187 u32 reserved_3[3]; 1188}; 1189 1190#endif /* __ASSEMBLY__ */ 1191#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ 1192