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6#ifndef _ASM_ARCH_GRF_RK3066_H
7#define _ASM_ARCH_GRF_RK3066_H
8
9#include <linux/bitops.h>
10#include <linux/bitfield.h>
11
12#define REG(name, h, l) \
13 name##_MASK = GENMASK(h, l), \
14 name##_SHIFT = __bf_shf(name##_MASK)
15
16struct rk3066_grf_gpio_lh {
17 u32 l;
18 u32 h;
19};
20
21struct rk3066_grf {
22 struct rk3066_grf_gpio_lh gpio_dir[7];
23 struct rk3066_grf_gpio_lh gpio_do[7];
24 struct rk3066_grf_gpio_lh gpio_en[7];
25
26 u32 gpio0a_iomux;
27 u32 gpio0b_iomux;
28 u32 gpio0c_iomux;
29 u32 gpio0d_iomux;
30
31 u32 gpio1a_iomux;
32 u32 gpio1b_iomux;
33 u32 gpio1c_iomux;
34 u32 gpio1d_iomux;
35
36 u32 gpio2a_iomux;
37 u32 gpio2b_iomux;
38 u32 gpio2c_iomux;
39 u32 gpio2d_iomux;
40
41 u32 gpio3a_iomux;
42 u32 gpio3b_iomux;
43 u32 gpio3c_iomux;
44 u32 gpio3d_iomux;
45
46 u32 gpio4a_iomux;
47 u32 gpio4b_iomux;
48 u32 gpio4c_iomux;
49 u32 gpio4d_iomux;
50
51 u32 reserved0[5];
52
53 u32 gpio6b_iomux;
54
55 u32 reserved1[2];
56
57 struct rk3066_grf_gpio_lh gpio_pull[7];
58
59 u32 soc_con0;
60 u32 soc_con1;
61 u32 soc_con2;
62
63 u32 soc_status0;
64
65 u32 dmac1_con[3];
66 u32 dmac2_con[4];
67
68 u32 uoc0_con[3];
69 u32 uoc1_con[4];
70 u32 ddrc_con;
71 u32 ddrc_stat;
72
73 u32 reserved2[10];
74
75 u32 os_reg[4];
76};
77
78check_member(rk3066_grf, os_reg[3], 0x01d4);
79
80
81enum {
82 REG(GPIO1B1, 2, 2),
83 GPIO1B1_GPIO = 0,
84 GPIO1B1_UART2_SOUT,
85
86 REG(GPIO1B0, 0, 0),
87 GPIO1B0_GPIO = 0,
88 GPIO1B0_UART2_SIN
89};
90
91
92enum {
93 REG(GPIO3B6, 12, 12),
94 GPIO3B6_GPIO = 0,
95 GPIO3B6_SDMMC0_DECTN,
96
97 REG(GPIO3B5, 10, 10),
98 GPIO3B5_GPIO = 0,
99 GPIO3B5_SDMMC0_DATA3,
100
101 REG(GPIO3B4, 8, 8),
102 GPIO3B4_GPIO = 0,
103 GPIO3B4_SDMMC0_DATA2,
104
105 REG(GPIO3B3, 6, 6),
106 GPIO3B3_GPIO = 0,
107 GPIO3B3_SDMMC0_DATA1,
108
109 REG(GPIO3B2, 4, 4),
110 GPIO3B2_GPIO = 0,
111 GPIO3B2_SDMMC0_DATA0,
112
113 REG(GPIO3B1, 2, 2),
114 GPIO3B1_GPIO = 0,
115 GPIO3B1_SDMMC0_CMD,
116
117 REG(GPIO3B0, 0, 0),
118 GPIO3B0_GPIO = 0,
119 GPIO3B0_SDMMC0_CLKOUT,
120};
121
122
123enum {
124 REG(SMC_MUX_CON, 13, 13),
125
126 REG(NOC_REMAP, 12, 12),
127
128 REG(EMMC_FLASH_SEL, 11, 11),
129
130 REG(TZPC_REVISION, 10, 7),
131
132 REG(L2CACHE_ACC, 6, 5),
133
134 REG(L2RD_WAIT, 4, 3),
135
136 REG(IMEMRD_WAIT, 2, 1),
137
138 REG(SOC_REMAP, 0, 0),
139};
140
141
142enum {
143 REG(RKI2C4_SEL, 15, 15),
144
145 REG(RKI2C3_SEL, 14, 14),
146
147 REG(RKI2C2_SEL, 13, 13),
148
149 REG(RKI2C1_SEL, 12, 12),
150
151 REG(RKI2C0_SEL, 11, 11),
152
153 REG(VCODEC_SEL, 10, 10),
154
155 REG(PERI_EMEM_PAUSE, 9, 9),
156
157 REG(PERI_USB_PAUSE, 8, 8),
158
159 REG(SMC_MUX_MODE_0, 6, 6),
160
161 REG(SMC_SRAM_MW_0, 5, 4),
162
163 REG(SMC_REMAP_0, 3, 3),
164
165 REG(SMC_A_GT_M0_SYNC, 2, 2),
166
167 REG(EMAC_SPEED, 1, 1),
168
169 REG(EMAC_MODE, 0, 0),
170};
171
172
173enum {
174 REG(MSCH4_MAINDDR3, 7, 7),
175 MSCH4_MAINDDR3_DDR3 = 1,
176
177 REG(EMAC_NEWRCV_EN, 6, 6),
178
179 REG(SW_ADDR15_EN, 5, 5),
180
181 REG(SW_ADDR16_EN, 4, 4),
182
183 REG(SW_ADDR17_EN, 3, 3),
184
185 REG(BANK2_TO_RANK_EN, 2, 2),
186
187 REG(RANK_TO_ROW15_EN, 1, 1),
188
189 REG(UPCTL_C_ACTIVE_IN, 0, 0),
190 UPCTL_C_ACTIVE_IN_MAY = 0,
191 UPCTL_C_ACTIVE_IN_WILL,
192};
193
194
195enum {
196 REG(DTO_LB, 12, 11),
197
198 REG(DTO_TE, 10, 9),
199
200 REG(DTO_PDR, 8, 7),
201
202 REG(DTO_PDD, 6, 5),
203
204 REG(DTO_IOM, 4, 3),
205
206 REG(DTO_OE, 2, 1),
207
208 REG(ATO_AE, 0, 0),
209};
210#endif
211
