LXR uboot/arch/arm/mach-exynos/include/mach/spi.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * (C) Copyright 2012 SAMSUNG Electronics
   4 * Padmavathi Venna <padma.v@samsung.com>
   5 */
   6
   7#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
   8#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
   9
  10#ifndef __ASSEMBLY__
  11
  12/* SPI peripheral register map; padded to 64KB */
  13struct exynos_spi {
  14        unsigned int            ch_cfg;         /* 0x00 */
  15        unsigned char           reserved0[4];
  16        unsigned int            mode_cfg;       /* 0x08 */
  17        unsigned int            cs_reg;         /* 0x0c */
  18        unsigned char           reserved1[4];
  19        unsigned int            spi_sts;        /* 0x14 */
  20        unsigned int            tx_data;        /* 0x18 */
  21        unsigned int            rx_data;        /* 0x1c */
  22        unsigned int            pkt_cnt;        /* 0x20 */
  23        unsigned char           reserved2[4];
  24        unsigned int            swap_cfg;       /* 0x28 */
  25        unsigned int            fb_clk;         /* 0x2c */
  26        unsigned char           padding[0xffd0];
  27};
  28
  29#define EXYNOS_SPI_MAX_FREQ     50000000
  30
  31#define SPI_TIMEOUT_MS          10
  32#define SF_READ_DATA_CMD        0x3
  33
  34/* SPI_CHCFG */
  35#define SPI_CH_HS_EN            (1 << 6)
  36#define SPI_CH_RST              (1 << 5)
  37#define SPI_SLAVE_MODE          (1 << 4)
  38#define SPI_CH_CPOL_L           (1 << 3)
  39#define SPI_CH_CPHA_B           (1 << 2)
  40#define SPI_RX_CH_ON            (1 << 1)
  41#define SPI_TX_CH_ON            (1 << 0)
  42
  43/* SPI_MODECFG */
  44#define SPI_MODE_CH_WIDTH_WORD  (0x2 << 29)
  45#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
  46
  47/* SPI_CSREG */
  48#define SPI_SLAVE_SIG_INACT     (1 << 0)
  49
  50/* SPI_STS */
  51#define SPI_ST_TX_DONE          (1 << 25)
  52#define SPI_FIFO_LVL_MASK       0x1ff
  53#define SPI_TX_LVL_OFFSET       6
  54#define SPI_RX_LVL_OFFSET       15
  55
  56/* Feedback Delay */
  57#define SPI_CLK_BYPASS          (0 << 0)
  58#define SPI_FB_DELAY_90         (1 << 0)
  59#define SPI_FB_DELAY_180        (2 << 0)
  60#define SPI_FB_DELAY_270        (3 << 0)
  61
  62/* Packet Count */
  63#define SPI_PACKET_CNT_EN       (1 << 16)
  64
  65/* Swap config */
  66#define SPI_TX_SWAP_EN          (1 << 0)
  67#define SPI_TX_BYTE_SWAP        (1 << 2)
  68#define SPI_TX_HWORD_SWAP       (1 << 3)
  69#define SPI_TX_BYTE_SWAP        (1 << 2)
  70#define SPI_RX_SWAP_EN          (1 << 4)
  71#define SPI_RX_BYTE_SWAP        (1 << 6)
  72#define SPI_RX_HWORD_SWAP       (1 << 7)
  73
  74#endif /* __ASSEMBLY__ */
  75#endif
  76