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7#include <common.h>
8#include <dwc3-uboot.h>
9#include <efi.h>
10#include <efi_loader.h>
11#include <errno.h>
12#include <miiphy.h>
13#include <netdev.h>
14#include <spl.h>
15#include <usb.h>
16#include <asm/io.h>
17#include <asm/mach-imx/iomux-v3.h>
18#include <asm-generic/gpio.h>
19#include <asm/arch/imx8mp_pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/mach-imx/gpio.h>
22#include <asm/mach-imx/mxc_i2c.h>
23#include <asm/arch/clock.h>
24#include <asm/mach-imx/dma.h>
25#include <linux/delay.h>
26#include <linux/kernel.h>
27#include <power/pmic.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#ifdef CONFIG_NAND_MXS
32static void setup_gpmi_nand(void)
33{
34 init_nand_clk();
35}
36#endif
37
38#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
39struct efi_fw_image fw_images[] = {
40#if defined(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)
41 {
42 .image_type_id = IMX8MP_RSB3720A1_4G_FIT_IMAGE_GUID,
43 .fw_name = u"IMX8MP-RSB3720-FIT",
44 .image_index = 1,
45 },
46#elif defined(CONFIG_TARGET_IMX8MP_RSB3720A1_6G)
47 {
48 .image_type_id = IMX8MP_RSB3720A1_6G_FIT_IMAGE_GUID,
49 .fw_name = u"IMX8MP-RSB3720-FIT",
50 .image_index = 1,
51 },
52#endif
53};
54
55struct efi_capsule_update_info update_info = {
56 .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1",
57 .images = fw_images,
58};
59
60u8 num_image_type_guids = ARRAY_SIZE(fw_images);
61#endif
62
63
64int board_early_init_f(void)
65{
66 init_uart_clk(2);
67
68 return 0;
69}
70
71#ifdef CONFIG_OF_BOARD_SETUP
72int ft_board_setup(void *blob, struct bd_info *bd)
73{
74 return 0;
75}
76#endif
77
78#ifdef CONFIG_FEC_MXC
79#define FEC_RST_PAD IMX_GPIO_NR(4, 2)
80static const iomux_v3_cfg_t fec1_rst_pads[] = {
81 MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
82};
83
84static void setup_iomux_fec(void)
85{
86 imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
87 ARRAY_SIZE(fec1_rst_pads));
88
89 gpio_request(FEC_RST_PAD, "fec1_rst");
90 gpio_direction_output(FEC_RST_PAD, 0);
91 mdelay(15);
92 gpio_direction_output(FEC_RST_PAD, 1);
93 mdelay(100);
94}
95
96static int setup_fec(void)
97{
98 struct iomuxc_gpr_base_regs *gpr =
99 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
100
101 setup_iomux_fec();
102
103
104 setbits_le32(&gpr->gpr[1], BIT(22));
105
106 return 0;
107}
108#endif
109
110#ifdef CONFIG_DWC_ETH_QOS
111#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
112static const iomux_v3_cfg_t eqos_rst_pads[] = {
113 MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
114};
115
116static void setup_iomux_eqos(void)
117{
118 imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
119 ARRAY_SIZE(eqos_rst_pads));
120
121 gpio_request(EQOS_RST_PAD, "eqos_rst");
122 gpio_direction_output(EQOS_RST_PAD, 0);
123 mdelay(15);
124 gpio_direction_output(EQOS_RST_PAD, 1);
125 mdelay(100);
126}
127
128static int setup_eqos(void)
129{
130 struct iomuxc_gpr_base_regs *gpr =
131 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
132
133 setup_iomux_eqos();
134
135
136 clrsetbits_le32(&gpr->gpr[1],
137 IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
138 setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
139
140 return set_clk_eqos(ENET_125MHZ);
141}
142#endif
143
144int board_phy_config(struct phy_device *phydev)
145{
146 if (IS_ENABLED(CONFIG_FEC_MXC) || IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
147
148 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
149 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
150
151 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
152 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
153 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
154 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
155
156 if (phydev->drv->config)
157 phydev->drv->config(phydev);
158 }
159
160 return 0;
161}
162
163#define DISPMIX 13
164#define MIPI 15
165
166#define WDOG_TRIG IMX_GPIO_NR(4, 20)
167
168static iomux_v3_cfg_t wdt_trig[] = {
169 MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
170};
171
172static void setup_iomux_wdt(void)
173{
174 imx_iomux_v3_setup_multiple_pads(wdt_trig, ARRAY_SIZE(wdt_trig));
175 gpio_request(WDOG_TRIG, "wdt_trig");
176 gpio_direction_output(WDOG_TRIG, 1);
177}
178
179int board_init(void)
180{
181#ifdef CONFIG_FEC_MXC
182 setup_fec();
183#endif
184
185#ifdef CONFIG_DWC_ETH_QOS
186
187 setup_eqos();
188#endif
189
190#ifdef CONFIG_NAND_MXS
191 setup_gpmi_nand();
192#endif
193
194 setup_iomux_wdt();
195
196 return 0;
197}
198
199int board_late_init(void)
200{
201 if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
202 env_set("board_name", "RSB3720A1");
203 env_set("board_rev", "iMX8MP");
204 }
205
206 return 0;
207}
208
209#ifdef CONFIG_SPL_MMC
210#define UBOOT_RAW_SECTOR_OFFSET 0x40
211unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
212{
213 u32 boot_dev = spl_boot_device();
214
215 switch (boot_dev) {
216 case BOOT_DEVICE_MMC2:
217 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
218 default:
219 return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
220 }
221}
222#endif
223
