LXR uboot/board/bticino/mamoj/spl.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
   4 * Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
   5 * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
   6 */
   7
   8#include <common.h>
   9#include <init.h>
  10#include <serial.h>
  11#include <spl.h>
  12#include <asm/global_data.h>
  13#include <linux/delay.h>
  14
  15#include <asm/io.h>
  16#include <linux/sizes.h>
  17
  18#include <asm/arch/clock.h>
  19#include <asm/arch/crm_regs.h>
  20#include <asm/arch/iomux.h>
  21#include <asm/arch/mx6-ddr.h>
  22#include <asm/arch/mx6-pins.h>
  23#include <asm/arch/sys_proto.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27#define IMX6SDL_DRIVE_STRENGTH          0x28
  28#define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29                        PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  30
  31static iomux_v3_cfg_t const uart3_pads[] = {
  32        IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  33        IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  34};
  35
  36#ifdef CONFIG_SPL_OS_BOOT
  37int spl_start_uboot(void)
  38{
  39        /* break into full u-boot on 'c' */
  40        if (serial_tstc() && serial_getc() == 'c')
  41                return 1;
  42
  43        return 0;
  44}
  45#endif
  46
  47struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  48        .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  49        .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  50        .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  51        .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  52        .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  53        .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  54        .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  55        .dram_sdba2 = 0x00000000,
  56        .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  57        .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  58        .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  59        .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  60        .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  61        .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  62        .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  63        .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  64        .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  65        .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  66        .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  67        .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  68        .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  69        .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  70        .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  71        .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  72        .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  73        .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  74};
  75
  76struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  77        .grp_ddr_type = 0x000c0000,
  78        .grp_ddrmode_ctl = 0x00020000,
  79        .grp_ddrpke = 0x00000000,
  80        .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  81        .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  82        .grp_ddrmode = 0x00020000,
  83        .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  84        .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  85        .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  86        .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  87        .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  88        .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  89        .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  90        .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  91};
  92
  93static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  94        .mem_speed = 1600,
  95        .density = 4,
  96        .width = 32,
  97        .banks = 8,
  98        .rowaddr = 14,
  99        .coladdr = 10,
 100        .pagesz = 2,
 101        .trcd = 1375,
 102        .trcmin = 4875,
 103        .trasmin = 3500,
 104        .SRT = 0,
 105};
 106
 107static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
 108        .p0_mpwldectrl0 = 0x0042004b,
 109        .p0_mpwldectrl1 = 0x0038003c,
 110        .p0_mpdgctrl0 = 0x42340230,
 111        .p0_mpdgctrl1 = 0x0228022c,
 112        .p0_mprddlctl = 0x42444646,
 113        .p0_mpwrdlctl = 0x38382e2e,
 114};
 115
 116static struct mx6_ddr_sysinfo mem_dl = {
 117        .dsize          = 1,
 118        .cs1_mirror     = 0,
 119        /* config for full 4GB range so that get_mem_size() works */
 120        .cs_density     = 32,
 121        .ncs            = 1,
 122        .bi_on          = 1,
 123        .rtt_nom        = 1,
 124        .rtt_wr         = 1,
 125        .ralat          = 5,
 126        .walat          = 0,
 127        .mif3_mode      = 3,
 128        .rst_to_cke     = 0x23,
 129        .sde_to_rst     = 0x10,
 130        .refsel         = 1,
 131        .refr           = 7,
 132};
 133
 134static void spl_dram_init(void)
 135{
 136        mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 137        mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
 138
 139        udelay(100);
 140}
 141
 142static void ccgr_init(void)
 143{
 144        struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 145
 146        writel(0x00003f3f, &ccm->CCGR0);
 147        writel(0x0030fc00, &ccm->CCGR1);
 148        writel(0x000fc000, &ccm->CCGR2);
 149        writel(0x3f300000, &ccm->CCGR3);
 150        writel(0xff00f300, &ccm->CCGR4);
 151        writel(0x0f0000c3, &ccm->CCGR5);
 152        writel(0x000003cc, &ccm->CCGR6);
 153}
 154
 155void board_init_f(ulong dummy)
 156{
 157        ccgr_init();
 158
 159        /* setup AIPS and disable watchdog */
 160        arch_cpu_init();
 161
 162        gpr_init();
 163
 164        /* iomux */
 165        SETUP_IOMUX_PADS(uart3_pads);
 166
 167        /* setup GP timer */
 168        timer_init();
 169
 170        /* UART clocks enabled and gd valid - init serial console */
 171        preloader_console_init();
 172
 173        /* DDR initialization */
 174        spl_dram_init();
 175}
 176