LXR uboot/board/freescale/common/ics307

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <clock_legacy.h>
   8#include <log.h>
   9#include <asm/io.h>
  10
  11#include "ics307_clk.h"
  12
  13#if defined(CONFIG_FSL_NGPIXIS)
  14#include "ngpixis.h"
  15#define fpga_reg pixis
  16#elif defined(CONFIG_FSL_QIXIS)
  17#include "qixis.h"
  18#define fpga_reg ((struct qixis *)QIXIS_BASE)
  19#else
  20#include "pixis.h"
  21#define fpga_reg pixis
  22#endif
  23
  24/* define for SYS CLK or CLK1Frequency */
  25#define TTL             1
  26#define CLK2            0
  27#define CRYSTAL         0
  28#define MAX_VDW         (511 + 8)
  29#define MAX_RDW         (127 + 2)
  30#define MIN_VDW         (4 + 8)
  31#define MIN_RDW         (1 + 2)
  32#define NUM_OD_SETTING  8
  33/*
  34 * These defines cover the industrial temperature range part,
  35 * for commercial, change below to 400000 and 55000, respectively
  36 */
  37#define MAX_VCO         360000
  38#define MIN_VCO         60000
  39
  40/* decode S[0-2] to Output Divider (OD) */
  41static u8 ics307_s_to_od[] = {
  42        10, 2, 8, 4, 5, 7, 3, 6
  43};
  44
  45/*
  46 * Find one solution to generate required frequency for SYSCLK
  47 * out_freq: KHz, required frequency to the SYSCLK
  48 * the result will be retuned with component RDW, VDW, OD, TTL,
  49 * CLK2 and crystal
  50 */
  51unsigned long ics307_sysclk_calculator(unsigned long out_freq)
  52{
  53        const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
  54        unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
  55        unsigned long tmp_out, diff, result = 0;
  56        int found = 0;
  57
  58        for (odp = 0; odp < NUM_OD_SETTING; odp++) {
  59                od = ics307_s_to_od[odp];
  60                if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
  61                        continue;
  62                for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
  63                        /* Calculate the VDW */
  64                        vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
  65                        if (vdw > MAX_VDW)
  66                                vdw = MAX_VDW;
  67                        if (vdw < MIN_VDW)
  68                                continue;
  69                        /* Calculate the temp out frequency */
  70                        tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
  71                        diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
  72                        /*
  73                         * calculate the percent, the precision is 1/1000
  74                         * If greater than 1/1000, continue
  75                         * otherwise, we think the solution is we required
  76                         */
  77                        if (diff * 1000 / out_freq > 1)
  78                                continue;
  79                        else {
  80                                s_vdw = vdw;
  81                                s_rdw = rdw;
  82                                s_odp = odp;
  83                                found = 1;
  84                                break;
  85                        }
  86                }
  87        }
  88
  89        if (found)
  90                result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
  91                        CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
  92
  93        debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
  94                        ics307_s_to_od[s_odp]);
  95        return result;
  96}
  97
  98/*
  99 * Calculate frequency being generated by ICS307-02 clock chip based upon
 100 * the control bytes being programmed into it.
 101 */
 102static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
 103{
 104        const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
 105        unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 106        unsigned long rdw = cw2 & 0x7F;
 107        unsigned long od = ics307_s_to_od[cw0 & 0x7];
 108        unsigned long freq;
 109
 110        /*
 111         * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
 112         *
 113         * cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 114         * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 115         * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 116         *
 117         * R6:R0 = Reference Divider Word (RDW)
 118         * V8:V0 = VCO Divider Word (VDW)
 119         * S2:S0 = Output Divider Select (OD)
 120         * F1:F0 = Function of CLK2 Output
 121         * TTL = duty cycle
 122         * C1:C0 = internal load capacitance for cyrstal
 123         *
 124         */
 125
 126        freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
 127
 128        debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 129                        freq);
 130        return freq;
 131}
 132
 133unsigned long get_board_sys_clk(void)
 134{
 135        return ics307_clk_freq(
 136                        in_8(&fpga_reg->sclk[0]),
 137                        in_8(&fpga_reg->sclk[1]),
 138                        in_8(&fpga_reg->sclk[2]));
 139}
 140
 141#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 142unsigned long get_board_ddr_clk(void)
 143{
 144        return ics307_clk_freq(
 145                        in_8(&fpga_reg->dclk[0]),
 146                        in_8(&fpga_reg->dclk[1]),
 147                        in_8(&fpga_reg->dclk[2]));
 148}
 149#endif
 150