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6#include <common.h>
7#include <init.h>
8#include <asm/global_data.h>
9#include <asm/io.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux-vf610.h>
12#include <asm/arch/ddrmc-vf610.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/clock.h>
15#include <mmc.h>
16#include <fsl_esdhc_imx.h>
17#include <miiphy.h>
18#include <netdev.h>
19#include <i2c.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
24 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
25
26#define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
27 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
28
29#define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
30 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
31
32static struct ddrmc_cr_setting vf610twr_cr_settings[] = {
33
34 { DDRMC_CR97_WRLVL_EN, 97 },
35 { DDRMC_CR98_WRLVL_DL_0(0), 98 },
36 { DDRMC_CR99_WRLVL_DL_1(0), 99 },
37 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 },
38 { DDRMC_CR105_RDLVL_DL_0(0), 105 },
39 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 },
40 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 },
41
42 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
43 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
44 { DDRMC_CR120_AXI0_PRI1_RPRI(2) |
45 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
46 { DDRMC_CR121_AXI0_PRI3_RPRI(2) |
47 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
48 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
49 DDRMC_CR122_AXI0_PRIRLX(100), 122 },
50 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
51 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
52 { DDRMC_CR124_AXI1_PRIRLX(100), 124 },
53 { DDRMC_CR126_PHY_RDLAT(8), 126 },
54 { DDRMC_CR132_WRLAT_ADJ(5) |
55 DDRMC_CR132_RDLAT_ADJ(6), 132 },
56 { DDRMC_CR137_PHYCTL_DL(2), 137 },
57 { DDRMC_CR138_PHY_WRLV_MXDL(256) |
58 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
59 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
60 DDRMC_CR139_PHY_WRLV_DLL(3) |
61 DDRMC_CR139_PHY_WRLV_EN(3), 139 },
62 { DDRMC_CR140_PHY_WRLV_WW(64), 140 },
63 { DDRMC_CR143_RDLV_GAT_MXDL(1536) |
64 DDRMC_CR143_RDLV_MXDL(128), 143 },
65 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
66 DDRMC_CR144_PHY_RDLV_DLL(3) |
67 DDRMC_CR144_PHY_RDLV_EN(3), 144 },
68 { DDRMC_CR145_PHY_RDLV_RR(64), 145 },
69 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
70 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
71 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
72 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
73 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
74
75 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
76 DDRMC_CR154_PAD_ZQ_MODE(1) |
77 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
78 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
79 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 },
80 { DDRMC_CR158_TWR(6), 158 },
81 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
82 DDRMC_CR161_TODTH_WR(2), 161 },
83
84 { 0, -1 }
85};
86
87int dram_init(void)
88{
89 static const struct ddr3_jedec_timings timings = {
90 .tinit = 5,
91 .trst_pwron = 80000,
92 .cke_inactive = 200000,
93 .wrlat = 5,
94 .caslat_lin = 12,
95 .trc = 21,
96 .trrd = 4,
97 .tccd = 4,
98 .tbst_int_interval = 0,
99 .tfaw = 20,
100 .trp = 6,
101 .twtr = 4,
102 .tras_min = 15,
103 .tmrd = 4,
104 .trtp = 4,
105 .tras_max = 28080,
106 .tmod = 12,
107 .tckesr = 4,
108 .tcke = 3,
109 .trcd_int = 6,
110 .tras_lockout = 0,
111 .tdal = 12,
112 .bstlen = 3,
113 .tdll = 512,
114 .trp_ab = 6,
115 .tref = 3120,
116 .trfc = 44,
117 .tref_int = 0,
118 .tpdex = 3,
119 .txpdll = 10,
120 .txsnr = 48,
121 .txsr = 468,
122 .cksrx = 5,
123 .cksre = 5,
124 .freq_chg_en = 0,
125 .zqcl = 256,
126 .zqinit = 512,
127 .zqcs = 64,
128 .ref_per_zq = 64,
129 .zqcs_rotate = 0,
130 .aprebit = 10,
131 .cmd_age_cnt = 64,
132 .age_cnt = 64,
133 .q_fullness = 7,
134 .odt_rd_mapcs0 = 0,
135 .odt_wr_mapcs0 = 1,
136 .wlmrd = 40,
137 .wldqsen = 25,
138 };
139
140 ddrmc_setup_iomux(NULL, 0);
141
142 ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3);
143 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
144
145 return 0;
146}
147
148static void setup_iomux_uart(void)
149{
150 static const iomux_v3_cfg_t uart1_pads[] = {
151 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
152 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
153 };
154
155 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
156}
157
158static void setup_iomux_enet(void)
159{
160 static const iomux_v3_cfg_t enet0_pads[] = {
161 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL),
162 NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL),
163 NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL),
164 NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL),
165 NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL),
166 NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL),
167 NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL),
168 NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL),
169 NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL),
170 NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL),
171 };
172
173 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
174}
175
176static void setup_iomux_i2c(void)
177{
178 static const iomux_v3_cfg_t i2c0_pads[] = {
179 VF610_PAD_PTB14__I2C0_SCL,
180 VF610_PAD_PTB15__I2C0_SDA,
181 };
182
183 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
184}
185
186#ifdef CONFIG_NAND_VF610_NFC
187static void setup_iomux_nfc(void)
188{
189 static const iomux_v3_cfg_t nfc_pads[] = {
190 VF610_PAD_PTD31__NF_IO15,
191 VF610_PAD_PTD30__NF_IO14,
192 VF610_PAD_PTD29__NF_IO13,
193 VF610_PAD_PTD28__NF_IO12,
194 VF610_PAD_PTD27__NF_IO11,
195 VF610_PAD_PTD26__NF_IO10,
196 VF610_PAD_PTD25__NF_IO9,
197 VF610_PAD_PTD24__NF_IO8,
198 VF610_PAD_PTD23__NF_IO7,
199 VF610_PAD_PTD22__NF_IO6,
200 VF610_PAD_PTD21__NF_IO5,
201 VF610_PAD_PTD20__NF_IO4,
202 VF610_PAD_PTD19__NF_IO3,
203 VF610_PAD_PTD18__NF_IO2,
204 VF610_PAD_PTD17__NF_IO1,
205 VF610_PAD_PTD16__NF_IO0,
206 VF610_PAD_PTB24__NF_WE_B,
207 VF610_PAD_PTB25__NF_CE0_B,
208 VF610_PAD_PTB27__NF_RE_B,
209 VF610_PAD_PTC26__NF_RB_B,
210 VF610_PAD_PTC27__NF_ALE,
211 VF610_PAD_PTC28__NF_CLE
212 };
213
214 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
215}
216#endif
217
218
219static void setup_iomux_qspi(void)
220{
221 static const iomux_v3_cfg_t qspi0_pads[] = {
222 VF610_PAD_PTD0__QSPI0_A_QSCK,
223 VF610_PAD_PTD1__QSPI0_A_CS0,
224 VF610_PAD_PTD2__QSPI0_A_DATA3,
225 VF610_PAD_PTD3__QSPI0_A_DATA2,
226 VF610_PAD_PTD4__QSPI0_A_DATA1,
227 VF610_PAD_PTD5__QSPI0_A_DATA0,
228 VF610_PAD_PTD7__QSPI0_B_QSCK,
229 VF610_PAD_PTD8__QSPI0_B_CS0,
230 VF610_PAD_PTD9__QSPI0_B_DATA3,
231 VF610_PAD_PTD10__QSPI0_B_DATA2,
232 VF610_PAD_PTD11__QSPI0_B_DATA1,
233 VF610_PAD_PTD12__QSPI0_B_DATA0,
234 };
235
236 imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
237}
238
239#ifdef CONFIG_FSL_ESDHC_IMX
240struct fsl_esdhc_cfg esdhc_cfg[1] = {
241 {ESDHC1_BASE_ADDR},
242};
243
244int board_mmc_getcd(struct mmc *mmc)
245{
246
247 return 1;
248}
249
250int board_mmc_init(struct bd_info *bis)
251{
252 static const iomux_v3_cfg_t esdhc1_pads[] = {
253 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
254 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
255 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
256 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
257 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
258 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
259 };
260
261 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
262
263 imx_iomux_v3_setup_multiple_pads(
264 esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
265
266 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
267}
268#endif
269
270static void clock_init(void)
271{
272 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
273 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
274
275 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
276 CCM_CCGR0_UART1_CTRL_MASK);
277 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
278 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
279 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
280 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
281 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
282 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK |
283 CCM_CCGR2_QSPI0_CTRL_MASK);
284 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
285 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
286 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
287 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
288 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
289 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
290 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
291 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
292 CCM_CCGR7_SDHC1_CTRL_MASK);
293 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
294 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
295 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
296 CCM_CCGR10_NFC_CTRL_MASK);
297
298 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
299 ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
300 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
301 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
302
303 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
304 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
305 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,
306 CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN |
307 CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN |
308 CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN |
309 CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN |
310 CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) |
311 CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4));
312 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
313 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
314 CCM_CACRR_ARM_CLK_DIV(0));
315 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
316 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
317 CCM_CSCMR1_NFC_CLK_SEL(0));
318 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
319 CCM_CSCDR1_RMII_CLK_EN);
320 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
321 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
322 CCM_CSCDR2_NFC_EN);
323 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
324 CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
325 CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
326 CCM_CSCDR3_NFC_PRE_DIV(5));
327 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
328 CCM_CSCMR2_RMII_CLK_SEL(0));
329}
330
331static void mscm_init(void)
332{
333 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
334 int i;
335
336 for (i = 0; i < MSCM_IRSPRC_NUM; i++)
337 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
338}
339
340int board_phy_config(struct phy_device *phydev)
341{
342 if (phydev->drv->config)
343 phydev->drv->config(phydev);
344
345 return 0;
346}
347
348int board_early_init_f(void)
349{
350 clock_init();
351 mscm_init();
352
353 setup_iomux_uart();
354 setup_iomux_enet();
355 setup_iomux_i2c();
356 setup_iomux_qspi();
357#ifdef CONFIG_NAND_VF610_NFC
358 setup_iomux_nfc();
359#endif
360
361 return 0;
362}
363
364int board_init(void)
365{
366 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
367
368
369 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
370
371
372
373
374
375
376
377
378 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
379
380 return 0;
381}
382
383int checkboard(void)
384{
385 puts("Board: vf610twr\n");
386
387 return 0;
388}
389
