LXR uboot/board/phytec/phycore

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (C) 2019-2020 PHYTEC Messtechnik GmbH
   4 * Author: Teresa Remmet <t.remmet@phytec.de>
   5 */
   6
   7#include <common.h>
   8#include <asm/arch/clock.h>
   9#include <asm/arch/ddr.h>
  10#include <asm/arch/imx8mm_pins.h>
  11#include <asm/arch/sys_proto.h>
  12#include <asm/global_data.h>
  13#include <asm/mach-imx/boot_mode.h>
  14#include <asm/mach-imx/iomux-v3.h>
  15#include <hang.h>
  16#include <init.h>
  17#include <log.h>
  18#include <spl.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22int spl_board_boot_device(enum boot_device boot_dev_spl)
  23{
  24        switch (boot_dev_spl) {
  25        case SD2_BOOT:
  26        case MMC2_BOOT:
  27                return BOOT_DEVICE_MMC1;
  28        case SD3_BOOT:
  29        case MMC3_BOOT:
  30                return BOOT_DEVICE_MMC2;
  31        case QSPI_BOOT:
  32                return BOOT_DEVICE_NOR;
  33        case USB_BOOT:
  34                return BOOT_DEVICE_BOARD;
  35        default:
  36                return BOOT_DEVICE_NONE;
  37        }
  38}
  39
  40static void spl_dram_init(void)
  41{
  42        ddr_init(&dram_timing);
  43}
  44
  45int board_fit_config_name_match(const char *name)
  46{
  47        return 0;
  48}
  49
  50void board_init_f(ulong dummy)
  51{
  52        int ret;
  53
  54        arch_cpu_init();
  55
  56        init_uart_clk(2);
  57
  58        /* Clear the BSS. */
  59        memset(__bss_start, 0, __bss_end - __bss_start);
  60
  61        ret = spl_early_init();
  62        if (ret) {
  63                debug("spl_early_init() failed: %d\n", ret);
  64                hang();
  65        }
  66
  67        preloader_console_init();
  68
  69        enable_tzc380();
  70
  71        /* DDR initialization */
  72        spl_dram_init();
  73
  74        board_init_r(NULL, 0);
  75}
  76