LXR uboot/board/ti/ks2_evm/board

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * K2HK EVM : Board initialization
   4 *
   5 * (C) Copyright 2012-2014
   6 *     Texas Instruments Incorporated, <www.ti.com>
   7 */
   8
   9#include <common.h>
  10#include <image.h>
  11#include <init.h>
  12#include <asm/arch/clock.h>
  13#include <asm/arch/hardware.h>
  14#include <asm/ti-common/keystone_net.h>
  15
  16unsigned int external_clk[ext_clk_count] = {
  17        [sys_clk]       =       122880000,
  18        [alt_core_clk]  =       125000000,
  19        [pa_clk]        =       122880000,
  20        [tetris_clk]    =       125000000,
  21        [ddr3a_clk]     =       100000000,
  22        [ddr3b_clk]     =       100000000,
  23};
  24
  25unsigned int get_external_clk(u32 clk)
  26{
  27        unsigned int clk_freq;
  28
  29        switch (clk) {
  30        case sys_clk:
  31                clk_freq = 122880000;
  32                break;
  33        case alt_core_clk:
  34                clk_freq = 125000000;
  35                break;
  36        case pa_clk:
  37                clk_freq = 122880000;
  38                break;
  39        case tetris_clk:
  40                clk_freq = 125000000;
  41                break;
  42        case ddr3a_clk:
  43                clk_freq = 100000000;
  44                break;
  45        case ddr3b_clk:
  46                clk_freq = 100000000;
  47                break;
  48        default:
  49                clk_freq = 0;
  50                break;
  51        }
  52
  53        return clk_freq;
  54}
  55
  56static struct pll_init_data core_pll_config[NUM_SPDS] = {
  57        [SPD800]        = CORE_PLL_799,
  58        [SPD1000]       = CORE_PLL_999,
  59        [SPD1200]       = CORE_PLL_1200,
  60};
  61
  62s16 divn_val[16] = {
  63        0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
  64};
  65
  66static struct pll_init_data tetris_pll_config[] = {
  67        [SPD800]        = TETRIS_PLL_800,
  68        [SPD1000]       = TETRIS_PLL_1000,
  69        [SPD1200]       = TETRIS_PLL_1200,
  70        [SPD1350]       = TETRIS_PLL_1350,
  71        [SPD1400]       = TETRIS_PLL_1400,
  72};
  73
  74static struct pll_init_data pa_pll_config =
  75        PASS_PLL_983;
  76
  77struct pll_init_data *get_pll_init_data(int pll)
  78{
  79        int speed;
  80        struct pll_init_data *data;
  81
  82        switch (pll) {
  83        case MAIN_PLL:
  84                speed = get_max_dev_speed(speeds);
  85                data = &core_pll_config[speed];
  86                break;
  87        case TETRIS_PLL:
  88                speed = get_max_arm_speed(speeds);
  89                data = &tetris_pll_config[speed];
  90                break;
  91        case PASS_PLL:
  92                data = &pa_pll_config;
  93                break;
  94        default:
  95                data = NULL;
  96        }
  97
  98        return data;
  99}
 100
 101#ifdef CONFIG_BOARD_EARLY_INIT_F
 102int board_early_init_f(void)
 103{
 104        init_plls();
 105
 106        return 0;
 107}
 108#endif
 109
 110#if defined(CONFIG_MULTI_DTB_FIT)
 111int board_fit_config_name_match(const char *name)
 112{
 113        if (!strcmp(name, "keystone-k2hk-evm"))
 114                return 0;
 115
 116        return -1;
 117}
 118#endif
 119
 120#ifdef CONFIG_SPL_BUILD
 121void spl_init_keystone_plls(void)
 122{
 123        init_plls();
 124}
 125#endif
 126