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11#include <init.h>
12#include <asm/arch/clock.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/imx-regs.h>
15#include <asm/arch/iomux.h>
16#include <asm/arch/mx6-pins.h>
17#include <asm/global_data.h>
18#include <asm/gpio.h>
19#include <asm/mach-imx/iomux-v3.h>
20#include <dm.h>
21#include <env.h>
22#include <mmc.h>
23#include <fsl_esdhc_imx.h>
24#include <asm/arch/crm_regs.h>
25#include <asm/io.h>
26#include <asm/mach-imx/mxc_i2c.h>
27#include <asm/arch/sys_proto.h>
28#include <spl.h>
29#include <linux/delay.h>
30#include <linux/sizes.h>
31#include <common.h>
32#include <i2c.h>
33#include <power/pmic.h>
34#include <power/pfuze3000_pmic.h>
35#include <malloc.h>
36
37DECLARE_GLOBAL_DATA_PTR;
38
39enum {
40 UDOO_NEO_TYPE_BASIC,
41 UDOO_NEO_TYPE_BASIC_KS,
42 UDOO_NEO_TYPE_FULL,
43 UDOO_NEO_TYPE_EXTENDED,
44};
45
46#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
48 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
49
50#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
52 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
53
54#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
56 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
57 PAD_CTL_ODE)
58
59#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
60 PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
64 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
65
66#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
67 PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
68
69#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
70 PAD_CTL_DSE_40ohm)
71
72#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
73 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
74 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
75#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \
76 MUX_MODE_SION)
77
78#define OCRAM_START 0x8f8000
79
80int dram_init(void)
81{
82 gd->ram_size = imx_ddr_size();
83 return 0;
84}
85
86#ifdef CONFIG_SYS_I2C_MXC
87#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
88
89static struct i2c_pads_info i2c_pad_info1 = {
90 .scl = {
91 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
92 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
93 .gp = IMX_GPIO_NR(1, 0),
94 },
95 .sda = {
96 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
97 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
98 .gp = IMX_GPIO_NR(1, 1),
99 },
100};
101#endif
102
103#if CONFIG_IS_ENABLED(POWER_LEGACY)
104int power_init_board(void)
105{
106 struct pmic *p;
107 int ret;
108 unsigned int reg, rev_id;
109
110 ret = power_pfuze3000_init(PFUZE3000_I2C_BUS);
111 if (ret)
112 return ret;
113
114 p = pmic_get("PFUZE3000");
115 ret = pmic_probe(p);
116 if (ret)
117 return ret;
118
119 pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
120 pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
121 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
122
123
124 pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
125 reg |= 0x1;
126 ret = pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
127 if (ret)
128 return ret;
129
130 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc);
131 if (ret)
132 return ret;
133
134 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc);
135 if (ret)
136 return ret;
137
138 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc);
139 if (ret)
140 return ret;
141
142 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc);
143 if (ret)
144 return ret;
145
146
147 pmic_reg_read(p, PFUZE3000_SW1ASTBY, ®);
148 reg &= ~0x3f;
149 reg |= PFUZE3000_SW1AB_SETP(9750);
150 ret = pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
151 if (ret)
152 return ret;
153
154
155 pmic_reg_read(p, PFUZE3000_SW1BSTBY, ®);
156 reg &= ~0x3f;
157 reg |= PFUZE3000_SW1AB_SETP(9750);
158 ret = pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
159 if (ret)
160 return ret;
161
162
163 pmic_reg_read(p, PFUZE3000_SW1ACONF, ®);
164 reg &= ~0xc0;
165 reg |= 0x40;
166 ret = pmic_reg_write(p, PFUZE3000_SW1ACONF, reg);
167 if (ret)
168 return ret;
169
170
171 pmic_reg_read(p, PFUZE3000_SW1BCONF, ®);
172 reg &= ~0xc0;
173 reg |= 0x40;
174 ret = pmic_reg_write(p, PFUZE3000_SW1BCONF, reg);
175 if (ret)
176 return ret;
177
178
179 pmic_reg_read(p, PFUZE3000_SW1AVOLT, ®);
180 reg &= ~0x3f;
181 reg |= PFUZE3000_SW1AB_SETP(13500);
182 ret = pmic_reg_write(p, PFUZE3000_SW1AVOLT, reg);
183 if (ret)
184 return ret;
185
186
187 pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
188 reg &= ~0x3f;
189 reg |= PFUZE3000_SW1AB_SETP(13500);
190 ret = pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
191 if (ret)
192 return ret;
193
194
195 pmic_reg_read(p, PFUZE3000_SW3VOLT, ®);
196 reg &= ~0x0f;
197 reg |= PFUZE3000_SW3_SETP(13500);
198 ret = pmic_reg_write(p, PFUZE3000_SW3VOLT, reg);
199 if (ret)
200 return ret;
201
202
203 pmic_reg_read(p, PFUZE3000_VLDO2CTL, ®);
204 reg &= ~0x0f;
205 reg |= PFUZE3000_VLDO_SETP(15000);
206
207 reg |= 0x10;
208 ret = pmic_reg_write(p, PFUZE3000_VLDO2CTL, reg);
209 if (ret)
210 return ret;
211
212 return 0;
213}
214#endif
215
216static iomux_v3_cfg_t const uart1_pads[] = {
217 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
218 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
219};
220
221static iomux_v3_cfg_t const usdhc2_pads[] = {
222 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
223 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
224 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
225 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
226 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
227 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
228
229 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
230
231 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
232};
233
234static iomux_v3_cfg_t const phy_control_pads[] = {
235
236 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
237 MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
238};
239
240static iomux_v3_cfg_t const wdog_b_pad = {
241 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
242};
243
244static iomux_v3_cfg_t const peri_3v3_pads[] = {
245 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
246};
247
248static void setup_iomux_uart(void)
249{
250 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
251}
252
253static int setup_fec(void)
254{
255 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
256 int reg;
257
258 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
259 ARRAY_SIZE(phy_control_pads));
260
261
262 gpio_request(IMX_GPIO_NR(2, 1), "enet_rst");
263 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0);
264 udelay(10000);
265 gpio_set_value(IMX_GPIO_NR(2, 1), 1);
266 udelay(100);
267
268 reg = readl(&anatop->pll_enet);
269 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
270 writel(reg, &anatop->pll_enet);
271
272 return enable_fec_anatop_clock(0, ENET_25MHZ);
273}
274
275int board_init(void)
276{
277
278 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
279
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286
287 imx_iomux_v3_setup_pad(wdog_b_pad);
288
289
290 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
291 ARRAY_SIZE(peri_3v3_pads));
292
293
294 gpio_request(IMX_GPIO_NR(4, 16), "ncp692");
295 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
296
297#ifdef CONFIG_SYS_I2C_MXC
298 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
299#endif
300
301 setup_fec();
302
303 return 0;
304}
305
306int board_early_init_f(void)
307{
308 setup_iomux_uart();
309
310 return 0;
311}
312
313static struct fsl_esdhc_cfg usdhc_cfg[1] = {
314 {USDHC2_BASE_ADDR},
315};
316
317#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
318#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2)
319
320int board_mmc_getcd(struct mmc *mmc)
321{
322 return !gpio_get_value(USDHC2_CD_GPIO);
323}
324
325int board_mmc_init(struct bd_info *bis)
326{
327 SETUP_IOMUX_PADS(usdhc2_pads);
328 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
329 usdhc_cfg[0].max_bus_width = 4;
330 gpio_request(IMX_GPIO_NR(6, 1), "usdhc2_pwr");
331 gpio_request(IMX_GPIO_NR(6, 2), "usdhc2_cd");
332 gpio_direction_input(USDHC2_CD_GPIO);
333 gpio_direction_output(USDHC2_PWR_GPIO, 1);
334
335 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
336}
337
338static char *board_string(int type)
339{
340 switch (type) {
341 case UDOO_NEO_TYPE_BASIC:
342 return "BASIC";
343 case UDOO_NEO_TYPE_BASIC_KS:
344 return "BASICKS";
345 case UDOO_NEO_TYPE_FULL:
346 return "FULL";
347 case UDOO_NEO_TYPE_EXTENDED:
348 return "EXTENDED";
349 }
350 return "UNDEFINED";
351}
352
353
354int show_board_info(void)
355{
356 int *board_type = (int *)OCRAM_START;
357
358 printf("Board: UDOO Neo %s\n", board_string(*board_type));
359 return 0;
360}
361
362int board_late_init(void)
363{
364 int *board_type = (int *)OCRAM_START;
365
366#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
367 env_set("board_name", board_string(*board_type));
368#endif
369
370 return 0;
371}
372
373#ifdef CONFIG_SPL_BUILD
374
375#include <linux/libfdt.h>
376#include <asm/arch/mx6-ddr.h>
377
378static const iomux_v3_cfg_t board_recognition_pads[] = {
379
380 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
381
382 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
383};
384
385static int get_board_value(void)
386{
387 int r184, r185;
388
389 imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
390 ARRAY_SIZE(board_recognition_pads));
391
392 gpio_request(IMX_GPIO_NR(4, 13), "r184");
393 gpio_request(IMX_GPIO_NR(4, 0), "r185");
394 gpio_direction_input(IMX_GPIO_NR(4, 13));
395 gpio_direction_input(IMX_GPIO_NR(4, 0));
396
397 r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
398 r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
399
400
401
402
403
404
405
406
407
408
409
410 return (r184 << 1) + r185;
411}
412
413static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
414 .dram_dqm0 = 0x00000028,
415 .dram_dqm1 = 0x00000028,
416 .dram_dqm2 = 0x00000028,
417 .dram_dqm3 = 0x00000028,
418 .dram_ras = 0x00000020,
419 .dram_cas = 0x00000020,
420 .dram_odt0 = 0x00000020,
421 .dram_odt1 = 0x00000020,
422 .dram_sdba2 = 0x00000000,
423 .dram_sdcke0 = 0x00003000,
424 .dram_sdcke1 = 0x00003000,
425 .dram_sdclk_0 = 0x00000030,
426 .dram_sdqs0 = 0x00000028,
427 .dram_sdqs1 = 0x00000028,
428 .dram_sdqs2 = 0x00000028,
429 .dram_sdqs3 = 0x00000028,
430 .dram_reset = 0x00000020,
431};
432
433static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
434 .grp_addds = 0x00000020,
435 .grp_ddrmode_ctl = 0x00020000,
436 .grp_ddrpke = 0x00000000,
437 .grp_ddrmode = 0x00020000,
438 .grp_b0ds = 0x00000028,
439 .grp_b1ds = 0x00000028,
440 .grp_ctlds = 0x00000020,
441 .grp_ddr_type = 0x000c0000,
442 .grp_b2ds = 0x00000028,
443 .grp_b3ds = 0x00000028,
444};
445
446static const struct mx6_mmdc_calibration neo_mmcd_calib = {
447 .p0_mpwldectrl0 = 0x000E000B,
448 .p0_mpwldectrl1 = 0x000E0010,
449 .p0_mpdgctrl0 = 0x41600158,
450 .p0_mpdgctrl1 = 0x01500140,
451 .p0_mprddlctl = 0x3A383E3E,
452 .p0_mpwrdlctl = 0x3A383C38,
453};
454
455static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
456 .p0_mpwldectrl0 = 0x001E0022,
457 .p0_mpwldectrl1 = 0x001C0019,
458 .p0_mpdgctrl0 = 0x41540150,
459 .p0_mpdgctrl1 = 0x01440138,
460 .p0_mprddlctl = 0x403E4644,
461 .p0_mpwrdlctl = 0x3C3A4038,
462};
463
464
465static struct mx6_ddr3_cfg neo_mem_ddr = {
466 .mem_speed = 1600,
467 .density = 4,
468 .width = 16,
469 .banks = 8,
470 .rowaddr = 15,
471 .coladdr = 10,
472 .pagesz = 2,
473 .trcd = 1375,
474 .trcmin = 4875,
475 .trasmin = 3500,
476};
477
478
479static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
480 .mem_speed = 1600,
481 .density = 2,
482 .width = 16,
483 .banks = 8,
484 .rowaddr = 14,
485 .coladdr = 10,
486 .pagesz = 2,
487 .trcd = 1375,
488 .trcmin = 4875,
489 .trasmin = 3500,
490};
491
492static void ccgr_init(void)
493{
494 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
495
496 writel(0xFFFFFFFF, &ccm->CCGR0);
497 writel(0xFFFFFFFF, &ccm->CCGR1);
498 writel(0xFFFFFFFF, &ccm->CCGR2);
499 writel(0xFFFFFFFF, &ccm->CCGR3);
500 writel(0xFFFFFFFF, &ccm->CCGR4);
501 writel(0xFFFFFFFF, &ccm->CCGR5);
502 writel(0xFFFFFFFF, &ccm->CCGR6);
503 writel(0xFFFFFFFF, &ccm->CCGR7);
504}
505
506static void spl_dram_init(void)
507{
508 int *board_type = (int *)OCRAM_START;
509
510 struct mx6_ddr_sysinfo sysinfo = {
511 .dsize = 1,
512 .cs_density = 24,
513 .ncs = 1,
514 .cs1_mirror = 0,
515 .rtt_wr = 2,
516 .rtt_nom = 2,
517 .walat = 1,
518 .ralat = 5,
519 .mif3_mode = 3,
520 .bi_on = 1,
521 .sde_to_rst = 0x10,
522 .rst_to_cke = 0x23,
523 };
524
525 *board_type = get_board_value();
526
527 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
528 if (*board_type == UDOO_NEO_TYPE_BASIC ||
529 *board_type == UDOO_NEO_TYPE_BASIC_KS)
530 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
531 &neo_basic_mem_ddr);
532 else
533 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
534}
535
536void board_init_f(ulong dummy)
537{
538 ccgr_init();
539
540
541 arch_cpu_init();
542
543 board_early_init_f();
544
545
546 timer_init();
547
548
549 preloader_console_init();
550
551
552 spl_dram_init();
553
554
555 memset(__bss_start, 0, __bss_end - __bss_start);
556
557
558 board_init_r(NULL, 0);
559}
560
561#endif
562
