LXR uboot/drivers/mmc/rockchip

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
   4 *
   5 * Rockchip SD Host Controller Interface
   6 */
   7
   8#include <common.h>
   9#include <clk.h>
  10#include <dm.h>
  11#include <dm/ofnode.h>
  12#include <dt-structs.h>
  13#include <linux/delay.h>
  14#include <linux/err.h>
  15#include <linux/libfdt.h>
  16#include <linux/iopoll.h>
  17#include <malloc.h>
  18#include <mapmem.h>
  19#include "mmc_private.h"
  20#include <sdhci.h>
  21#include <syscon.h>
  22#include <asm/arch-rockchip/clock.h>
  23#include <asm/arch-rockchip/hardware.h>
  24
  25/* DWCMSHC specific Mode Select value */
  26#define DWCMSHC_CTRL_HS400              0x7
  27/* 400KHz is max freq for card ID etc. Use that as min */
  28#define EMMC_MIN_FREQ   400000
  29#define KHz     (1000)
  30#define MHz     (1000 * KHz)
  31#define SDHCI_TUNING_LOOP_COUNT         40
  32
  33#define PHYCTRL_CALDONE_MASK            0x1
  34#define PHYCTRL_CALDONE_SHIFT           0x6
  35#define PHYCTRL_CALDONE_DONE            0x1
  36#define PHYCTRL_DLLRDY_MASK             0x1
  37#define PHYCTRL_DLLRDY_SHIFT            0x5
  38#define PHYCTRL_DLLRDY_DONE             0x1
  39#define PHYCTRL_FREQSEL_200M            0x0
  40#define PHYCTRL_FREQSEL_50M             0x1
  41#define PHYCTRL_FREQSEL_100M            0x2
  42#define PHYCTRL_FREQSEL_150M            0x3
  43#define PHYCTRL_DLL_LOCK_WO_TMOUT(x)    \
  44        ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
  45        PHYCTRL_DLLRDY_DONE)
  46
  47#define ARASAN_VENDOR_REGISTER          0x78
  48#define ARASAN_VENDOR_ENHANCED_STROBE   BIT(0)
  49
  50/* DWC IP vendor area 1 pointer */
  51#define DWCMSHC_P_VENDOR_AREA1          0xe8
  52#define DWCMSHC_AREA1_MASK              GENMASK(11, 0)
  53/* Offset inside the vendor area 1 */
  54#define DWCMSHC_EMMC_CONTROL            0x2c
  55#define DWCMSHC_CARD_IS_EMMC            BIT(0)
  56#define DWCMSHC_ENHANCED_STROBE         BIT(8)
  57
  58/* Rockchip specific Registers */
  59#define DWCMSHC_EMMC_DLL_CTRL           0x800
  60#define DWCMSHC_EMMC_DLL_CTRL_RESET     BIT(1)
  61#define DWCMSHC_EMMC_DLL_RXCLK          0x804
  62#define DWCMSHC_EMMC_DLL_TXCLK          0x808
  63#define DWCMSHC_EMMC_DLL_STRBIN         0x80c
  64#define DWCMSHC_EMMC_DLL_STATUS0        0x840
  65#define DWCMSHC_EMMC_DLL_STATUS1        0x844
  66#define DWCMSHC_EMMC_DLL_START          BIT(0)
  67#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL   29
  68#define DWCMSHC_EMMC_DLL_START_POINT    16
  69#define DWCMSHC_EMMC_DLL_START_DEFAULT  5
  70#define DWCMSHC_EMMC_DLL_INC_VALUE      2
  71#define DWCMSHC_EMMC_DLL_INC            8
  72#define DWCMSHC_EMMC_DLL_DLYENA         BIT(27)
  73#define DLL_TXCLK_TAPNUM_DEFAULT        0xA
  74
  75#define DLL_STRBIN_TAPNUM_DEFAULT       0x8
  76#define DLL_STRBIN_TAPNUM_FROM_SW       BIT(24)
  77#define DLL_STRBIN_DELAY_NUM_SEL        BIT(26)
  78#define DLL_STRBIN_DELAY_NUM_OFFSET     16
  79#define DLL_STRBIN_DELAY_NUM_DEFAULT    0x16
  80
  81#define DLL_TXCLK_TAPNUM_FROM_SW        BIT(24)
  82#define DWCMSHC_EMMC_DLL_LOCKED         BIT(8)
  83#define DWCMSHC_EMMC_DLL_TIMEOUT        BIT(9)
  84#define DLL_RXCLK_NO_INVERTER           1
  85#define DLL_RXCLK_INVERTER              0
  86#define DWCMSHC_ENHANCED_STROBE         BIT(8)
  87#define DLL_LOCK_WO_TMOUT(x) \
  88        ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
  89        (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
  90#define ROCKCHIP_MAX_CLKS               3
  91
  92struct rockchip_sdhc_plat {
  93        struct mmc_config cfg;
  94        struct mmc mmc;
  95};
  96
  97struct rockchip_emmc_phy {
  98        u32 emmcphy_con[7];
  99        u32 reserved;
 100        u32 emmcphy_status;
 101};
 102
 103struct rockchip_sdhc {
 104        struct sdhci_host host;
 105        struct udevice *dev;
 106        void *base;
 107        struct rockchip_emmc_phy *phy;
 108        struct clk emmc_clk;
 109};
 110
 111struct sdhci_data {
 112        int (*emmc_phy_init)(struct udevice *dev);
 113        int (*get_phy)(struct udevice *dev);
 114
 115        /**
 116         * set_control_reg() - Set SDHCI control registers
 117         *
 118         * This is the set_control_reg() SDHCI operation that should be
 119         * used for the hardware this driver data is associated with.
 120         * Normally, this is used to set up control registers for
 121         * voltage level and UHS speed mode.
 122         *
 123         * @host: SDHCI host structure
 124         */
 125        void (*set_control_reg)(struct sdhci_host *host);
 126
 127        /**
 128         * set_ios_post() - Host specific hook after set_ios() calls
 129         *
 130         * This is the set_ios_post() SDHCI operation that should be
 131         * used for the hardware this driver data is associated with.
 132         * Normally, this is a hook that is called after sdhci_set_ios()
 133         * that does any necessary host-specific configuration.
 134         *
 135         * @host: SDHCI host structure
 136         * Return: 0 if successful, -ve on error
 137         */
 138        int (*set_ios_post)(struct sdhci_host *host);
 139
 140        /**
 141         * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
 142         *
 143         * This is the set_enhanced_strobe() SDHCI operation that should
 144         * be used for the hardware this driver data is associated with.
 145         * Normally, this is used to set any host-specific configuration
 146         * necessary for HS400 ES.
 147         *
 148         * @host: SDHCI host structure
 149         * Return: 0 if successful, -ve on error
 150         */
 151        int (*set_enhanced_strobe)(struct sdhci_host *host);
 152};
 153
 154static int rk3399_emmc_phy_init(struct udevice *dev)
 155{
 156        return 0;
 157}
 158
 159static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
 160{
 161        u32 caldone, dllrdy, freqsel;
 162
 163        writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]);
 164        writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]);
 165        writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]);
 166
 167        /*
 168         * According to the user manual, calpad calibration
 169         * cycle takes more than 2us without the minimal recommended
 170         * value, so we may need a little margin here
 171         */
 172        udelay(3);
 173        writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]);
 174
 175        /*
 176         * According to the user manual, it asks driver to
 177         * wait 5us for calpad busy trimming. But it seems that
 178         * 5us of caldone isn't enough for all cases.
 179         */
 180        udelay(500);
 181        caldone = readl(&phy->emmcphy_status);
 182        caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
 183        if (caldone != PHYCTRL_CALDONE_DONE) {
 184                printf("%s: caldone timeout.\n", __func__);
 185                return;
 186        }
 187
 188        /* Set the frequency of the DLL operation */
 189        if (clock < 75 * MHz)
 190                freqsel = PHYCTRL_FREQSEL_50M;
 191        else if (clock < 125 * MHz)
 192                freqsel = PHYCTRL_FREQSEL_100M;
 193        else if (clock < 175 * MHz)
 194                freqsel = PHYCTRL_FREQSEL_150M;
 195        else
 196                freqsel = PHYCTRL_FREQSEL_200M;
 197
 198        /* Set the frequency of the DLL operation */
 199        writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]);
 200        writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]);
 201
 202        /* REN Enable on STRB Line for HS400 */
 203        writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]);
 204
 205        read_poll_timeout(readl, dllrdy, PHYCTRL_DLL_LOCK_WO_TMOUT(dllrdy), 1,
 206                          5000, &phy->emmcphy_status);
 207}
 208
 209static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy)
 210{
 211        writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]);
 212        writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]);
 213}
 214
 215static int rk3399_emmc_get_phy(struct udevice *dev)
 216{
 217        struct rockchip_sdhc *priv = dev_get_priv(dev);
 218        ofnode phy_node;
 219        void *grf_base;
 220        u32 grf_phy_offset, phandle;
 221
 222        phandle = dev_read_u32_default(dev, "phys", 0);
 223        phy_node = ofnode_get_by_phandle(phandle);
 224        if (!ofnode_valid(phy_node)) {
 225                debug("Not found emmc phy device\n");
 226                return -ENODEV;
 227        }
 228
 229        grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 230        if (IS_ERR_OR_NULL(grf_base)) {
 231                printf("%s Get syscon grf failed", __func__);
 232                return -ENODEV;
 233        }
 234        grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0);
 235
 236        priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset);
 237
 238        return 0;
 239}
 240
 241static int rk3399_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 242{
 243        struct mmc *mmc = host->mmc;
 244        u32 vendor;
 245
 246        vendor = sdhci_readl(host, ARASAN_VENDOR_REGISTER);
 247        if (mmc->selected_mode == MMC_HS_400_ES)
 248                vendor |= ARASAN_VENDOR_ENHANCED_STROBE;
 249        else
 250                vendor &= ~ARASAN_VENDOR_ENHANCED_STROBE;
 251        sdhci_writel(host, vendor, ARASAN_VENDOR_REGISTER);
 252
 253        return 0;
 254}
 255
 256static void rk3399_sdhci_set_control_reg(struct sdhci_host *host)
 257{
 258        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 259        struct mmc *mmc = host->mmc;
 260        uint clock = mmc->tran_speed;
 261        int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
 262
 263        if (cycle_phy)
 264                rk3399_emmc_phy_power_off(priv->phy);
 265
 266        sdhci_set_control_reg(host);
 267
 268        /*
 269         * Reinitializing the device tries to set it to lower-speed modes
 270         * first, which fails if the Enhanced Strobe bit is set, making
 271         * the device impossible to use. Set the correct value here to
 272         * let reinitialization attempts succeed.
 273         */
 274        if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
 275                rk3399_sdhci_set_enhanced_strobe(host);
 276};
 277
 278static int rk3399_sdhci_set_ios_post(struct sdhci_host *host)
 279{
 280        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 281        struct mmc *mmc = host->mmc;
 282        uint clock = mmc->tran_speed;
 283        int cycle_phy = host->clock != clock && clock > EMMC_MIN_FREQ;
 284
 285        if (!clock)
 286                clock = mmc->clock;
 287
 288        if (cycle_phy)
 289                rk3399_emmc_phy_power_on(priv->phy, clock);
 290
 291        return 0;
 292}
 293
 294static int rk3568_emmc_phy_init(struct udevice *dev)
 295{
 296        struct rockchip_sdhc *prv = dev_get_priv(dev);
 297        struct sdhci_host *host = &prv->host;
 298        u32 extra;
 299
 300        extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 301        sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 302
 303        return 0;
 304}
 305
 306static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock)
 307{
 308        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 309        int val, ret;
 310        u32 extra;
 311
 312        if (clock > host->max_clk)
 313                clock = host->max_clk;
 314        if (clock)
 315                clk_set_rate(&priv->emmc_clk, clock);
 316
 317        sdhci_set_clock(host->mmc, clock);
 318
 319        if (clock >= 100 * MHz) {
 320                /* reset DLL */
 321                sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
 322                udelay(1);
 323                sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 324
 325                /* Init DLL settings */
 326                extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
 327                        DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
 328                        DWCMSHC_EMMC_DLL_START;
 329                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
 330
 331                ret = read_poll_timeout(readl, val, DLL_LOCK_WO_TMOUT(val), 1,
 332                                        500,
 333                                        host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0);
 334                if (ret)
 335                        return ret;
 336
 337                extra = DWCMSHC_EMMC_DLL_DLYENA |
 338                        DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 339                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 340
 341                extra = DWCMSHC_EMMC_DLL_DLYENA |
 342                        DLL_TXCLK_TAPNUM_DEFAULT |
 343                        DLL_TXCLK_TAPNUM_FROM_SW;
 344                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
 345
 346                extra = DWCMSHC_EMMC_DLL_DLYENA |
 347                        DLL_STRBIN_TAPNUM_DEFAULT |
 348                        DLL_STRBIN_TAPNUM_FROM_SW;
 349                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 350        } else {
 351                /* reset the clock phase when the frequency is lower than 100MHz */
 352                sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
 353                extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
 354                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
 355                sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
 356                /*
 357                 * Before switching to hs400es mode, the driver will enable
 358                 * enhanced strobe first. PHY needs to configure the parameters
 359                 * of enhanced strobe first.
 360                 */
 361                extra = DWCMSHC_EMMC_DLL_DLYENA |
 362                        DLL_STRBIN_DELAY_NUM_SEL |
 363                        DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
 364                sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
 365        }
 366
 367        return 0;
 368}
 369
 370static int rk3568_emmc_get_phy(struct udevice *dev)
 371{
 372        return 0;
 373}
 374
 375static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 376{
 377        struct mmc *mmc = host->mmc;
 378        u32 vendor;
 379        int reg;
 380
 381        reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
 382              + DWCMSHC_EMMC_CONTROL;
 383
 384        vendor = sdhci_readl(host, reg);
 385        if (mmc->selected_mode == MMC_HS_400_ES)
 386                vendor |= DWCMSHC_ENHANCED_STROBE;
 387        else
 388                vendor &= ~DWCMSHC_ENHANCED_STROBE;
 389        sdhci_writel(host, vendor, reg);
 390
 391        return 0;
 392}
 393
 394static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
 395{
 396        struct mmc *mmc = host->mmc;
 397        uint clock = mmc->tran_speed;
 398        u32 reg, vendor_reg;
 399
 400        if (!clock)
 401                clock = mmc->clock;
 402
 403        rk3568_sdhci_emmc_set_clock(host, clock);
 404
 405        if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES) {
 406                reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 407                reg &= ~SDHCI_CTRL_UHS_MASK;
 408                reg |= DWCMSHC_CTRL_HS400;
 409                sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 410
 411                vendor_reg = (sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK)
 412                             + DWCMSHC_EMMC_CONTROL;
 413                /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
 414                reg = sdhci_readw(host, vendor_reg);
 415                reg |= DWCMSHC_CARD_IS_EMMC;
 416                sdhci_writew(host, reg, vendor_reg);
 417        } else {
 418                sdhci_set_uhs_timing(host);
 419        }
 420
 421        return 0;
 422}
 423
 424static void rockchip_sdhci_set_control_reg(struct sdhci_host *host)
 425{
 426        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 427        struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
 428
 429        if (data->set_control_reg)
 430                data->set_control_reg(host);
 431}
 432
 433static int rockchip_sdhci_set_ios_post(struct sdhci_host *host)
 434{
 435        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 436        struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
 437
 438        if (data->set_ios_post)
 439                return data->set_ios_post(host);
 440
 441        return 0;
 442}
 443
 444static int rockchip_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
 445{
 446        struct sdhci_host *host = dev_get_priv(mmc->dev);
 447        char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
 448        struct mmc_cmd cmd;
 449        u32 ctrl, blk_size;
 450        int ret = 0;
 451
 452        ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 453        ctrl |= SDHCI_CTRL_EXEC_TUNING;
 454        sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 455
 456        sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
 457        sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
 458
 459        blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
 460        if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && host->mmc->bus_width == 8)
 461                blk_size = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
 462        sdhci_writew(host, blk_size, SDHCI_BLOCK_SIZE);
 463        sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
 464
 465        cmd.cmdidx = opcode;
 466        cmd.resp_type = MMC_RSP_R1;
 467        cmd.cmdarg = 0;
 468
 469        do {
 470                if (tuning_loop_counter-- == 0)
 471                        break;
 472
 473                mmc_send_cmd(mmc, &cmd, NULL);
 474
 475                if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
 476                        /*
 477                         * For tuning command, do not do busy loop. As tuning
 478                         * is happening (CLK-DATA latching for setup/hold time
 479                         * requirements), give time to complete
 480                         */
 481                        udelay(1);
 482
 483                ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 484        } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
 485
 486        if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
 487                printf("%s:Tuning failed\n", __func__);
 488                ret = -EIO;
 489        }
 490
 491        if (tuning_loop_counter < 0) {
 492                ctrl &= ~SDHCI_CTRL_TUNED_CLK;
 493                sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
 494        }
 495
 496        /* Enable only interrupts served by the SD controller */
 497        sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE);
 498        /* Mask all sdhci interrupt sources */
 499        sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 500
 501        return ret;
 502}
 503
 504static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
 505{
 506        struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
 507        struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
 508
 509        if (data->set_enhanced_strobe)
 510                return data->set_enhanced_strobe(host);
 511
 512        return -ENOTSUPP;
 513}
 514
 515static struct sdhci_ops rockchip_sdhci_ops = {
 516        .set_ios_post   = rockchip_sdhci_set_ios_post,
 517        .platform_execute_tuning = &rockchip_sdhci_execute_tuning,
 518        .set_control_reg = rockchip_sdhci_set_control_reg,
 519        .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
 520};
 521
 522static int rockchip_sdhci_probe(struct udevice *dev)
 523{
 524        struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev);
 525        struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 526        struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 527        struct rockchip_sdhc *prv = dev_get_priv(dev);
 528        struct mmc_config *cfg = &plat->cfg;
 529        struct sdhci_host *host = &prv->host;
 530        struct clk clk;
 531        int ret;
 532
 533        host->max_clk = cfg->f_max;
 534        ret = clk_get_by_index(dev, 0, &clk);
 535        if (!ret) {
 536                ret = clk_set_rate(&clk, host->max_clk);
 537                if (IS_ERR_VALUE(ret))
 538                        printf("%s clk set rate fail!\n", __func__);
 539        } else {
 540                printf("%s fail to get clk\n", __func__);
 541        }
 542
 543        prv->emmc_clk = clk;
 544        prv->dev = dev;
 545
 546        if (data->get_phy) {
 547                ret = data->get_phy(dev);
 548                if (ret)
 549                        return ret;
 550        }
 551
 552        if (data->emmc_phy_init) {
 553                ret = data->emmc_phy_init(dev);
 554                if (ret)
 555                        return ret;
 556        }
 557
 558        host->ops = &rockchip_sdhci_ops;
 559        host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
 560
 561        host->mmc = &plat->mmc;
 562        host->mmc->priv = &prv->host;
 563        host->mmc->dev = dev;
 564        upriv->mmc = host->mmc;
 565
 566        ret = sdhci_setup_cfg(cfg, host, cfg->f_max, EMMC_MIN_FREQ);
 567        if (ret)
 568                return ret;
 569
 570        return sdhci_probe(dev);
 571}
 572
 573static int rockchip_sdhci_of_to_plat(struct udevice *dev)
 574{
 575        struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 576        struct sdhci_host *host = dev_get_priv(dev);
 577        struct mmc_config *cfg = &plat->cfg;
 578        int ret;
 579
 580        host->name = dev->name;
 581        host->ioaddr = dev_read_addr_ptr(dev);
 582
 583        ret = mmc_of_parse(dev, cfg);
 584        if (ret)
 585                return ret;
 586
 587        return 0;
 588}
 589
 590static int rockchip_sdhci_bind(struct udevice *dev)
 591{
 592        struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
 593
 594        return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 595}
 596
 597static const struct sdhci_data rk3399_data = {
 598        .get_phy = rk3399_emmc_get_phy,
 599        .emmc_phy_init = rk3399_emmc_phy_init,
 600        .set_control_reg = rk3399_sdhci_set_control_reg,
 601        .set_ios_post = rk3399_sdhci_set_ios_post,
 602        .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
 603};
 604
 605static const struct sdhci_data rk3568_data = {
 606        .get_phy = rk3568_emmc_get_phy,
 607        .emmc_phy_init = rk3568_emmc_phy_init,
 608        .set_ios_post = rk3568_sdhci_set_ios_post,
 609        .set_enhanced_strobe = rk3568_sdhci_set_enhanced_strobe,
 610};
 611
 612static const struct udevice_id sdhci_ids[] = {
 613        {
 614                .compatible = "arasan,sdhci-5.1",
 615                .data = (ulong)&rk3399_data,
 616        },
 617        {
 618                .compatible = "rockchip,rk3568-dwcmshc",
 619                .data = (ulong)&rk3568_data,
 620        },
 621        { }
 622};
 623
 624U_BOOT_DRIVER(arasan_sdhci_drv) = {
 625        .name           = "rockchip_sdhci_5_1",
 626        .id             = UCLASS_MMC,
 627        .of_match       = sdhci_ids,
 628        .of_to_plat     = rockchip_sdhci_of_to_plat,
 629        .ops            = &sdhci_ops,
 630        .bind           = rockchip_sdhci_bind,
 631        .probe          = rockchip_sdhci_probe,
 632        .priv_auto      = sizeof(struct rockchip_sdhc),
 633        .plat_auto      = sizeof(struct rockchip_sdhc_plat),
 634};
 635