1/* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2019-2021 Broadcom. 4 */ 5 6#ifndef _BNXT_HSI_H_ 7#define _BNXT_HSI_H_ 8 9/* input (size:128b/16B) */ 10struct input { 11 __le16 req_type; 12 __le16 cmpl_ring; 13 __le16 seq_id; 14 __le16 target_id; 15 __le64 resp_addr; 16}; 17 18/* output (size:64b/8B) */ 19struct output { 20 __le16 error_code; 21 __le16 req_type; 22 __le16 seq_id; 23 __le16 resp_len; 24}; 25 26/* hwrm_short_input (size:128b/16B) */ 27struct hwrm_short_input { 28 __le16 req_type; 29 __le16 signature; 30#define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 31 __le16 unused_0; 32 __le16 size; 33 __le64 req_addr; 34}; 35 36#define HWRM_VER_GET 0x0UL 37#define HWRM_FUNC_RESET 0x11UL 38#define HWRM_FUNC_QCAPS 0x15UL 39#define HWRM_FUNC_QCFG 0x16UL 40#define HWRM_FUNC_CFG 0x17UL 41#define HWRM_FUNC_DRV_UNRGTR 0x1aUL 42#define HWRM_FUNC_DRV_RGTR 0x1dUL 43#define HWRM_PORT_PHY_CFG 0x20UL 44#define HWRM_PORT_MAC_CFG 0x21UL 45#define HWRM_PORT_PHY_QCFG 0x27UL 46#define HWRM_VNIC_ALLOC 0x40UL 47#define HWRM_VNIC_FREE 0x41UL 48#define HWRM_VNIC_CFG 0x42UL 49#define HWRM_RING_ALLOC 0x50UL 50#define HWRM_RING_FREE 0x51UL 51#define HWRM_RING_GRP_ALLOC 0x60UL 52#define HWRM_RING_GRP_FREE 0x61UL 53#define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 54#define HWRM_CFA_L2_FILTER_FREE 0x91UL 55#define HWRM_CFA_L2_SET_RX_MASK 0x93UL 56#define HWRM_STAT_CTX_ALLOC 0xb0UL 57#define HWRM_STAT_CTX_FREE 0xb1UL 58#define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 59#define HWRM_NVM_FLUSH 0xfff0UL 60#define HWRM_NVM_GET_VARIABLE 0xfff1UL 61#define HWRM_NVM_SET_VARIABLE 0xfff2UL 62 63#define HWRM_NA_SIGNATURE ((__le32)(-1)) 64#define HWRM_MAX_REQ_LEN 128 65#define HWRM_VERSION_MAJOR 1 66#define HWRM_VERSION_MINOR 10 67#define HWRM_VERSION_UPDATE 0 68 69/* hwrm_ver_get_input (size:192b/24B) */ 70struct hwrm_ver_get_input { 71 __le16 req_type; 72 __le16 cmpl_ring; 73 __le16 seq_id; 74 __le16 target_id; 75 __le64 resp_addr; 76 u8 hwrm_intf_maj; 77 u8 hwrm_intf_min; 78 u8 hwrm_intf_upd; 79 u8 unused_0[5]; 80}; 81 82/* hwrm_ver_get_output (size:1408b/176B) */ 83struct hwrm_ver_get_output { 84 __le16 error_code; 85 __le16 req_type; 86 __le16 seq_id; 87 __le16 resp_len; 88 u8 hwrm_intf_maj_8b; 89 u8 hwrm_intf_min_8b; 90 u8 hwrm_intf_upd_8b; 91 u8 hwrm_intf_rsvd_8b; 92 u8 hwrm_fw_maj_8b; 93 u8 hwrm_fw_min_8b; 94 u8 hwrm_fw_bld_8b; 95 u8 hwrm_fw_rsvd_8b; 96 u8 mgmt_fw_maj_8b; 97 u8 mgmt_fw_min_8b; 98 u8 mgmt_fw_bld_8b; 99 u8 mgmt_fw_rsvd_8b; 100 u8 netctrl_fw_maj_8b; 101 u8 netctrl_fw_min_8b; 102 u8 netctrl_fw_bld_8b; 103 u8 netctrl_fw_rsvd_8b; 104 __le32 dev_caps_cfg; 105#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 106#define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 107 u8 roce_fw_maj_8b; 108 u8 roce_fw_min_8b; 109 u8 roce_fw_bld_8b; 110 u8 roce_fw_rsvd_8b; 111 char hwrm_fw_name[16]; 112 char mgmt_fw_name[16]; 113 char netctrl_fw_name[16]; 114 u8 reserved2[16]; 115 char roce_fw_name[16]; 116 __le16 chip_num; 117 u8 chip_rev; 118 u8 chip_metal; 119 u8 chip_bond_id; 120 u8 chip_platform_type; 121 __le16 max_req_win_len; 122 __le16 max_resp_len; 123 __le16 def_req_timeout; 124 u8 flags; 125 u8 unused_0[2]; 126 u8 always_1; 127 __le16 hwrm_intf_major; 128 __le16 hwrm_intf_minor; 129 __le16 hwrm_intf_build; 130 __le16 hwrm_intf_patch; 131 __le16 hwrm_fw_major; 132 __le16 hwrm_fw_minor; 133 __le16 hwrm_fw_build; 134 __le16 hwrm_fw_patch; 135 __le16 mgmt_fw_major; 136 __le16 mgmt_fw_minor; 137 __le16 mgmt_fw_build; 138 __le16 mgmt_fw_patch; 139 __le16 netctrl_fw_major; 140 __le16 netctrl_fw_minor; 141 __le16 netctrl_fw_build; 142 __le16 netctrl_fw_patch; 143 __le16 roce_fw_major; 144 __le16 roce_fw_minor; 145 __le16 roce_fw_build; 146 __le16 roce_fw_patch; 147 __le16 max_ext_req_len; 148 u8 unused_1[5]; 149 u8 valid; 150}; 151 152/* hwrm_async_event_cmpl (size:128b/16B) */ 153struct hwrm_async_event_cmpl { 154 __le16 type; 155 __le16 event_id; 156#define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 157 __le32 event_data2; 158 u8 opaque_v; 159 u8 timestamp_lo; 160 __le16 timestamp_hi; 161 __le32 event_data1; 162}; 163 164/* hwrm_func_reset_input (size:192b/24B) */ 165struct hwrm_func_reset_input { 166 __le16 req_type; 167 __le16 cmpl_ring; 168 __le16 seq_id; 169 __le16 target_id; 170 __le64 resp_addr; 171 __le32 enables; 172 __le16 vf_id; 173 u8 func_reset_level; 174#define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 175 u8 unused_0; 176}; 177 178/* hwrm_func_qcaps_input (size:192b/24B) */ 179struct hwrm_func_qcaps_input { 180 __le16 req_type; 181 __le16 cmpl_ring; 182 __le16 seq_id; 183 __le16 target_id; 184 __le64 resp_addr; 185 __le16 fid; 186 u8 unused_0[6]; 187}; 188 189/* hwrm_func_qcaps_output (size:640b/80B) */ 190struct hwrm_func_qcaps_output { 191 __le16 error_code; 192 __le16 req_type; 193 __le16 seq_id; 194 __le16 resp_len; 195 __le16 fid; 196 __le16 port_id; 197 __le32 flags; 198 u8 mac_address[6]; 199 __le16 max_rsscos_ctx; 200 __le16 max_cmpl_rings; 201 __le16 max_tx_rings; 202 __le16 max_rx_rings; 203 __le16 max_l2_ctxs; 204 __le16 max_vnics; 205 __le16 first_vf_id; 206 __le16 max_vfs; 207 __le16 max_stat_ctx; 208 __le32 max_encap_records; 209 __le32 max_decap_records; 210 __le32 max_tx_em_flows; 211 __le32 max_tx_wm_flows; 212 __le32 max_rx_em_flows; 213 __le32 max_rx_wm_flows; 214 __le32 max_mcast_filters; 215 __le32 max_flow_id; 216 __le32 max_hw_ring_grps; 217 __le16 max_sp_tx_rings; 218 u8 unused_0; 219 u8 valid; 220}; 221 222/* hwrm_func_qcfg_input (size:192b/24B) */ 223struct hwrm_func_qcfg_input { 224 __le16 req_type; 225 __le16 cmpl_ring; 226 __le16 seq_id; 227 __le16 target_id; 228 __le64 resp_addr; 229 __le16 fid; 230 u8 unused_0[6]; 231}; 232 233/* hwrm_func_qcfg_output (size:704b/88B) */ 234struct hwrm_func_qcfg_output { 235 __le16 error_code; 236 __le16 req_type; 237 __le16 seq_id; 238 __le16 resp_len; 239 __le16 fid; 240 __le16 port_id; 241 __le16 vlan; 242 __le16 flags; 243#define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 244 u8 mac_address[6]; 245 __le16 pci_id; 246 __le16 alloc_rsscos_ctx; 247 __le16 alloc_cmpl_rings; 248 __le16 alloc_tx_rings; 249 __le16 alloc_rx_rings; 250 __le16 alloc_l2_ctx; 251 __le16 alloc_vnics; 252 __le16 mtu; 253 __le16 mru; 254 __le16 stat_ctx_id; 255 u8 port_partition_type; 256#define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 257 u8 port_pf_cnt; 258 __le16 dflt_vnic_id; 259 __le16 max_mtu_configured; 260 __le32 min_bw; 261 __le32 max_bw; 262 u8 evb_mode; 263 u8 options; 264 __le16 alloc_vfs; 265 __le32 alloc_mcast_filters; 266 __le32 alloc_hw_ring_grps; 267 __le16 alloc_sp_tx_rings; 268 __le16 alloc_stat_ctx; 269 __le16 alloc_msix; 270 __le16 registered_vfs; 271 u8 unused_1[3]; 272 u8 always_1; 273 __le32 reset_addr_poll; 274 u8 unused_2[3]; 275 u8 valid; 276}; 277 278/* hwrm_func_cfg_input (size:704b/88B) */ 279struct hwrm_func_cfg_input { 280 __le16 req_type; 281 __le16 cmpl_ring; 282 __le16 seq_id; 283 __le16 target_id; 284 __le64 resp_addr; 285 __le16 fid; 286 __le16 num_msix; 287 __le32 flags; 288 __le32 enables; 289#define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 290#define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 291#define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 292#define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 293#define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 294#define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 295 __le16 mtu; 296 __le16 mru; 297 __le16 num_rsscos_ctxs; 298 __le16 num_cmpl_rings; 299 __le16 num_tx_rings; 300 __le16 num_rx_rings; 301 __le16 num_l2_ctxs; 302 __le16 num_vnics; 303 __le16 num_stat_ctxs; 304 __le16 num_hw_ring_grps; 305 u8 dflt_mac_addr[6]; 306 __le16 dflt_vlan; 307 __be32 dflt_ip_addr[4]; 308 __le32 min_bw; 309 __le32 max_bw; 310 __le16 async_event_cr; 311 u8 vlan_antispoof_mode; 312 u8 allowed_vlan_pris; 313 u8 evb_mode; 314 u8 options; 315 __le16 num_mcast_filters; 316}; 317 318/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 319struct hwrm_func_drv_rgtr_input { 320 __le16 req_type; 321 __le16 cmpl_ring; 322 __le16 seq_id; 323 __le16 target_id; 324 __le64 resp_addr; 325 __le32 flags; 326 __le32 enables; 327#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 328#define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 329#define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 330 __le16 os_type; 331#define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 332 u8 ver_maj_8b; 333 u8 ver_min_8b; 334 u8 ver_upd_8b; 335 u8 unused_0[3]; 336 __le32 timestamp; 337 u8 unused_1[4]; 338 __le32 vf_req_fwd[8]; 339 __le32 async_event_fwd[8]; 340 __le16 ver_maj; 341 __le16 ver_min; 342 __le16 ver_upd; 343 __le16 ver_patch; 344}; 345 346/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 347struct hwrm_func_drv_unrgtr_input { 348 __le16 req_type; 349 __le16 cmpl_ring; 350 __le16 seq_id; 351 __le16 target_id; 352 __le64 resp_addr; 353 __le32 flags; 354#define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 355 u8 unused_0[4]; 356}; 357 358/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 359struct hwrm_func_resource_qcaps_input { 360 __le16 req_type; 361 __le16 cmpl_ring; 362 __le16 seq_id; 363 __le16 target_id; 364 __le64 resp_addr; 365 __le16 fid; 366 u8 unused_0[6]; 367}; 368 369/* hwrm_func_resource_qcaps_output (size:448b/56B) */ 370struct hwrm_func_resource_qcaps_output { 371 __le16 error_code; 372 __le16 req_type; 373 __le16 seq_id; 374 __le16 resp_len; 375 __le16 max_vfs; 376 __le16 max_msix; 377 __le16 vf_reservation_strategy; 378 __le16 min_rsscos_ctx; 379 __le16 max_rsscos_ctx; 380 __le16 min_cmpl_rings; 381 __le16 max_cmpl_rings; 382 __le16 min_tx_rings; 383 __le16 max_tx_rings; 384 __le16 min_rx_rings; 385 __le16 max_rx_rings; 386 __le16 min_l2_ctxs; 387 __le16 max_l2_ctxs; 388 __le16 min_vnics; 389 __le16 max_vnics; 390 __le16 min_stat_ctx; 391 __le16 max_stat_ctx; 392 __le16 min_hw_ring_grps; 393 __le16 max_hw_ring_grps; 394 __le16 max_tx_scheduler_inputs; 395 __le16 flags; 396 u8 unused_0[5]; 397 u8 valid; 398}; 399 400/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ 401struct hwrm_func_vlan_qcfg_input { 402 __le16 req_type; 403 __le16 cmpl_ring; 404 __le16 seq_id; 405 __le16 target_id; 406 __le64 resp_addr; 407 __le16 fid; 408 u8 unused_0[6]; 409}; 410 411/* hwrm_port_phy_cfg_input (size:448b/56B) */ 412struct hwrm_port_phy_cfg_input { 413 __le16 req_type; 414 __le16 cmpl_ring; 415 __le16 seq_id; 416 __le16 target_id; 417 __le64 resp_addr; 418 __le32 flags; 419#define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 420#define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 421 __le32 enables; 422#define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 423#define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 424#define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 425#define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 426 __le16 port_id; 427 __le16 force_link_speed; 428#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 429#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 430#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 431#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 432#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 433#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 434 u8 auto_mode; 435#define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 436 u8 auto_duplex; 437#define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 438 u8 auto_pause; 439#define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 440#define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 441 u8 unused_0; 442 __le16 auto_link_speed; 443 __le16 auto_link_speed_mask; 444#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 445#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 446#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 447#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 448#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 449#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 450#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 451 u8 wirespeed; 452 u8 lpbk; 453 u8 force_pause; 454 u8 unused_1; 455 __le32 preemphasis; 456 __le16 eee_link_speed_mask; 457 u8 unused_2[2]; 458 __le32 tx_lpi_timer; 459 __le32 unused_3; 460}; 461 462/* hwrm_port_phy_qcfg_input (size:192b/24B) */ 463struct hwrm_port_phy_qcfg_input { 464 __le16 req_type; 465 __le16 cmpl_ring; 466 __le16 seq_id; 467 __le16 target_id; 468 __le64 resp_addr; 469 __le16 port_id; 470 u8 unused_0[6]; 471}; 472 473/* hwrm_port_phy_qcfg_output (size:768b/96B) */ 474struct hwrm_port_phy_qcfg_output { 475 __le16 error_code; 476 __le16 req_type; 477 __le16 seq_id; 478 __le16 resp_len; 479 u8 link; 480#define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 481 u8 unused_0; 482 __le16 link_speed; 483#define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 484#define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 485#define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 486#define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 487#define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 488#define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 489#define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 490#define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 491#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 492#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 493#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 494 u8 duplex_cfg; 495 u8 pause; 496 __le16 support_speeds; 497#define PORT_QCFG_SUPPORT_SPEEDS_100MBHD 0x1UL 498#define PORT_QCFG_SUPPORT_SPEEDS_100MB 0x2UL 499#define PORT_QCFG_SUPPORT_SPEEDS_1GBHD 0x4UL 500#define PORT_QCFG_SUPPORT_SPEEDS_1GB 0x8UL 501#define PORT_QCFG_SUPPORT_SPEEDS_2GB 0x10UL 502#define PORT_QCFG_SUPPORT_SPEEDS_2_5GB 0x20UL 503#define PORT_QCFG_SUPPORT_SPEEDS_10GB 0x40UL 504#define PORT_QCFG_SUPPORT_SPEEDS_20GB 0x80UL 505#define PORT_QCFG_SUPPORT_SPEEDS_25GB 0x100UL 506#define PORT_QCFG_SUPPORT_SPEEDS_50GB 0x400UL 507#define PORT_QCFG_SUPPORT_SPEEDS_100GB 0x800UL 508#define PORT_QCFG_SUPPORT_SPEEDS_200GB 0x4000UL 509 __le16 force_link_speed; 510 u8 auto_mode; 511 u8 auto_pause; 512 __le16 auto_link_speed; 513 __le16 auto_link_speed_mask; 514 u8 wirespeed; 515 u8 lpbk; 516 u8 force_pause; 517 u8 module_status; 518 __le32 preemphasis; 519 u8 phy_maj; 520 u8 phy_min; 521 u8 phy_bld; 522 u8 phy_type; 523 u8 media_type; 524 u8 xcvr_pkg_type; 525 u8 eee_config_phy_addr; 526 u8 parallel_detect; 527 __le16 link_partner_adv_speeds; 528 u8 link_partner_adv_auto_mode; 529 u8 link_partner_adv_pause; 530 __le16 adv_eee_link_speed_mask; 531 __le16 link_partner_adv_eee_link_speed_mask; 532 __le32 xcvr_identifier_type_tx_lpi_timer; 533 __le16 fec_cfg; 534 u8 duplex_state; 535 u8 option_flags; 536 char phy_vendor_name[16]; 537 char phy_vendor_partnumber[16]; 538 u8 unused_2[7]; 539 u8 valid; 540}; 541 542/* hwrm_port_mac_cfg_input (size:320b/40B) */ 543struct hwrm_port_mac_cfg_input { 544 __le16 req_type; 545 __le16 cmpl_ring; 546 __le16 seq_id; 547 __le16 target_id; 548 __le64 resp_addr; 549 __le32 flags; 550 __le32 enables; 551 __le16 port_id; 552 u8 ipg; 553 u8 lpbk; 554#define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 555 u8 vlan_pri2cos_map_pri; 556 u8 reserved1; 557 u8 tunnel_pri2cos_map_pri; 558 u8 dscp2pri_map_pri; 559 __le16 rx_ts_capture_ptp_msg_type; 560 __le16 tx_ts_capture_ptp_msg_type; 561 u8 cos_field_cfg; 562 u8 unused_0[3]; 563}; 564 565/* hwrm_vnic_alloc_input (size:192b/24B) */ 566struct hwrm_vnic_alloc_input { 567 __le16 req_type; 568 __le16 cmpl_ring; 569 __le16 seq_id; 570 __le16 target_id; 571 __le64 resp_addr; 572 __le32 flags; 573#define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 574 u8 unused_0[4]; 575}; 576 577/* hwrm_vnic_alloc_output (size:128b/16B) */ 578struct hwrm_vnic_alloc_output { 579 __le16 error_code; 580 __le16 req_type; 581 __le16 seq_id; 582 __le16 resp_len; 583 __le32 vnic_id; 584 u8 unused_0[3]; 585 u8 valid; 586}; 587 588/* hwrm_vnic_free_input (size:192b/24B) */ 589struct hwrm_vnic_free_input { 590 __le16 req_type; 591 __le16 cmpl_ring; 592 __le16 seq_id; 593 __le16 target_id; 594 __le64 resp_addr; 595 __le32 vnic_id; 596 u8 unused_0[4]; 597}; 598 599/* hwrm_vnic_cfg_input (size:320b/40B) */ 600struct hwrm_vnic_cfg_input { 601 __le16 req_type; 602 __le16 cmpl_ring; 603 __le16 seq_id; 604 __le16 target_id; 605 __le64 resp_addr; 606 __le32 flags; 607 __le32 enables; 608#define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 609#define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 610 __le16 vnic_id; 611 __le16 dflt_ring_grp; 612 __le16 rss_rule; 613 __le16 cos_rule; 614 __le16 lb_rule; 615 __le16 mru; 616 __le16 default_rx_ring_id; 617 __le16 default_cmpl_ring_id; 618}; 619 620/* hwrm_ring_alloc_input (size:704b/88B) */ 621struct hwrm_ring_alloc_input { 622 __le16 req_type; 623 __le16 cmpl_ring; 624 __le16 seq_id; 625 __le16 target_id; 626 __le64 resp_addr; 627 __le32 enables; 628#define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 629 u8 ring_type; 630#define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 631#define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 632#define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 633 u8 unused_0; 634 __le16 flags; 635 __le64 page_tbl_addr; 636 __le32 fbo; 637 u8 page_size; 638 u8 page_tbl_depth; 639 u8 unused_1[2]; 640 __le32 length; 641 __le16 logical_id; 642 __le16 cmpl_ring_id; 643 __le16 queue_id; 644 __le16 rx_buf_size; 645 __le16 rx_ring_id; 646 __le16 nq_ring_id; 647 __le16 ring_arb_cfg; 648 __le16 unused_3; 649 __le32 reserved3; 650 __le32 stat_ctx_id; 651 __le32 reserved4; 652 __le32 max_bw; 653 u8 int_mode; 654#define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 655 u8 unused_4[3]; 656 __le64 cq_handle; 657}; 658 659/* hwrm_ring_alloc_output (size:128b/16B) */ 660struct hwrm_ring_alloc_output { 661 __le16 error_code; 662 __le16 req_type; 663 __le16 seq_id; 664 __le16 resp_len; 665 __le16 ring_id; 666 __le16 logical_ring_id; 667 u8 unused_0[3]; 668 u8 valid; 669}; 670 671/* hwrm_ring_free_input (size:192b/24B) */ 672struct hwrm_ring_free_input { 673 __le16 req_type; 674 __le16 cmpl_ring; 675 __le16 seq_id; 676 __le16 target_id; 677 __le64 resp_addr; 678 u8 ring_type; 679#define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 680#define RING_FREE_REQ_RING_TYPE_TX 0x1UL 681#define RING_FREE_REQ_RING_TYPE_RX 0x2UL 682 u8 unused_0; 683 __le16 ring_id; 684 u8 unused_1[4]; 685}; 686 687/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 688struct hwrm_ring_grp_alloc_input { 689 __le16 req_type; 690 __le16 cmpl_ring; 691 __le16 seq_id; 692 __le16 target_id; 693 __le64 resp_addr; 694 __le16 cr; 695 __le16 rr; 696 __le16 ar; 697 __le16 sc; 698}; 699 700/* hwrm_ring_grp_alloc_output (size:128b/16B) */ 701struct hwrm_ring_grp_alloc_output { 702 __le16 error_code; 703 __le16 req_type; 704 __le16 seq_id; 705 __le16 resp_len; 706 __le32 ring_group_id; 707 u8 unused_0[3]; 708 u8 valid; 709}; 710 711/* hwrm_ring_grp_free_input (size:192b/24B) */ 712struct hwrm_ring_grp_free_input { 713 __le16 req_type; 714 __le16 cmpl_ring; 715 __le16 seq_id; 716 __le16 target_id; 717 __le64 resp_addr; 718 __le32 ring_group_id; 719 u8 unused_0[4]; 720}; 721 722/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 723struct hwrm_cfa_l2_filter_alloc_input { 724 __le16 req_type; 725 __le16 cmpl_ring; 726 __le16 seq_id; 727 __le16 target_id; 728 __le64 resp_addr; 729 __le32 flags; 730#define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 731 __le32 enables; 732#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 733#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 734#define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 735 u8 l2_addr[6]; 736 u8 unused_0[2]; 737 u8 l2_addr_mask[6]; 738 __le16 l2_ovlan; 739 __le16 l2_ovlan_mask; 740 __le16 l2_ivlan; 741 __le16 l2_ivlan_mask; 742 u8 unused_1[2]; 743 u8 t_l2_addr[6]; 744 u8 unused_2[2]; 745 u8 t_l2_addr_mask[6]; 746 __le16 t_l2_ovlan; 747 __le16 t_l2_ovlan_mask; 748 __le16 t_l2_ivlan; 749 __le16 t_l2_ivlan_mask; 750 u8 src_type; 751#define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 752 u8 unused_3; 753 __le32 src_id; 754 u8 tunnel_type; 755 u8 unused_4; 756 __le16 dst_id; 757 __le16 mirror_vnic_id; 758 u8 pri_hint; 759 u8 unused_5; 760 __le32 unused_6; 761 __le64 l2_filter_id_hint; 762}; 763 764/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 765struct hwrm_cfa_l2_filter_alloc_output { 766 __le16 error_code; 767 __le16 req_type; 768 __le16 seq_id; 769 __le16 resp_len; 770 __le64 l2_filter_id; 771 __le32 flow_id; 772 u8 unused_0[3]; 773 u8 valid; 774}; 775 776/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 777struct hwrm_cfa_l2_filter_free_input { 778 __le16 req_type; 779 __le16 cmpl_ring; 780 __le16 seq_id; 781 __le16 target_id; 782 __le64 resp_addr; 783 __le64 l2_filter_id; 784}; 785 786/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 787struct hwrm_cfa_l2_set_rx_mask_input { 788 __le16 req_type; 789 __le16 cmpl_ring; 790 __le16 seq_id; 791 __le16 target_id; 792 __le64 resp_addr; 793 __le32 vnic_id; 794 __le32 mask; 795#define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 796#define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 797#define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 798#define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 799 __le64 mc_tbl_addr; 800 __le32 num_mc_entries; 801 u8 unused_0[4]; 802 __le64 vlan_tag_tbl_addr; 803 __le32 num_vlan_tags; 804 u8 unused_1[4]; 805}; 806 807/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 808struct hwrm_stat_ctx_alloc_input { 809 __le16 req_type; 810 __le16 cmpl_ring; 811 __le16 seq_id; 812 __le16 target_id; 813 __le64 resp_addr; 814 __le64 stats_dma_addr; 815 __le32 update_period_ms; 816 u8 stat_ctx_flags; 817 u8 unused_0[3]; 818}; 819 820/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 821struct hwrm_stat_ctx_alloc_output { 822 __le16 error_code; 823 __le16 req_type; 824 __le16 seq_id; 825 __le16 resp_len; 826 __le32 stat_ctx_id; 827 u8 unused_0[3]; 828 u8 valid; 829}; 830 831/* hwrm_stat_ctx_free_input (size:192b/24B) */ 832struct hwrm_stat_ctx_free_input { 833 __le16 req_type; 834 __le16 cmpl_ring; 835 __le16 seq_id; 836 __le16 target_id; 837 __le64 resp_addr; 838 __le32 stat_ctx_id; 839 u8 unused_0[4]; 840}; 841 842/* hwrm_nvm_flush_input (size:128b/16B) */ 843struct hwrm_nvm_flush_input { 844 __le16 req_type; 845 __le16 cmpl_ring; 846 __le16 seq_id; 847 __le16 target_id; 848 __le64 resp_addr; 849}; 850 851/* hwrm_nvm_get_variable_input (size:320b/40B) */ 852struct hwrm_nvm_get_variable_input { 853 __le16 req_type; 854 __le16 cmpl_ring; 855 __le16 seq_id; 856 __le16 target_id; 857 __le64 resp_addr; 858 __le64 dest_data_addr; 859 __le16 data_len; 860 __le16 option_num; 861 __le16 dimensions; 862 __le16 index_0; 863 __le16 index_1; 864 __le16 index_2; 865 __le16 index_3; 866 u8 flags; 867 u8 unused_0; 868}; 869 870/* hwrm_nvm_set_variable_input (size:320b/40B) */ 871struct hwrm_nvm_set_variable_input { 872 __le16 req_type; 873 __le16 cmpl_ring; 874 __le16 seq_id; 875 __le16 target_id; 876 __le64 resp_addr; 877 __le64 src_data_addr; 878 __le16 data_len; 879 __le16 option_num; 880 __le16 dimensions; 881 __le16 index_0; 882 __le16 index_1; 883 __le16 index_2; 884 __le16 index_3; 885 u8 flags; 886 u8 unused_0; 887}; 888 889#endif /* _BNXT_HSI_H_ */ 890