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7#include <common.h>
8#include <dm.h>
9#include <dm/device-internal.h>
10#include <dm/lists.h>
11#include <dm/pinctrl.h>
12#include <asm/io.h>
13#include <asm-generic/gpio.h>
14#include <linux/bitops.h>
15
16#include "pinctrl-mtk-common.h"
17
18#if CONFIG_IS_ENABLED(PINCONF)
19
20
21
22
23
24
25
26
27
28
29struct mtk_drive_desc {
30 u8 min;
31 u8 max;
32 u8 step;
33 u8 scal;
34};
35
36
37static const struct mtk_drive_desc mtk_drive[] = {
38 [DRV_GRP0] = { 4, 16, 4, 1 },
39 [DRV_GRP1] = { 4, 16, 4, 2 },
40 [DRV_GRP2] = { 2, 8, 2, 1 },
41 [DRV_GRP3] = { 2, 8, 2, 2 },
42 [DRV_GRP4] = { 2, 16, 2, 1 },
43};
44#endif
45
46static const char *mtk_pinctrl_dummy_name = "_dummy";
47
48static void mtk_w32(struct udevice *dev, u8 i, u32 reg, u32 val)
49{
50 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
51
52 __raw_writel(val, priv->base[i] + reg);
53}
54
55static u32 mtk_r32(struct udevice *dev, u8 i, u32 reg)
56{
57 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
58
59 return __raw_readl(priv->base[i] + reg);
60}
61
62static inline int get_count_order(unsigned int count)
63{
64 int order;
65
66 order = fls(count) - 1;
67 if (count & (count - 1))
68 order++;
69 return order;
70}
71
72void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
73{
74 return mtk_i_rmw(dev, 0, reg, mask, set);
75}
76
77void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set)
78{
79 u32 val;
80
81 val = mtk_r32(dev, i, reg);
82 val &= ~mask;
83 val |= set;
84 mtk_w32(dev, i, reg, val);
85}
86
87static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
88 const struct mtk_pin_reg_calc *rc,
89 struct mtk_pin_field *pfd)
90{
91 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
92 const struct mtk_pin_field_calc *c, *e;
93 u32 bits;
94 u32 base_calc = priv->soc->base_calc;
95
96 c = rc->range;
97 e = c + rc->nranges;
98
99 while (c < e) {
100 if (pin >= c->s_pin && pin <= c->e_pin)
101 break;
102 c++;
103 }
104
105 if (c >= e)
106 return -EINVAL;
107
108
109
110
111
112 bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
113
114
115
116
117 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
118 pfd->bitpos = bits % c->sz_reg;
119 pfd->mask = (1 << c->x_bits) - 1;
120
121 if (base_calc)
122 pfd->index = c->i_base;
123 else
124 pfd->index = 0;
125
126
127
128
129
130 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
131
132 return 0;
133}
134
135static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
136 int field, struct mtk_pin_field *pfd)
137{
138 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
139 const struct mtk_pin_reg_calc *rc;
140
141 if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
142 return -EINVAL;
143
144 if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
145 rc = &priv->soc->reg_cal[field];
146 else
147 return -EINVAL;
148
149 return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
150}
151
152static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
153{
154 *l = 32 - pf->bitpos;
155 *h = get_count_order(pf->mask) - *l;
156}
157
158static void mtk_hw_write_cross_field(struct udevice *dev,
159 struct mtk_pin_field *pf, int value)
160{
161 int nbits_l, nbits_h;
162
163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
164
165 mtk_i_rmw(dev, pf->index, pf->offset, pf->mask << pf->bitpos,
166 (value & pf->mask) << pf->bitpos);
167
168 mtk_i_rmw(dev, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
169 (value & pf->mask) >> nbits_l);
170}
171
172static void mtk_hw_read_cross_field(struct udevice *dev,
173 struct mtk_pin_field *pf, int *value)
174{
175 int nbits_l, nbits_h, h, l;
176
177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
178
179 l = (mtk_r32(dev, pf->index, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
180 h = (mtk_r32(dev, pf->index, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
181
182 *value = (h << nbits_l) | l;
183}
184
185static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
186 int value)
187{
188 struct mtk_pin_field pf;
189 int err;
190
191 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
192 if (err)
193 return err;
194
195 if (!pf.next)
196 mtk_i_rmw(dev, pf.index, pf.offset, pf.mask << pf.bitpos,
197 (value & pf.mask) << pf.bitpos);
198 else
199 mtk_hw_write_cross_field(dev, &pf, value);
200
201 return 0;
202}
203
204static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
205 int *value)
206{
207 struct mtk_pin_field pf;
208 int err;
209
210 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
211 if (err)
212 return err;
213
214 if (!pf.next)
215 *value = (mtk_r32(dev, pf.index, pf.offset) >> pf.bitpos) & pf.mask;
216 else
217 mtk_hw_read_cross_field(dev, &pf, value);
218
219 return 0;
220}
221
222#if CONFIG_IS_ENABLED(PINCONF)
223static int mtk_get_pin_io_type(struct udevice *dev, int pin,
224 struct mtk_io_type_desc *io_type)
225{
226 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
227 u8 io_n = priv->soc->pins[pin].io_n;
228
229 if (io_n >= priv->soc->ntype)
230 return -EINVAL;
231
232 io_type->name = priv->soc->io_type[io_n].name;
233 io_type->bias_set = priv->soc->io_type[io_n].bias_set;
234 io_type->drive_set = priv->soc->io_type[io_n].drive_set;
235 io_type->input_enable = priv->soc->io_type[io_n].input_enable;
236
237 return 0;
238}
239#endif
240
241static int mtk_get_groups_count(struct udevice *dev)
242{
243 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
244
245 return priv->soc->ngrps;
246}
247
248static const char *mtk_get_pin_name(struct udevice *dev,
249 unsigned int selector)
250{
251 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
252
253 if (!priv->soc->pins[selector].name)
254 return mtk_pinctrl_dummy_name;
255
256 return priv->soc->pins[selector].name;
257}
258
259static int mtk_get_pins_count(struct udevice *dev)
260{
261 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
262
263 return priv->soc->npins;
264}
265
266static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector,
267 char *buf, int size)
268{
269 int val, err;
270 err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val);
271 if (err)
272 return err;
273
274 snprintf(buf, size, "Aux Func.%d", val);
275 return 0;
276}
277
278static const char *mtk_get_group_name(struct udevice *dev,
279 unsigned int selector)
280{
281 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
282
283 if (!priv->soc->grps[selector].name)
284 return mtk_pinctrl_dummy_name;
285
286 return priv->soc->grps[selector].name;
287}
288
289static int mtk_get_functions_count(struct udevice *dev)
290{
291 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
292
293 return priv->soc->nfuncs;
294}
295
296static const char *mtk_get_function_name(struct udevice *dev,
297 unsigned int selector)
298{
299 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
300
301 if (!priv->soc->funcs[selector].name)
302 return mtk_pinctrl_dummy_name;
303
304 return priv->soc->funcs[selector].name;
305}
306
307static int mtk_pinmux_group_set(struct udevice *dev,
308 unsigned int group_selector,
309 unsigned int func_selector)
310{
311 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
312 const struct mtk_group_desc *grp =
313 &priv->soc->grps[group_selector];
314 int i;
315
316 for (i = 0; i < grp->num_pins; i++) {
317 int *pin_modes = grp->data;
318
319 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
320 pin_modes[i]);
321 }
322
323 return 0;
324}
325
326#if CONFIG_IS_ENABLED(PINCONF)
327static const struct pinconf_param mtk_conf_params[] = {
328 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
329 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
330 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
331 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
332 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
333 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
334 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
335 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
336 { "output-high", PIN_CONFIG_OUTPUT, 1, },
337 { "output-low", PIN_CONFIG_OUTPUT, 0, },
338 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
339};
340
341int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
342 bool pullup, u32 val)
343{
344 return mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val);
345}
346
347int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
348 bool pullup, u32 val)
349{
350 int err;
351
352
353 err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
354 val);
355 if (err)
356 return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
357 pullup, val);
358
359 return err;
360}
361
362int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable,
363 bool pullup, u32 val)
364{
365 int err;
366
367 if (disable) {
368 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
369 if (err)
370 return err;
371 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
372 if (err)
373 return err;
374 } else {
375 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
376 if (err)
377 return err;
378 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup);
379 if (err)
380 return err;
381 }
382
383 return 0;
384}
385
386int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
387 bool disable, bool pullup, u32 val)
388{
389 int err;
390
391 if (disable) {
392 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
393 if (err)
394 return err;
395 } else {
396 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1);
397 if (err)
398 return err;
399 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
400 pullup);
401 if (err)
402 return err;
403 }
404
405 return 0;
406}
407
408int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
409 bool pullup, u32 val)
410{
411 int err, r0, r1;
412
413 r0 = !!(val & 1);
414 r1 = !!(val & 2);
415
416 if (disable) {
417 pullup = 0;
418 r0 = 0;
419 r1 = 0;
420 }
421
422
423 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
424 if (err)
425 return err;
426
427
428 mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
429 mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
430
431 return 0;
432}
433
434int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val)
435{
436 int err;
437 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
438 struct mtk_io_type_desc io_type;
439 int rev = priv->soc->rev;
440 bool disable, pullup;
441
442 disable = (arg == PIN_CONFIG_BIAS_DISABLE);
443 pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
444
445 if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
446 if (io_type.bias_set)
447 err = io_type.bias_set(dev, pin, disable, pullup,
448 val);
449 else
450 err = -EINVAL;
451
452 } else if (rev == MTK_PINCTRL_V0) {
453 err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val);
454 } else {
455 err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val);
456 }
457
458 return err;
459}
460
461int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
462{
463 int err;
464
465 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
466 if (err)
467 return err;
468 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
469 if (err)
470 return err;
471
472 return 0;
473}
474
475int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg)
476{
477 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
478 struct mtk_io_type_desc io_type;
479
480 int rev = priv->soc->rev;
481
482 if (!mtk_get_pin_io_type(dev, pin, &io_type))
483 if (io_type.input_enable)
484 return io_type.input_enable(dev, pin, arg);
485 if (rev == MTK_PINCTRL_V1)
486 return mtk_pinconf_input_enable_v1(dev, pin, arg);
487
488 return 0;
489}
490
491int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
492{
493 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
494 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
495 const struct mtk_drive_desc *tb;
496 int err = -ENOTSUPP;
497
498 tb = &mtk_drive[desc->drv_n];
499
500
501
502
503
504 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
505 arg = (arg / tb->step - 1) * tb->scal;
506 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4,
507 arg & 0x1);
508 if (err)
509 return err;
510 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8,
511 (arg & 0x2) >> 1);
512 if (err)
513 return err;
514 }
515
516 return 0;
517}
518
519int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
520{
521 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
522 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
523 const struct mtk_drive_desc *tb;
524 int err = -ENOTSUPP;
525
526 tb = &mtk_drive[desc->drv_n];
527 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
528 arg = (arg / tb->step - 1) * tb->scal;
529 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
530 if (err)
531 return err;
532 }
533
534 return 0;
535}
536
537int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
538{
539 int err;
540 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
541 struct mtk_io_type_desc io_type;
542 int rev = priv->soc->rev;
543
544 if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
545 if (io_type.drive_set)
546 err = io_type.drive_set(dev, pin, arg);
547 else
548 err = -EINVAL;
549 } else if (rev == MTK_PINCTRL_V0) {
550 err = mtk_pinconf_drive_set_v0(dev, pin, arg);
551 } else {
552 err = mtk_pinconf_drive_set_v1(dev, pin, arg);
553 }
554
555 return err;
556}
557
558static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
559 unsigned int param, unsigned int arg)
560{
561 int err = 0;
562
563 switch (param) {
564 case PIN_CONFIG_BIAS_DISABLE:
565 case PIN_CONFIG_BIAS_PULL_UP:
566 case PIN_CONFIG_BIAS_PULL_DOWN:
567 err = mtk_pinconf_bias_set(dev, pin, param, arg);
568 if (err)
569 goto err;
570 break;
571 case PIN_CONFIG_OUTPUT_ENABLE:
572 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
573 if (err)
574 goto err;
575 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
576 if (err)
577 goto err;
578 break;
579 case PIN_CONFIG_INPUT_ENABLE:
580 err = mtk_pinconf_input_enable(dev, pin, param);
581 if (err)
582 goto err;
583 break;
584 case PIN_CONFIG_OUTPUT:
585 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
586 if (err)
587 goto err;
588
589 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
590 if (err)
591 goto err;
592 break;
593 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
594
595
596
597 arg = arg ? 2 : 1;
598 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
599 arg & 1);
600 if (err)
601 goto err;
602
603 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
604 !!(arg & 2));
605 if (err)
606 goto err;
607 break;
608 case PIN_CONFIG_DRIVE_STRENGTH:
609 err = mtk_pinconf_drive_set(dev, pin, arg);
610 if (err)
611 goto err;
612 break;
613
614 default:
615 err = -ENOTSUPP;
616 }
617
618err:
619
620 return err;
621}
622
623static int mtk_pinconf_group_set(struct udevice *dev,
624 unsigned int group_selector,
625 unsigned int param, unsigned int arg)
626{
627 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
628 const struct mtk_group_desc *grp =
629 &priv->soc->grps[group_selector];
630 int i, ret;
631
632 for (i = 0; i < grp->num_pins; i++) {
633 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
634 if (ret)
635 return ret;
636 }
637
638 return 0;
639}
640#endif
641
642const struct pinctrl_ops mtk_pinctrl_ops = {
643 .get_pins_count = mtk_get_pins_count,
644 .get_pin_name = mtk_get_pin_name,
645 .get_pin_muxing = mtk_get_pin_muxing,
646 .get_groups_count = mtk_get_groups_count,
647 .get_group_name = mtk_get_group_name,
648 .get_functions_count = mtk_get_functions_count,
649 .get_function_name = mtk_get_function_name,
650 .pinmux_group_set = mtk_pinmux_group_set,
651#if CONFIG_IS_ENABLED(PINCONF)
652 .pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
653 .pinconf_params = mtk_conf_params,
654 .pinconf_set = mtk_pinconf_set,
655 .pinconf_group_set = mtk_pinconf_group_set,
656#endif
657 .set_state = pinctrl_generic_set_state,
658};
659
660#if CONFIG_IS_ENABLED(DM_GPIO) || \
661 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
662static int mtk_gpio_get(struct udevice *dev, unsigned int off)
663{
664 int val, err;
665
666 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
667 if (err)
668 return err;
669
670 return !!val;
671}
672
673static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
674{
675 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
676}
677
678static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
679{
680 int val, err;
681
682 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
683 if (err)
684 return err;
685
686 return val ? GPIOF_OUTPUT : GPIOF_INPUT;
687}
688
689static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
690{
691 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
692}
693
694static int mtk_gpio_direction_output(struct udevice *dev,
695 unsigned int off, int val)
696{
697 mtk_gpio_set(dev, off, val);
698
699
700 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
701}
702
703static int mtk_gpio_request(struct udevice *dev, unsigned int off,
704 const char *label)
705{
706 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
707
708 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE,
709 priv->soc->gpio_mode);
710}
711
712static int mtk_gpio_probe(struct udevice *dev)
713{
714 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
715 struct gpio_dev_priv *uc_priv;
716
717 uc_priv = dev_get_uclass_priv(dev);
718 uc_priv->bank_name = priv->soc->name;
719 uc_priv->gpio_count = priv->soc->npins;
720
721 return 0;
722}
723
724static const struct dm_gpio_ops mtk_gpio_ops = {
725 .request = mtk_gpio_request,
726 .set_value = mtk_gpio_set,
727 .get_value = mtk_gpio_get,
728 .get_function = mtk_gpio_get_direction,
729 .direction_input = mtk_gpio_direction_input,
730 .direction_output = mtk_gpio_direction_output,
731};
732
733static struct driver mtk_gpio_driver = {
734 .name = "mediatek_gpio",
735 .id = UCLASS_GPIO,
736 .probe = mtk_gpio_probe,
737 .ops = &mtk_gpio_ops,
738};
739
740static int mtk_gpiochip_register(struct udevice *parent)
741{
742 struct uclass_driver *drv;
743 struct udevice *dev;
744 int ret;
745 ofnode node;
746
747 drv = lists_uclass_lookup(UCLASS_GPIO);
748 if (!drv)
749 return -ENOENT;
750
751 ret = -ENOENT;
752 dev_for_each_subnode(node, parent)
753 if (ofnode_read_bool(node, "gpio-controller")) {
754 ret = 0;
755 break;
756 }
757
758 if (ret)
759 return ret;
760
761 ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
762 "mediatek_gpio", 0, node,
763 &dev);
764 if (ret)
765 return ret;
766
767 return 0;
768}
769#endif
770
771int mtk_pinctrl_common_probe(struct udevice *dev,
772 struct mtk_pinctrl_soc *soc)
773{
774 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
775 int ret = 0;
776 u32 i = 0;
777 fdt_addr_t addr;
778 u32 base_calc = soc->base_calc;
779 u32 nbase_names = soc->nbase_names;
780
781 priv->soc = soc;
782
783 if (!base_calc)
784 nbase_names = 1;
785
786 for (i = 0; i < nbase_names; i++) {
787 addr = devfdt_get_addr_index(dev, i);
788 if (addr == FDT_ADDR_T_NONE)
789 return -EINVAL;
790 priv->base[i] = (void __iomem *)addr;
791 }
792
793#if CONFIG_IS_ENABLED(DM_GPIO) || \
794 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
795 ret = mtk_gpiochip_register(dev);
796#endif
797
798 return ret;
799}
800
