LXR uboot/drivers/pinctrl/nxp/pinctrl-imx.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
   4 */
   5
   6#include <common.h>
   7#include <malloc.h>
   8#include <mapmem.h>
   9#include <asm/global_data.h>
  10#include <dm/device_compat.h>
  11#include <dm/devres.h>
  12#include <linux/bitops.h>
  13#include <linux/io.h>
  14#include <linux/err.h>
  15#include <dm.h>
  16#include <dm/pinctrl.h>
  17
  18#include "pinctrl-imx.h"
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  23{
  24        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
  25        struct imx_pinctrl_soc_info *info = priv->info;
  26        int node = dev_of_offset(config);
  27        const struct fdt_property *prop;
  28        u32 *pin_data;
  29        int npins, size, pin_size;
  30        int mux_reg, conf_reg, input_reg;
  31        u32 input_val, mux_mode, config_val;
  32        u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
  33        int i, j = 0;
  34
  35        dev_dbg(dev, "%s: %s\n", __func__, config->name);
  36
  37        if (info->flags & IMX8_USE_SCU)
  38                pin_size = SHARE_IMX8_PIN_SIZE;
  39        else if (info->flags & SHARE_MUX_CONF_REG)
  40                pin_size = SHARE_FSL_PIN_SIZE;
  41        else
  42                pin_size = FSL_PIN_SIZE;
  43
  44        prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
  45        if (!prop) {
  46                dev_err(dev, "No fsl,pins property in node %s\n", config->name);
  47                return -EINVAL;
  48        }
  49
  50        if (!size || size % pin_size) {
  51                dev_err(dev, "Invalid fsl,pins property in node %s\n",
  52                        config->name);
  53                return -EINVAL;
  54        }
  55
  56        pin_data = devm_kzalloc(dev, size, 0);
  57        if (!pin_data)
  58                return -ENOMEM;
  59
  60        if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
  61                                 pin_data, size >> 2)) {
  62                dev_err(dev, "Error reading pin data.\n");
  63                devm_kfree(dev, pin_data);
  64                return -EINVAL;
  65        }
  66
  67        npins = size / pin_size;
  68
  69        if (info->flags & IMX8_USE_SCU) {
  70                imx_pinctrl_scu_conf_pins(info, pin_data, npins);
  71        } else {
  72                /*
  73                 * Refer to linux documentation for details:
  74                 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
  75                 */
  76                for (i = 0; i < npins; i++) {
  77                        mux_reg = pin_data[j++];
  78
  79                        if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  80                                mux_reg = -1;
  81
  82                        if (info->flags & SHARE_MUX_CONF_REG) {
  83                                conf_reg = mux_reg;
  84                        } else {
  85                                conf_reg = pin_data[j++];
  86                                if (!(info->flags & ZERO_OFFSET_VALID) &&
  87                                    !conf_reg)
  88                                        conf_reg = -1;
  89                        }
  90
  91                        if ((mux_reg == -1) || (conf_reg == -1)) {
  92                                dev_err(dev, "Error mux_reg or conf_reg\n");
  93                                devm_kfree(dev, pin_data);
  94                                return -EINVAL;
  95                        }
  96
  97                        input_reg = pin_data[j++];
  98                        mux_mode = pin_data[j++];
  99                        input_val = pin_data[j++];
 100                        config_val = pin_data[j++];
 101
 102                        dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
 103                                "input_reg 0x%x, mux_mode 0x%x, "
 104                                "input_val 0x%x, config_val 0x%x\n",
 105                                mux_reg, conf_reg, input_reg, mux_mode,
 106                                input_val, config_val);
 107
 108                        if (config_val & IMX_PAD_SION)
 109                                mux_mode |= IOMUXC_CONFIG_SION;
 110
 111                        config_val &= ~IMX_PAD_SION;
 112
 113                        /* Set Mux */
 114                        if (info->flags & SHARE_MUX_CONF_REG) {
 115                                clrsetbits_le32(info->base + mux_reg,
 116                                                info->mux_mask,
 117                                                mux_mode << mux_shift);
 118                        } else {
 119                                writel(mux_mode, info->base + mux_reg);
 120                        }
 121
 122                        dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
 123                                mux_reg, mux_mode);
 124
 125                        /*
 126                         * Set select input
 127                         *
 128                         * If the select input value begins with 0xff,
 129                         * it's a quirky select input and the value should
 130                         * be interpreted as below.
 131                         *     31     23      15      7        0
 132                         *     | 0xff | shift | width | select |
 133                         * It's used to work around the problem that the
 134                         * select input for some pin is not implemented in
 135                         * the select input register but in some general
 136                         * purpose register. We encode the select input
 137                         * value, width and shift of the bit field into
 138                         * input_val cell of pin function ID in device tree,
 139                         * and then decode them here for setting up the select
 140                         * input bits in general purpose register.
 141                         */
 142
 143                        if (input_val >> 24 == 0xff) {
 144                                u32 val = input_val;
 145                                u8 select = val & 0xff;
 146                                u8 width = (val >> 8) & 0xff;
 147                                u8 shift = (val >> 16) & 0xff;
 148                                u32 mask = ((1 << width) - 1) << shift;
 149                                /*
 150                                 * The input_reg[i] here is actually some
 151                                 * IOMUXC general purpose register, not
 152                                 * regular select input register.
 153                                 */
 154                                val = readl(info->base + input_reg);
 155                                val &= ~mask;
 156                                val |= select << shift;
 157                                writel(val, info->base + input_reg);
 158                        } else if (input_reg) {
 159                                /*
 160                                 * Regular select input register can never be
 161                                 * at offset 0, and we only print register
 162                                 * value for regular case.
 163                                 */
 164                                if (info->input_sel_base)
 165                                        writel(input_val,
 166                                               info->input_sel_base +
 167                                               input_reg);
 168                                else
 169                                        writel(input_val,
 170                                               info->base + input_reg);
 171
 172                                dev_dbg(dev, "select_input: offset 0x%x val "
 173                                        "0x%x\n", input_reg, input_val);
 174                        }
 175
 176                        /* Set config */
 177                        if (!(config_val & IMX_NO_PAD_CTL)) {
 178                                if (info->flags & SHARE_MUX_CONF_REG) {
 179                                        clrsetbits_le32(info->base + conf_reg,
 180                                                        ~info->mux_mask,
 181                                                        config_val);
 182                                } else {
 183                                        writel(config_val,
 184                                               info->base + conf_reg);
 185                                }
 186
 187                                dev_dbg(dev, "write config: offset 0x%x val "
 188                                        "0x%x\n", conf_reg, config_val);
 189                        }
 190                }
 191        }
 192
 193        devm_kfree(dev, pin_data);
 194
 195        return 0;
 196}
 197
 198const struct pinctrl_ops imx_pinctrl_ops  = {
 199        .set_state = imx_pinctrl_set_state,
 200};
 201
 202int imx_pinctrl_probe(struct udevice *dev,
 203                      struct imx_pinctrl_soc_info *info)
 204{
 205        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 206        int node = dev_of_offset(dev), ret;
 207        struct fdtdec_phandle_args arg;
 208        fdt_addr_t addr;
 209        fdt_size_t size;
 210
 211        if (!info) {
 212                dev_err(dev, "wrong pinctrl info\n");
 213                return -EINVAL;
 214        }
 215
 216        priv->dev = dev;
 217        priv->info = info;
 218
 219        if (info->flags & IMX8_USE_SCU)
 220                return 0;
 221
 222        addr = devfdt_get_addr_size_index(dev, 0, &size);
 223        if (addr == FDT_ADDR_T_NONE)
 224                return -EINVAL;
 225
 226        info->base = map_sysmem(addr, size);
 227        if (!info->base)
 228                return -ENOMEM;
 229        priv->info = info;
 230
 231        info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
 232        /*
 233         * Refer to linux documentation for details:
 234         * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
 235         */
 236        if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
 237                ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
 238                                                     node, "fsl,input-sel",
 239                                                     NULL, 0, 0, &arg);
 240                if (ret) {
 241                        dev_err(dev, "iomuxc fsl,input-sel property not found\n");
 242                        return -EINVAL;
 243                }
 244
 245                addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
 246                                            &size);
 247                if (addr == FDT_ADDR_T_NONE)
 248                        return -EINVAL;
 249
 250                info->input_sel_base = map_sysmem(addr, size);
 251                if (!info->input_sel_base)
 252                        return -ENOMEM;
 253        }
 254
 255        dev_dbg(dev, "initialized IMX pinctrl driver\n");
 256
 257        return 0;
 258}
 259
 260int imx_pinctrl_remove(struct udevice *dev)
 261{
 262        struct imx_pinctrl_priv *priv = dev_get_priv(dev);
 263        struct imx_pinctrl_soc_info *info = priv->info;
 264
 265        if (info->flags & IMX8_USE_SCU)
 266                return 0;
 267
 268        if (info->input_sel_base)
 269                unmap_sysmem(info->input_sel_base);
 270        if (info->base)
 271                unmap_sysmem(info->base);
 272
 273        return 0;
 274}
 275