LXR uboot/drivers/ram/stm32mp1/stm32mp1

   1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4 */
   5
   6#define LOG_CATEGORY UCLASS_RAM
   7
   8#include <common.h>
   9#include <clk.h>
  10#include <log.h>
  11#include <ram.h>
  12#include <reset.h>
  13#include <timer.h>
  14#include <asm/io.h>
  15#include <asm/arch/ddr.h>
  16#include <linux/bitops.h>
  17#include <linux/delay.h>
  18#include <linux/iopoll.h>
  19#include "stm32mp1_ddr.h"
  20#include "stm32mp1_ddr_regs.h"
  21
  22#define RCC_DDRITFCR            0xD8
  23
  24#define RCC_DDRITFCR_DDRCAPBRST         (BIT(14))
  25#define RCC_DDRITFCR_DDRCAXIRST         (BIT(15))
  26#define RCC_DDRITFCR_DDRCORERST         (BIT(16))
  27#define RCC_DDRITFCR_DPHYAPBRST         (BIT(17))
  28#define RCC_DDRITFCR_DPHYRST            (BIT(18))
  29#define RCC_DDRITFCR_DPHYCTLRST         (BIT(19))
  30#define RCC_DDRITFCR_DDRCKMOD_MASK      GENMASK(22, 20)
  31#define RCC_DDRITFCR_DDRCKMOD_ASR       BIT(20)
  32
  33struct reg_desc {
  34        const char *name;
  35        u16 offset;     /* offset for base address */
  36        u8 par_offset;  /* offset for parameter array */
  37};
  38
  39#define INVALID_OFFSET  0xFF
  40
  41#define DDRCTL_REG(x, y) \
  42        {#x,\
  43         offsetof(struct stm32mp1_ddrctl, x),\
  44         offsetof(struct y, x)}
  45
  46#define DDRPHY_REG(x, y) \
  47        {#x,\
  48         offsetof(struct stm32mp1_ddrphy, x),\
  49         offsetof(struct y, x)}
  50
  51#define DDR_REG_DYN(x) \
  52        {#x,\
  53         offsetof(struct stm32mp1_ddrctl, x),\
  54         INVALID_OFFSET}
  55
  56#define DDRPHY_REG_DYN(x) \
  57        {#x,\
  58         offsetof(struct stm32mp1_ddrphy, x),\
  59         INVALID_OFFSET}
  60
  61/***********************************************************
  62 * PARAMETERS: value get from device tree :
  63 *             size / order need to be aligned with binding
  64 *             modification NOT ALLOWED !!!
  65 ***********************************************************/
  66#define DDRCTL_REG_REG_SIZE     25      /* st,ctl-reg */
  67#define DDRCTL_REG_TIMING_SIZE  12      /* st,ctl-timing */
  68#define DDRCTL_REG_MAP_SIZE     9       /* st,ctl-map */
  69#define DDRCTL_REG_PERF_SIZE    17      /* st,ctl-perf */
  70
  71#define DDRPHY_REG_REG_SIZE     11      /* st,phy-reg */
  72#define DDRPHY_REG_TIMING_SIZE  10      /* st,phy-timing */
  73
  74#define DDRCTL_REG_REG(x)       DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
  75static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
  76        DDRCTL_REG_REG(mstr),
  77        DDRCTL_REG_REG(mrctrl0),
  78        DDRCTL_REG_REG(mrctrl1),
  79        DDRCTL_REG_REG(derateen),
  80        DDRCTL_REG_REG(derateint),
  81        DDRCTL_REG_REG(pwrctl),
  82        DDRCTL_REG_REG(pwrtmg),
  83        DDRCTL_REG_REG(hwlpctl),
  84        DDRCTL_REG_REG(rfshctl0),
  85        DDRCTL_REG_REG(rfshctl3),
  86        DDRCTL_REG_REG(crcparctl0),
  87        DDRCTL_REG_REG(zqctl0),
  88        DDRCTL_REG_REG(dfitmg0),
  89        DDRCTL_REG_REG(dfitmg1),
  90        DDRCTL_REG_REG(dfilpcfg0),
  91        DDRCTL_REG_REG(dfiupd0),
  92        DDRCTL_REG_REG(dfiupd1),
  93        DDRCTL_REG_REG(dfiupd2),
  94        DDRCTL_REG_REG(dfiphymstr),
  95        DDRCTL_REG_REG(odtmap),
  96        DDRCTL_REG_REG(dbg0),
  97        DDRCTL_REG_REG(dbg1),
  98        DDRCTL_REG_REG(dbgcmd),
  99        DDRCTL_REG_REG(poisoncfg),
 100        DDRCTL_REG_REG(pccfg),
 101};
 102
 103#define DDRCTL_REG_TIMING(x)    DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
 104static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
 105        DDRCTL_REG_TIMING(rfshtmg),
 106        DDRCTL_REG_TIMING(dramtmg0),
 107        DDRCTL_REG_TIMING(dramtmg1),
 108        DDRCTL_REG_TIMING(dramtmg2),
 109        DDRCTL_REG_TIMING(dramtmg3),
 110        DDRCTL_REG_TIMING(dramtmg4),
 111        DDRCTL_REG_TIMING(dramtmg5),
 112        DDRCTL_REG_TIMING(dramtmg6),
 113        DDRCTL_REG_TIMING(dramtmg7),
 114        DDRCTL_REG_TIMING(dramtmg8),
 115        DDRCTL_REG_TIMING(dramtmg14),
 116        DDRCTL_REG_TIMING(odtcfg),
 117};
 118
 119#define DDRCTL_REG_MAP(x)       DDRCTL_REG(x, stm32mp1_ddrctrl_map)
 120static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
 121        DDRCTL_REG_MAP(addrmap1),
 122        DDRCTL_REG_MAP(addrmap2),
 123        DDRCTL_REG_MAP(addrmap3),
 124        DDRCTL_REG_MAP(addrmap4),
 125        DDRCTL_REG_MAP(addrmap5),
 126        DDRCTL_REG_MAP(addrmap6),
 127        DDRCTL_REG_MAP(addrmap9),
 128        DDRCTL_REG_MAP(addrmap10),
 129        DDRCTL_REG_MAP(addrmap11),
 130};
 131
 132#define DDRCTL_REG_PERF(x)      DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
 133static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
 134        DDRCTL_REG_PERF(sched),
 135        DDRCTL_REG_PERF(sched1),
 136        DDRCTL_REG_PERF(perfhpr1),
 137        DDRCTL_REG_PERF(perflpr1),
 138        DDRCTL_REG_PERF(perfwr1),
 139        DDRCTL_REG_PERF(pcfgr_0),
 140        DDRCTL_REG_PERF(pcfgw_0),
 141        DDRCTL_REG_PERF(pcfgqos0_0),
 142        DDRCTL_REG_PERF(pcfgqos1_0),
 143        DDRCTL_REG_PERF(pcfgwqos0_0),
 144        DDRCTL_REG_PERF(pcfgwqos1_0),
 145        DDRCTL_REG_PERF(pcfgr_1),
 146        DDRCTL_REG_PERF(pcfgw_1),
 147        DDRCTL_REG_PERF(pcfgqos0_1),
 148        DDRCTL_REG_PERF(pcfgqos1_1),
 149        DDRCTL_REG_PERF(pcfgwqos0_1),
 150        DDRCTL_REG_PERF(pcfgwqos1_1),
 151};
 152
 153#define DDRPHY_REG_REG(x)       DDRPHY_REG(x, stm32mp1_ddrphy_reg)
 154static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
 155        DDRPHY_REG_REG(pgcr),
 156        DDRPHY_REG_REG(aciocr),
 157        DDRPHY_REG_REG(dxccr),
 158        DDRPHY_REG_REG(dsgcr),
 159        DDRPHY_REG_REG(dcr),
 160        DDRPHY_REG_REG(odtcr),
 161        DDRPHY_REG_REG(zq0cr1),
 162        DDRPHY_REG_REG(dx0gcr),
 163        DDRPHY_REG_REG(dx1gcr),
 164        DDRPHY_REG_REG(dx2gcr),
 165        DDRPHY_REG_REG(dx3gcr),
 166};
 167
 168#define DDRPHY_REG_TIMING(x)    DDRPHY_REG(x, stm32mp1_ddrphy_timing)
 169static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
 170        DDRPHY_REG_TIMING(ptr0),
 171        DDRPHY_REG_TIMING(ptr1),
 172        DDRPHY_REG_TIMING(ptr2),
 173        DDRPHY_REG_TIMING(dtpr0),
 174        DDRPHY_REG_TIMING(dtpr1),
 175        DDRPHY_REG_TIMING(dtpr2),
 176        DDRPHY_REG_TIMING(mr0),
 177        DDRPHY_REG_TIMING(mr1),
 178        DDRPHY_REG_TIMING(mr2),
 179        DDRPHY_REG_TIMING(mr3),
 180};
 181
 182/**************************************************************
 183 * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
 184 **************************************************************/
 185#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 186static const struct reg_desc ddr_dyn[] = {
 187        DDR_REG_DYN(stat),
 188        DDR_REG_DYN(init0),
 189        DDR_REG_DYN(dfimisc),
 190        DDR_REG_DYN(dfistat),
 191        DDR_REG_DYN(swctl),
 192        DDR_REG_DYN(swstat),
 193        DDR_REG_DYN(pctrl_0),
 194        DDR_REG_DYN(pctrl_1),
 195};
 196
 197#define DDR_REG_DYN_SIZE        ARRAY_SIZE(ddr_dyn)
 198
 199static const struct reg_desc ddrphy_dyn[] = {
 200        DDRPHY_REG_DYN(pir),
 201        DDRPHY_REG_DYN(pgsr),
 202        DDRPHY_REG_DYN(zq0sr0),
 203        DDRPHY_REG_DYN(zq0sr1),
 204        DDRPHY_REG_DYN(dx0gsr0),
 205        DDRPHY_REG_DYN(dx0gsr1),
 206        DDRPHY_REG_DYN(dx0dllcr),
 207        DDRPHY_REG_DYN(dx0dqtr),
 208        DDRPHY_REG_DYN(dx0dqstr),
 209        DDRPHY_REG_DYN(dx1gsr0),
 210        DDRPHY_REG_DYN(dx1gsr1),
 211        DDRPHY_REG_DYN(dx1dllcr),
 212        DDRPHY_REG_DYN(dx1dqtr),
 213        DDRPHY_REG_DYN(dx1dqstr),
 214        DDRPHY_REG_DYN(dx2gsr0),
 215        DDRPHY_REG_DYN(dx2gsr1),
 216        DDRPHY_REG_DYN(dx2dllcr),
 217        DDRPHY_REG_DYN(dx2dqtr),
 218        DDRPHY_REG_DYN(dx2dqstr),
 219        DDRPHY_REG_DYN(dx3gsr0),
 220        DDRPHY_REG_DYN(dx3gsr1),
 221        DDRPHY_REG_DYN(dx3dllcr),
 222        DDRPHY_REG_DYN(dx3dqtr),
 223        DDRPHY_REG_DYN(dx3dqstr),
 224};
 225
 226#define DDRPHY_REG_DYN_SIZE     ARRAY_SIZE(ddrphy_dyn)
 227
 228#endif
 229
 230/*****************************************************************
 231 * REGISTERS ARRAY: used to parse device tree and interactive mode
 232 *****************************************************************/
 233enum reg_type {
 234        REG_REG,
 235        REG_TIMING,
 236        REG_PERF,
 237        REG_MAP,
 238        REGPHY_REG,
 239        REGPHY_TIMING,
 240#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 241/* dynamic registers => managed in driver or not changed,
 242 * can be dumped in interactive mode
 243 */
 244        REG_DYN,
 245        REGPHY_DYN,
 246#endif
 247        REG_TYPE_NB
 248};
 249
 250enum base_type {
 251        DDR_BASE,
 252        DDRPHY_BASE,
 253        NONE_BASE
 254};
 255
 256struct ddr_reg_info {
 257        const char *name;
 258        const struct reg_desc *desc;
 259        u8 size;
 260        enum base_type base;
 261};
 262
 263const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
 264[REG_REG] = {
 265        "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
 266[REG_TIMING] = {
 267        "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
 268[REG_PERF] = {
 269        "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
 270[REG_MAP] = {
 271        "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
 272[REGPHY_REG] = {
 273        "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
 274[REGPHY_TIMING] = {
 275        "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
 276#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 277[REG_DYN] = {
 278        "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
 279[REGPHY_DYN] = {
 280        "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
 281#endif
 282
 283};
 284
 285const char *base_name[] = {
 286        [DDR_BASE] = "ctl",
 287        [DDRPHY_BASE] = "phy",
 288};
 289
 290static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
 291{
 292        if (base == DDRPHY_BASE)
 293                return (u32)priv->phy;
 294        else
 295                return (u32)priv->ctl;
 296}
 297
 298static void set_reg(const struct ddr_info *priv,
 299                    enum reg_type type,
 300                    const void *param)
 301{
 302        unsigned int i;
 303        unsigned int *ptr, value;
 304        enum base_type base = ddr_registers[type].base;
 305        u32 base_addr = get_base_addr(priv, base);
 306        const struct reg_desc *desc = ddr_registers[type].desc;
 307
 308        log_debug("init %s\n", ddr_registers[type].name);
 309        for (i = 0; i < ddr_registers[type].size; i++) {
 310                ptr = (unsigned int *)(base_addr + desc[i].offset);
 311                if (desc[i].par_offset == INVALID_OFFSET) {
 312                        log_err("invalid parameter offset for %s", desc[i].name);
 313                } else {
 314                        value = *((u32 *)((u32)param +
 315                                               desc[i].par_offset));
 316                        writel(value, ptr);
 317                        log_debug("[0x%x] %s= 0x%08x\n",
 318                                  (u32)ptr, desc[i].name, value);
 319                }
 320        }
 321}
 322
 323#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 324static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
 325{
 326        unsigned int *ptr;
 327
 328        ptr = (unsigned int *)(base_addr + desc->offset);
 329        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 330}
 331
 332static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
 333{
 334        unsigned int *ptr;
 335
 336        ptr = (unsigned int *)(par_addr + desc->par_offset);
 337        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 338}
 339
 340static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
 341{
 342        unsigned int i, j;
 343        const struct reg_desc *desc;
 344
 345        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 346                desc = ddr_registers[i].desc;
 347                for (j = 0; j < ddr_registers[i].size; j++) {
 348                        if (strcmp(name, desc[j].name) == 0) {
 349                                *type = i;
 350                                return &desc[j];
 351                        }
 352                }
 353        }
 354        *type = REG_TYPE_NB;
 355        return NULL;
 356}
 357
 358int stm32mp1_dump_reg(const struct ddr_info *priv,
 359                      const char *name)
 360{
 361        unsigned int i, j;
 362        const struct reg_desc *desc;
 363        u32 base_addr;
 364        enum base_type p_base;
 365        enum reg_type type;
 366        const char *p_name;
 367        enum base_type filter = NONE_BASE;
 368        int result = -1;
 369
 370        if (name) {
 371                if (strcmp(name, base_name[DDR_BASE]) == 0)
 372                        filter = DDR_BASE;
 373                else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
 374                        filter = DDRPHY_BASE;
 375        }
 376
 377        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 378                p_base = ddr_registers[i].base;
 379                p_name = ddr_registers[i].name;
 380                if (!name || (filter == p_base || !strcmp(name, p_name))) {
 381                        result = 0;
 382                        desc = ddr_registers[i].desc;
 383                        base_addr = get_base_addr(priv, p_base);
 384                        printf("==%s.%s==\n", base_name[p_base], p_name);
 385                        for (j = 0; j < ddr_registers[i].size; j++)
 386                                stm32mp1_dump_reg_desc(base_addr, &desc[j]);
 387                }
 388        }
 389        if (result) {
 390                desc = found_reg(name, &type);
 391                if (desc) {
 392                        p_base = ddr_registers[type].base;
 393                        base_addr = get_base_addr(priv, p_base);
 394                        stm32mp1_dump_reg_desc(base_addr, desc);
 395                        result = 0;
 396                }
 397        }
 398        return result;
 399}
 400
 401void stm32mp1_edit_reg(const struct ddr_info *priv,
 402                       char *name, char *string)
 403{
 404        unsigned long *ptr, value;
 405        enum reg_type type;
 406        enum base_type base;
 407        const struct reg_desc *desc;
 408        u32 base_addr;
 409
 410        desc = found_reg(name, &type);
 411
 412        if (!desc) {
 413                printf("%s not found\n", name);
 414                return;
 415        }
 416        if (strict_strtoul(string, 16, &value) < 0) {
 417                printf("invalid value %s\n", string);
 418                return;
 419        }
 420        base = ddr_registers[type].base;
 421        base_addr = get_base_addr(priv, base);
 422        ptr = (unsigned long *)(base_addr + desc->offset);
 423        writel(value, ptr);
 424        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 425}
 426
 427static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
 428                        enum reg_type type)
 429{
 430        u32 par_addr = 0x0;
 431
 432        switch (type) {
 433        case REG_REG:
 434                par_addr = (u32)&config->c_reg;
 435                break;
 436        case REG_TIMING:
 437                par_addr = (u32)&config->c_timing;
 438                break;
 439        case REG_PERF:
 440                par_addr = (u32)&config->c_perf;
 441                break;
 442        case REG_MAP:
 443                par_addr = (u32)&config->c_map;
 444                break;
 445        case REGPHY_REG:
 446                par_addr = (u32)&config->p_reg;
 447                break;
 448        case REGPHY_TIMING:
 449                par_addr = (u32)&config->p_timing;
 450                break;
 451        case REG_DYN:
 452        case REGPHY_DYN:
 453        case REG_TYPE_NB:
 454                par_addr = (u32)NULL;
 455                break;
 456        }
 457
 458        return par_addr;
 459}
 460
 461int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
 462                        const char *name)
 463{
 464        unsigned int i, j;
 465        const struct reg_desc *desc;
 466        u32 par_addr;
 467        enum base_type p_base;
 468        enum reg_type type;
 469        const char *p_name;
 470        enum base_type filter = NONE_BASE;
 471        int result = -EINVAL;
 472
 473        if (name) {
 474                if (strcmp(name, base_name[DDR_BASE]) == 0)
 475                        filter = DDR_BASE;
 476                else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
 477                        filter = DDRPHY_BASE;
 478        }
 479
 480        for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
 481                par_addr = get_par_addr(config, i);
 482                if (!par_addr)
 483                        continue;
 484                p_base = ddr_registers[i].base;
 485                p_name = ddr_registers[i].name;
 486                if (!name || (filter == p_base || !strcmp(name, p_name))) {
 487                        result = 0;
 488                        desc = ddr_registers[i].desc;
 489                        printf("==%s.%s==\n", base_name[p_base], p_name);
 490                        for (j = 0; j < ddr_registers[i].size; j++)
 491                                stm32mp1_dump_param_desc(par_addr, &desc[j]);
 492                }
 493        }
 494        if (result) {
 495                desc = found_reg(name, &type);
 496                if (desc) {
 497                        par_addr = get_par_addr(config, type);
 498                        if (par_addr) {
 499                                stm32mp1_dump_param_desc(par_addr, desc);
 500                                result = 0;
 501                        }
 502                }
 503        }
 504        return result;
 505}
 506
 507void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
 508                         char *name, char *string)
 509{
 510        unsigned long *ptr, value;
 511        enum reg_type type;
 512        const struct reg_desc *desc;
 513        u32 par_addr;
 514
 515        desc = found_reg(name, &type);
 516        if (!desc) {
 517                printf("%s not found\n", name);
 518                return;
 519        }
 520        if (strict_strtoul(string, 16, &value) < 0) {
 521                printf("invalid value %s\n", string);
 522                return;
 523        }
 524        par_addr = get_par_addr(config, type);
 525        if (!par_addr) {
 526                printf("no parameter %s\n", name);
 527                return;
 528        }
 529        ptr = (unsigned long *)(par_addr + desc->par_offset);
 530        writel(value, ptr);
 531        printf("%s= 0x%08x\n", desc->name, readl(ptr));
 532}
 533#endif
 534
 535__weak bool stm32mp1_ddr_interactive(void *priv,
 536                                     enum stm32mp1_ddr_interact_step step,
 537                                     const struct stm32mp1_ddr_config *config)
 538{
 539        return false;
 540}
 541
 542#define INTERACTIVE(step)\
 543        stm32mp1_ddr_interactive(priv, step, config)
 544
 545static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
 546{
 547        u32 pgsr;
 548        int ret;
 549
 550        ret = readl_poll_timeout(&phy->pgsr, pgsr,
 551                                 pgsr & (DDRPHYC_PGSR_IDONE |
 552                                         DDRPHYC_PGSR_DTERR |
 553                                         DDRPHYC_PGSR_DTIERR |
 554                                         DDRPHYC_PGSR_DFTERR |
 555                                         DDRPHYC_PGSR_RVERR |
 556                                         DDRPHYC_PGSR_RVEIRR),
 557                                1000000);
 558        log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
 559                  (u32)&phy->pgsr, pgsr, ret);
 560}
 561
 562static void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
 563{
 564        pir |= DDRPHYC_PIR_INIT;
 565        writel(pir, &phy->pir);
 566        log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
 567                  (u32)&phy->pir, pir, readl(&phy->pir));
 568
 569        /* need to wait 10 configuration clock before start polling */
 570        udelay(10);
 571
 572        /* Wait DRAM initialization and Gate Training Evaluation complete */
 573        ddrphy_idone_wait(phy);
 574}
 575
 576/* start quasi dynamic register update */
 577static void start_sw_done(struct stm32mp1_ddrctl *ctl)
 578{
 579        clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
 580}
 581
 582/* wait quasi dynamic register update */
 583static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
 584{
 585        int ret;
 586        u32 swstat;
 587
 588        setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
 589
 590        ret = readl_poll_timeout(&ctl->swstat, swstat,
 591                                 swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
 592                                 1000000);
 593        if (ret)
 594                panic("Timeout initialising DRAM : DDR->swstat = %x\n",
 595                      swstat);
 596
 597        log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
 598}
 599
 600/* wait quasi dynamic register update */
 601static void wait_operating_mode(struct ddr_info *priv, int mode)
 602{
 603        u32 stat, val, mask, val2 = 0, mask2 = 0;
 604        int ret;
 605
 606        mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
 607        val = mode;
 608        /* self-refresh due to software => check also STAT.selfref_type */
 609        if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
 610                mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
 611                val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
 612        } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
 613                /* normal mode: handle also automatic self refresh */
 614                mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
 615                        DDRCTRL_STAT_SELFREF_TYPE_MASK;
 616                val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
 617                       DDRCTRL_STAT_SELFREF_TYPE_ASR;
 618        }
 619
 620        ret = readl_poll_timeout(&priv->ctl->stat, stat,
 621                                 ((stat & mask) == val) ||
 622                                 (mask2 && ((stat & mask2) == val2)),
 623                                 1000000);
 624
 625        if (ret)
 626                panic("Timeout DRAM : DDR->stat = %x\n", stat);
 627
 628        log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
 629}
 630
 631static void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
 632{
 633        start_sw_done(ctl);
 634        /* quasi-dynamic register update*/
 635        setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
 636        clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
 637                                   DDRCTRL_PWRCTL_SELFREF_EN);
 638        clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 639        wait_sw_done_ack(ctl);
 640}
 641
 642static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
 643                                     u32 rfshctl3, u32 pwrctl)
 644{
 645        start_sw_done(ctl);
 646        if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
 647                clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
 648        if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
 649                setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
 650        if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
 651                setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
 652        setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 653        wait_sw_done_ack(ctl);
 654}
 655
 656static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl)
 657{
 658        struct stm32mp1_ddrctl *ctl = priv->ctl;
 659
 660        /* SSR is the best we can do. */
 661        if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE))
 662                return;
 663
 664        clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK,
 665                        RCC_DDRITFCR_DDRCKMOD_ASR);
 666
 667        start_sw_done(ctl);
 668
 669        setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN);
 670        writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) |
 671               DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01),
 672               &ctl->pwrtmg);
 673
 674        /* HSR we can do. */
 675        setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
 676
 677        if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */
 678                setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
 679
 680        setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 681        wait_sw_done_ack(ctl);
 682}
 683
 684/* board-specific DDR power initializations. */
 685__weak int board_ddr_power_init(enum ddr_type ddr_type)
 686{
 687        return 0;
 688}
 689
 690__maybe_unused
 691void stm32mp1_ddr_init(struct ddr_info *priv,
 692                       const struct stm32mp1_ddr_config *config)
 693{
 694        u32 pir;
 695        int ret = -EINVAL;
 696        char bus_width;
 697
 698        switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
 699        case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
 700                bus_width = 8;
 701                break;
 702        case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
 703                bus_width = 16;
 704                break;
 705        default:
 706                bus_width = 32;
 707                break;
 708        }
 709
 710
 711        if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 712                ret = board_ddr_power_init(STM32MP_DDR3);
 713        else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
 714                if (bus_width == 32)
 715                        ret = board_ddr_power_init(STM32MP_LPDDR2_32);
 716                else
 717                        ret = board_ddr_power_init(STM32MP_LPDDR2_16);
 718        } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
 719                if (bus_width == 32)
 720                        ret = board_ddr_power_init(STM32MP_LPDDR3_32);
 721                else
 722                        ret = board_ddr_power_init(STM32MP_LPDDR3_16);
 723        }
 724        if (ret)
 725                panic("ddr power init failed\n");
 726
 727start:
 728        log_debug("name = %s\n", config->info.name);
 729        log_debug("speed = %d kHz\n", config->info.speed);
 730        log_debug("size  = 0x%x\n", config->info.size);
 731/*
 732 * 1. Program the DWC_ddr_umctl2 registers
 733 * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
 734 */
 735        /* Assert All DDR part */
 736        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
 737        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
 738        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
 739        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
 740        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
 741        setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
 742
 743/* 1.2. start CLOCK */
 744        if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
 745                panic("invalid DRAM clock : %d kHz\n",
 746                      config->info.speed);
 747
 748/* 1.3. deassert reset */
 749        /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
 750        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
 751        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
 752        /* De-assert presetn once the clocks are active
 753         * and stable via DDRCAPBRST bit
 754         */
 755        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
 756
 757/* 1.4. wait 128 cycles to permit initialization of end logic */
 758        udelay(2);
 759        /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
 760
 761        if (INTERACTIVE(STEP_DDR_RESET))
 762                goto start;
 763
 764/* 1.5. initialize registers ddr_umctl2 */
 765        /* Stop uMCTL2 before PHY is ready */
 766        clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 767        log_debug("[0x%08x] dfimisc = 0x%08x\n",
 768                  (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
 769
 770        set_reg(priv, REG_REG, &config->c_reg);
 771        set_reg(priv, REG_TIMING, &config->c_timing);
 772        set_reg(priv, REG_MAP, &config->c_map);
 773
 774        /* skip CTRL init, SDRAM init is done by PHY PUBL */
 775        clrsetbits_le32(&priv->ctl->init0,
 776                        DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
 777                        DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
 778
 779        set_reg(priv, REG_PERF, &config->c_perf);
 780
 781        if (INTERACTIVE(STEP_CTL_INIT))
 782                goto start;
 783
 784/*  2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
 785        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
 786        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
 787        clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
 788
 789/*  3. start PHY init by accessing relevant PUBL registers
 790 *    (DXGCR, DCR, PTR*, MR*, DTPR*)
 791 */
 792        set_reg(priv, REGPHY_REG, &config->p_reg);
 793        set_reg(priv, REGPHY_TIMING, &config->p_timing);
 794
 795        if (INTERACTIVE(STEP_PHY_INIT))
 796                goto start;
 797
 798/*  4. Monitor PHY init status by polling PUBL register PGSR.IDONE
 799 *     Perform DDR PHY DRAM initialization and Gate Training Evaluation
 800 */
 801        ddrphy_idone_wait(priv->phy);
 802
 803/*  5. Indicate to PUBL that controller performs SDRAM initialization
 804 *     by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
 805 *     DRAM init is done by PHY, init0.skip_dram.init = 1
 806 */
 807        pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
 808              DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
 809
 810        if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 811                pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
 812
 813        stm32mp1_ddrphy_init(priv->phy, pir);
 814
 815/*  6. SET DFIMISC.dfi_init_complete_en to 1 */
 816        /* Enable quasi-dynamic register programming*/
 817        start_sw_done(priv->ctl);
 818        setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
 819        wait_sw_done_ack(priv->ctl);
 820
 821/*  7. Wait for DWC_ddr_umctl2 to move to normal operation mode
 822 *     by monitoring STAT.operating_mode signal
 823 */
 824        /* wait uMCTL2 ready */
 825
 826        wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
 827
 828        log_debug("DDR DQS training : ");
 829/*  8. Disable Auto refresh and power down by setting
 830 *    - RFSHCTL3.dis_au_refresh = 1
 831 *    - PWRCTL.powerdown_en = 0
 832 *    - DFIMISC.dfiinit_complete_en = 0
 833 */
 834        stm32mp1_refresh_disable(priv->ctl);
 835
 836/*  9. Program PUBL PGCR to enable refresh during training and rank to train
 837 *     not done => keep the programed value in PGCR
 838 */
 839
 840/* 10. configure PUBL PIR register to specify which training step to run */
 841        /* RVTRN is excuted only on LPDDR2/LPDDR3 */
 842        if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
 843                pir = DDRPHYC_PIR_QSTRN;
 844        else
 845                pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN;
 846        stm32mp1_ddrphy_init(priv->phy, pir);
 847
 848/* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
 849        ddrphy_idone_wait(priv->phy);
 850
 851/* 12. set back registers in step 8 to the orginal values if desidered */
 852        stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
 853                                 config->c_reg.pwrctl);
 854
 855/* Enable auto-self-refresh, which saves a bit of power at runtime. */
 856        stm32mp1_asr_enable(priv, config->c_reg.pwrctl);
 857
 858        /* enable uMCTL2 AXI port 0 and 1 */
 859        setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
 860        setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
 861
 862        if (INTERACTIVE(STEP_DDR_READY))
 863                goto start;
 864}
 865