LXR uboot/drivers/video/imx/ipu.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Porting to u-boot:
   4 *
   5 * (C) Copyright 2010
   6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
   7 *
   8 * Linux IPU driver for MX51:
   9 *
  10 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  11 */
  12
  13#ifndef __ASM_ARCH_IPU_H__
  14#define __ASM_ARCH_IPU_H__
  15
  16#include <linux/types.h>
  17#include <ipu_pixfmt.h>
  18
  19#define IDMA_CHAN_INVALID       0xFF
  20#define HIGH_RESOLUTION_WIDTH   1024
  21
  22struct clk {
  23        const char *name;
  24        int id;
  25        /* Source clock this clk depends on */
  26        struct clk *parent;
  27        /* Secondary clock to enable/disable with this clock */
  28        struct clk *secondary;
  29        /* Current clock rate */
  30        unsigned long rate;
  31        /* Reference count of clock enable/disable */
  32        __s8 usecount;
  33        /* Register bit position for clock's enable/disable control. */
  34        u8 enable_shift;
  35        /* Register address for clock's enable/disable control. */
  36        void *enable_reg;
  37        u32 flags;
  38        /*
  39         * Function ptr to recalculate the clock's rate based on parent
  40         * clock's rate
  41         */
  42        void (*recalc) (struct clk *);
  43        /*
  44         * Function ptr to set the clock to a new rate. The rate must match a
  45         * supported rate returned from round_rate. Leave blank if clock is not
  46        * programmable
  47         */
  48        int (*set_rate) (struct clk *, unsigned long);
  49        /*
  50         * Function ptr to round the requested clock rate to the nearest
  51         * supported rate that is less than or equal to the requested rate.
  52         */
  53        unsigned long (*round_rate) (struct clk *, unsigned long);
  54        /*
  55         * Function ptr to enable the clock. Leave blank if clock can not
  56         * be gated.
  57         */
  58        int (*enable) (struct clk *);
  59        /*
  60         * Function ptr to disable the clock. Leave blank if clock can not
  61         * be gated.
  62         */
  63        void (*disable) (struct clk *);
  64        /* Function ptr to set the parent clock of the clock. */
  65        int (*set_parent) (struct clk *, struct clk *);
  66};
  67
  68/*
  69 * Enumeration of Synchronous (Memory-less) panel types
  70 */
  71typedef enum {
  72        IPU_PANEL_SHARP_TFT,
  73        IPU_PANEL_TFT,
  74} ipu_panel_t;
  75
  76/*
  77 * IPU Driver channels definitions.
  78 * Note these are different from IDMA channels
  79 */
  80#define IPU_MAX_CH      32
  81#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
  82        ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
  83#define _MAKE_ALT_CHAN(ch)              (ch | (IPU_MAX_CH << 24))
  84#define IPU_CHAN_ID(ch)                 (ch >> 24)
  85#define IPU_CHAN_ALT(ch)                (ch & 0x02000000)
  86#define IPU_CHAN_ALPHA_IN_DMA(ch)       ((uint32_t) (ch >> 6) & 0x3F)
  87#define IPU_CHAN_GRAPH_IN_DMA(ch)       ((uint32_t) (ch >> 12) & 0x3F)
  88#define IPU_CHAN_VIDEO_IN_DMA(ch)       ((uint32_t) (ch >> 18) & 0x3F)
  89#define IPU_CHAN_OUT_DMA(ch)            ((uint32_t) (ch & 0x3F))
  90#define NO_DMA 0x3F
  91#define ALT     1
  92
  93/*
  94 * Enumeration of IPU logical channels. An IPU logical channel is defined as a
  95 * combination of an input (memory to IPU), output (IPU to memory), and/or
  96 * secondary input IDMA channels and in some cases an Image Converter task.
  97 * Some channels consist of only an input or output.
  98 */
  99typedef enum {
 100        CHAN_NONE = -1,
 101
 102        MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
 103        MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
 104        MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
 105        MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
 106
 107        MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
 108        MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
 109        MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
 110        MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
 111
 112        DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
 113        DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
 114
 115} ipu_channel_t;
 116
 117/*
 118 * Enumeration of types of buffers for a logical channel.
 119 */
 120typedef enum {
 121        IPU_OUTPUT_BUFFER = 0,  /*< Buffer for output from IPU */
 122        IPU_ALPHA_IN_BUFFER = 1,        /*< Buffer for input to IPU */
 123        IPU_GRAPH_IN_BUFFER = 2,        /*< Buffer for input to IPU */
 124        IPU_VIDEO_IN_BUFFER = 3,        /*< Buffer for input to IPU */
 125        IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
 126        IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
 127} ipu_buffer_t;
 128
 129#define IPU_PANEL_SERIAL                1
 130#define IPU_PANEL_PARALLEL              2
 131
 132struct ipu_channel {
 133        u8 video_in_dma;
 134        u8 alpha_in_dma;
 135        u8 graph_in_dma;
 136        u8 out_dma;
 137};
 138
 139enum ipu_dmfc_type {
 140        DMFC_NORMAL = 0,
 141        DMFC_HIGH_RESOLUTION_DC,
 142        DMFC_HIGH_RESOLUTION_DP,
 143        DMFC_HIGH_RESOLUTION_ONLY_DP,
 144};
 145
 146
 147/*
 148 * Union of initialization parameters for a logical channel.
 149 */
 150typedef union {
 151        struct {
 152                uint32_t di;
 153                unsigned char interlaced;
 154        } mem_dc_sync;
 155        struct {
 156                uint32_t temp;
 157        } mem_sdc_fg;
 158        struct {
 159                uint32_t di;
 160                unsigned char interlaced;
 161                uint32_t in_pixel_fmt;
 162                uint32_t out_pixel_fmt;
 163                unsigned char alpha_chan_en;
 164        } mem_dp_bg_sync;
 165        struct {
 166                uint32_t temp;
 167        } mem_sdc_bg;
 168        struct {
 169                uint32_t di;
 170                unsigned char interlaced;
 171                uint32_t in_pixel_fmt;
 172                uint32_t out_pixel_fmt;
 173                unsigned char alpha_chan_en;
 174        } mem_dp_fg_sync;
 175} ipu_channel_params_t;
 176
 177/*
 178 * Enumeration of IPU interrupts.
 179 */
 180enum ipu_irq_line {
 181        IPU_IRQ_DP_SF_END = 448 + 3,
 182        IPU_IRQ_DC_FC_1 = 448 + 9,
 183};
 184
 185/*
 186 * Bitfield of Display Interface signal polarities.
 187 */
 188typedef struct {
 189        unsigned datamask_en:1;
 190        unsigned ext_clk:1;
 191        unsigned interlaced:1;
 192        unsigned odd_field_first:1;
 193        unsigned clksel_en:1;
 194        unsigned clkidle_en:1;
 195        unsigned data_pol:1;    /* true = inverted */
 196        unsigned clk_pol:1;     /* true = rising edge */
 197        unsigned enable_pol:1;
 198        unsigned Hsync_pol:1;   /* true = active high */
 199        unsigned Vsync_pol:1;
 200} ipu_di_signal_cfg_t;
 201
 202typedef enum {
 203        RGB,
 204        YCbCr,
 205        YUV
 206} ipu_color_space_t;
 207
 208/* Common IPU API */
 209int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
 210void ipu_uninit_channel(ipu_channel_t channel);
 211
 212int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 213                                uint32_t pixel_fmt,
 214                                uint16_t width, uint16_t height,
 215                                uint32_t stride,
 216                                dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
 217                                uint32_t u_offset, uint32_t v_offset);
 218
 219int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
 220                                  uint32_t bufNum, dma_addr_t phyaddr);
 221
 222int32_t ipu_is_channel_busy(ipu_channel_t channel);
 223void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
 224                uint32_t bufNum);
 225int32_t ipu_enable_channel(ipu_channel_t channel);
 226int32_t ipu_disable_channel(ipu_channel_t channel);
 227
 228int32_t ipu_init_sync_panel(int disp,
 229                            uint32_t pixel_clk,
 230                            uint16_t width, uint16_t height,
 231                            uint32_t pixel_fmt,
 232                            uint16_t h_start_width, uint16_t h_sync_width,
 233                            uint16_t h_end_width, uint16_t v_start_width,
 234                            uint16_t v_sync_width, uint16_t v_end_width,
 235                            uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
 236
 237int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
 238                                  uint8_t alpha);
 239int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
 240                               uint32_t colorKey);
 241
 242uint32_t bytes_per_pixel(uint32_t fmt);
 243
 244void clk_enable(struct clk *clk);
 245void clk_disable(struct clk *clk);
 246u32 clk_get_rate(struct clk *clk);
 247int clk_set_rate(struct clk *clk, unsigned long rate);
 248long clk_round_rate(struct clk *clk, unsigned long rate);
 249int clk_set_parent(struct clk *clk, struct clk *parent);
 250int clk_get_usecount(struct clk *clk);
 251struct clk *clk_get_parent(struct clk *clk);
 252
 253void ipu_dump_registers(void);
 254int ipu_probe(void);
 255bool ipu_clk_enabled(void);
 256
 257void ipu_dmfc_init(int dmfc_type, int first);
 258void ipu_init_dc_mappings(void);
 259void ipu_dmfc_set_wait4eot(int dma_chan, int width);
 260void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
 261void ipu_dc_uninit(int dc_chan);
 262void ipu_dp_dc_enable(ipu_channel_t channel);
 263int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
 264                 uint32_t out_pixel_fmt);
 265void ipu_dp_uninit(ipu_channel_t channel);
 266void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
 267ipu_color_space_t format_to_colorspace(uint32_t fmt);
 268#endif
 269