LXR uboot/drivers/watchdog/designware

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
   4 */
   5
   6#include <clk.h>
   7#include <common.h>
   8#include <dm.h>
   9#include <reset.h>
  10#include <wdt.h>
  11#include <asm/io.h>
  12#include <linux/bitops.h>
  13
  14#define DW_WDT_CR       0x00
  15#define DW_WDT_TORR     0x04
  16#define DW_WDT_CRR      0x0C
  17
  18#define DW_WDT_CR_EN_OFFSET     0x00
  19#define DW_WDT_CR_RMOD_OFFSET   0x01
  20#define DW_WDT_CRR_RESTART_VAL  0x76
  21
  22struct designware_wdt_priv {
  23        void __iomem    *base;
  24        unsigned int    clk_khz;
  25        struct reset_ctl_bulk resets;
  26};
  27
  28/*
  29 * Set the watchdog time interval.
  30 * Counter is 32 bit.
  31 */
  32static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
  33                                     unsigned int timeout)
  34{
  35        signed int i;
  36
  37        /* calculate the timeout range value */
  38        i = fls(timeout * clk_khz - 1) - 16;
  39        i = clamp(i, 0, 15);
  40
  41        writel(i | (i << 4), base + DW_WDT_TORR);
  42
  43        return 0;
  44}
  45
  46static void designware_wdt_enable(void __iomem *base)
  47{
  48        writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
  49}
  50
  51static unsigned int designware_wdt_is_enabled(void __iomem *base)
  52{
  53        return readl(base + DW_WDT_CR) & BIT(0);
  54}
  55
  56static void designware_wdt_reset_common(void __iomem *base)
  57{
  58        if (designware_wdt_is_enabled(base))
  59                /* restart the watchdog counter */
  60                writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
  61}
  62
  63static int designware_wdt_reset(struct udevice *dev)
  64{
  65        struct designware_wdt_priv *priv = dev_get_priv(dev);
  66
  67        designware_wdt_reset_common(priv->base);
  68
  69        return 0;
  70}
  71
  72static int designware_wdt_stop(struct udevice *dev)
  73{
  74        struct designware_wdt_priv *priv = dev_get_priv(dev);
  75        __maybe_unused int ret;
  76
  77        designware_wdt_reset(dev);
  78        writel(0, priv->base + DW_WDT_CR);
  79
  80        if (CONFIG_IS_ENABLED(DM_RESET) &&
  81            ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) {
  82                ret = reset_assert_bulk(&priv->resets);
  83                if (ret)
  84                        return ret;
  85
  86                ret = reset_deassert_bulk(&priv->resets);
  87                if (ret)
  88                        return ret;
  89        }
  90
  91        return 0;
  92}
  93
  94static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
  95{
  96        struct designware_wdt_priv *priv = dev_get_priv(dev);
  97
  98        designware_wdt_stop(dev);
  99
 100        /* set timer in miliseconds */
 101        designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
 102
 103        designware_wdt_enable(priv->base);
 104
 105        /* reset the watchdog */
 106        return designware_wdt_reset(dev);
 107}
 108
 109static int designware_wdt_probe(struct udevice *dev)
 110{
 111        struct designware_wdt_priv *priv = dev_get_priv(dev);
 112        __maybe_unused int ret;
 113
 114        priv->base = dev_remap_addr(dev);
 115        if (!priv->base)
 116                return -EINVAL;
 117
 118#if CONFIG_IS_ENABLED(CLK)
 119        struct clk clk;
 120
 121        ret = clk_get_by_index(dev, 0, &clk);
 122        if (ret)
 123                return ret;
 124
 125        ret = clk_enable(&clk);
 126        if (ret)
 127                goto err;
 128
 129        priv->clk_khz = clk_get_rate(&clk) / 1000;
 130        if (!priv->clk_khz) {
 131                ret = -EINVAL;
 132                goto err;
 133        }
 134#else
 135        priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
 136#endif
 137
 138        if (CONFIG_IS_ENABLED(DM_RESET) &&
 139            ofnode_read_prop(dev_ofnode(dev), "resets", &ret)) {
 140                ret = reset_get_bulk(dev, &priv->resets);
 141                if (ret)
 142                        goto err;
 143
 144                ret = reset_deassert_bulk(&priv->resets);
 145                if (ret)
 146                        goto err;
 147        }
 148
 149        /* reset to disable the watchdog */
 150        return designware_wdt_stop(dev);
 151
 152err:
 153#if CONFIG_IS_ENABLED(CLK)
 154        clk_free(&clk);
 155#endif
 156        return ret;
 157}
 158
 159static const struct wdt_ops designware_wdt_ops = {
 160        .start = designware_wdt_start,
 161        .reset = designware_wdt_reset,
 162        .stop = designware_wdt_stop,
 163};
 164
 165static const struct udevice_id designware_wdt_ids[] = {
 166        { .compatible = "snps,dw-wdt"},
 167        {}
 168};
 169
 170U_BOOT_DRIVER(designware_wdt) = {
 171        .name = "designware_wdt",
 172        .id = UCLASS_WDT,
 173        .of_match = designware_wdt_ids,
 174        .priv_auto      = sizeof(struct designware_wdt_priv),
 175        .probe = designware_wdt_probe,
 176        .ops = &designware_wdt_ops,
 177        .flags = DM_FLAG_PRE_RELOC,
 178};
 179