LXR uboot/include/configs/T208xQDS.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
   4 * Copyright 2020-2021 NXP
   5 */
   6
   7/*
   8 * T2080/T2081 QDS board configuration file
   9 */
  10
  11#ifndef __T208xQDS_H
  12#define __T208xQDS_H
  13
  14#include <linux/stringify.h>
  15
  16#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  17#if defined(CONFIG_ARCH_T2080)
  18#define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  19#define CONFIG_SRIO1            /* SRIO port 1 */
  20#define CONFIG_SRIO2            /* SRIO port 2 */
  21#endif
  22
  23/* High Level Configuration Options */
  24
  25#define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  26
  27#ifdef CONFIG_RAMBOOT_PBL
  28#define RESET_VECTOR_OFFSET             0x27FFC
  29#define BOOT_PAGE_OFFSET                0x27000
  30
  31#ifdef CONFIG_MTD_RAW_NAND
  32#define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  33#define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  34#define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  35#endif
  36
  37#ifdef CONFIG_SPIFLASH
  38#define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  39#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  40#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  41#define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  42#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  43#endif
  44
  45#ifdef CONFIG_SDCARD
  46#define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  47#define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
  48#define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
  49#define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
  50#define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
  51#endif
  52
  53#endif /* CONFIG_RAMBOOT_PBL */
  54
  55#define CONFIG_SRIO_PCIE_BOOT_MASTER
  56#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  57/* Set 1M boot space */
  58#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  59#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  60                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  61#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  62#endif
  63
  64#ifndef CONFIG_RESET_VECTOR_ADDRESS
  65#define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  66#endif
  67
  68/*
  69 * These can be toggled for performance analysis, otherwise use default.
  70 */
  71#ifdef CONFIG_DDR_ECC
  72#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  73#endif
  74
  75/*
  76 * Config the L3 Cache as L3 SRAM
  77 */
  78#define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  79#define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  80
  81#define CONFIG_SYS_DCSRBAR      0xf0000000
  82#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  83
  84/*
  85 * DDR Setup
  86 */
  87#define CONFIG_VERY_BIG_RAM
  88#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  89#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90#define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
  91#define SPD_EEPROM_ADDRESS1     0x51
  92#define SPD_EEPROM_ADDRESS2     0x52
  93#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  94#define CTRL_INTLV_PREFERED     cacheline
  95
  96/*
  97 * IFC Definitions
  98 */
  99#define CONFIG_SYS_FLASH_BASE           0xe0000000
 100#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 101#define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 102#define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 103                                + 0x8000000) | \
 104                                CSPR_PORT_SIZE_16 | \
 105                                CSPR_MSEL_NOR | \
 106                                CSPR_V)
 107#define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 108#define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 109                                CSPR_PORT_SIZE_16 | \
 110                                CSPR_MSEL_NOR | \
 111                                CSPR_V)
 112#define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 113/* NOR Flash Timing Params */
 114#define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 115
 116#define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 117                                FTIM0_NOR_TEADC(0x5) | \
 118                                FTIM0_NOR_TEAHC(0x5))
 119#define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 120                                FTIM1_NOR_TRAD_NOR(0x1A) |\
 121                                FTIM1_NOR_TSEQRAD_NOR(0x13))
 122#define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 123                                FTIM2_NOR_TCH(0x4) | \
 124                                FTIM2_NOR_TWPH(0x0E) | \
 125                                FTIM2_NOR_TWP(0x1c))
 126#define CONFIG_SYS_NOR_FTIM3    0x0
 127
 128#define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 129
 130#define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 131                                        + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 132
 133#define QIXIS_BASE                      0xffdf0000
 134#define QIXIS_LBMAP_SWITCH              6
 135#define QIXIS_LBMAP_MASK                0x0f
 136#define QIXIS_LBMAP_SHIFT               0
 137#define QIXIS_LBMAP_DFLTBANK            0x00
 138#define QIXIS_LBMAP_ALTBANK             0x04
 139#define QIXIS_LBMAP_NAND                0x09
 140#define QIXIS_LBMAP_SD                  0x00
 141#define QIXIS_RCW_SRC_NAND              0x104
 142#define QIXIS_RCW_SRC_SD                0x040
 143#define QIXIS_RST_CTL_RESET             0x83
 144#define QIXIS_RST_FORCE_MEM             0x1
 145#define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 146#define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 147#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 148#define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 149
 150#define CONFIG_SYS_CSPR3_EXT    (0xf)
 151#define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 152                                | CSPR_PORT_SIZE_8 \
 153                                | CSPR_MSEL_GPCM \
 154                                | CSPR_V)
 155#define CONFIG_SYS_AMASK3       IFC_AMASK(64 * 1024)
 156#define CONFIG_SYS_CSOR3        0x0
 157/* QIXIS Timing parameters for IFC CS3 */
 158#define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 159                                        FTIM0_GPCM_TEADC(0x0e) | \
 160                                        FTIM0_GPCM_TEAHC(0x0e))
 161#define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 162                                        FTIM1_GPCM_TRAD(0x3f))
 163#define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 164                                        FTIM2_GPCM_TCH(0x8) | \
 165                                        FTIM2_GPCM_TWP(0x1f))
 166#define CONFIG_SYS_CS3_FTIM3            0x0
 167
 168/* NAND Flash on IFC */
 169#define CONFIG_SYS_NAND_BASE            0xff800000
 170#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 171
 172#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 173#define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 174                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 175                                | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 176                                | CSPR_V)
 177#define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 178
 179#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 180                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 181                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 182                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 183                                | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 184                                | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 185                                | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 186
 187/* ONFI NAND Flash mode0 Timing Params */
 188#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 189                                        FTIM0_NAND_TWP(0x18)    | \
 190                                        FTIM0_NAND_TWCHT(0x07)  | \
 191                                        FTIM0_NAND_TWH(0x0a))
 192#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 193                                        FTIM1_NAND_TWBE(0x39)   | \
 194                                        FTIM1_NAND_TRR(0x0e)    | \
 195                                        FTIM1_NAND_TRP(0x18))
 196#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 197                                        FTIM2_NAND_TREH(0x0a)   | \
 198                                        FTIM2_NAND_TWHRE(0x1e))
 199#define CONFIG_SYS_NAND_FTIM3           0x0
 200
 201#define CONFIG_SYS_NAND_DDR_LAW         11
 202#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 203
 204#if defined(CONFIG_MTD_RAW_NAND)
 205#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 206#define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 207#define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 208#define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 209#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 210#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 211#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 212#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 213#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 214#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 215#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 216#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 217#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 218#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 219#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 220#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 221#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 222#define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 223#define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 224#define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 225#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 226#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 227#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 228#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 229#else
 230#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 231#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 232#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 233#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 234#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 235#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 236#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 237#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 238#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 239#define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 240#define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 241#define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 242#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 243#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 244#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 245#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 246#define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 247#define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 248#define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 249#define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 250#define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 251#define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 252#define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 253#define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 254#endif
 255
 256#define CONFIG_HWCONFIG
 257
 258/* define to use L1 as initial stack */
 259#define CONFIG_L1_INIT_RAM
 260#define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 261#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 262#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 263/* The assembler doesn't like typecast */
 264#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 265                        ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 266                        CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 267#define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 268#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 269
 270/*
 271 * Serial Port
 272 */
 273#define CONFIG_SYS_NS16550_SERIAL
 274#define CONFIG_SYS_NS16550_REG_SIZE     1
 275#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 276#define CONFIG_SYS_BAUDRATE_TABLE       \
 277        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 278#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 279#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 280#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 281#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 282
 283/*
 284 * I2C
 285 */
 286
 287#define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 288#define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 289#define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 290#define I2C_MUX_CH_DEFAULT      0x8
 291
 292#define I2C_MUX_CH_VOL_MONITOR 0xa
 293
 294/* Voltage monitor on channel 2*/
 295#define I2C_VOL_MONITOR_ADDR           0x40
 296#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 297#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 298#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 299
 300/* The lowest and highest voltage allowed for T208xQDS */
 301#define VDD_MV_MIN                      819
 302#define VDD_MV_MAX                      1212
 303
 304/*
 305 * RapidIO
 306 */
 307#define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 308#define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 309#define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 310#define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 311#define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 312#define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 313/*
 314 * for slave u-boot IMAGE instored in master memory space,
 315 * PHYS must be aligned based on the SIZE
 316 */
 317#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 318#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 319#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 320#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 321/*
 322 * for slave UCODE and ENV instored in master memory space,
 323 * PHYS must be aligned based on the SIZE
 324 */
 325#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 326#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 327#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 328
 329/* slave core release by master*/
 330#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 331#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 332
 333/*
 334 * SRIO_PCIE_BOOT - SLAVE
 335 */
 336#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 337#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 338#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 339                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 340#endif
 341
 342/*
 343 * eSPI - Enhanced SPI
 344 */
 345
 346/*
 347 * General PCI
 348 * Memory space is mapped 1-1, but I/O space must start from 0.
 349 */
 350/* controller 1, direct to uli, tgtid 3, Base address 20000 */
 351#define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 352#define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 353#define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 354#define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 355
 356/* controller 2, Slot 2, tgtid 2, Base address 201000 */
 357#define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 358#define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 359#define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 360#define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 361
 362/* controller 3, Slot 1, tgtid 1, Base address 202000 */
 363#define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 364#define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 365#define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 366#define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 367
 368/* controller 4, Base address 203000 */
 369#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 370#define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 371#define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 372
 373/* Qman/Bman */
 374#ifndef CONFIG_NOBQFMAN
 375#define CONFIG_SYS_BMAN_NUM_PORTALS     18
 376#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 377#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 378#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 379#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 380#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 381#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 382#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 383#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 384                                        CONFIG_SYS_BMAN_CENA_SIZE)
 385#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 386#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 387#define CONFIG_SYS_QMAN_NUM_PORTALS     18
 388#define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 389#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 390#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 391#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 392#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 393#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 394#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 395#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 396                                        CONFIG_SYS_QMAN_CENA_SIZE)
 397#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 398#define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 399
 400#define CONFIG_SYS_DPAA_FMAN
 401#define CONFIG_SYS_DPAA_PME
 402#define CONFIG_SYS_PMAN
 403#define CONFIG_SYS_DPAA_DCE
 404#define CONFIG_SYS_DPAA_RMAN            /* RMan */
 405#endif /* CONFIG_NOBQFMAN */
 406
 407#ifdef CONFIG_SYS_DPAA_FMAN
 408#define RGMII_PHY1_ADDR 0x1
 409#define RGMII_PHY2_ADDR 0x2
 410#define FM1_10GEC1_PHY_ADDR       0x3
 411#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 412#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 413#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 414#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 415#endif
 416
 417/*
 418 * USB
 419 */
 420
 421/*
 422 * SDHC
 423 */
 424#ifdef CONFIG_MMC
 425#define CFG_SYS_FSL_ESDHC_ADDR  CFG_SYS_MPC85xx_ESDHC_ADDR
 426#endif
 427
 428/*
 429 * Dynamic MTD Partition support with mtdparts
 430 */
 431
 432/*
 433 * Miscellaneous configurable options
 434 */
 435
 436/*
 437 * For booting Linux, the board info and command line data
 438 * have to be in the first 64 MB of memory, since this is
 439 * the maximum mapped by the Linux kernel during initialization.
 440 */
 441#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 442
 443/*
 444 * Environment Configuration
 445 */
 446#define CONFIG_ROOTPATH  "/opt/nfsroot"
 447#define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 448
 449#define __USB_PHY_TYPE          utmi
 450
 451#define CONFIG_EXTRA_ENV_SETTINGS                               \
 452        "hwconfig=fsl_ddr:"                                     \
 453        "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 454        "bank_intlv=auto;"                                      \
 455        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 456        "netdev=eth0\0"                                         \
 457        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 458        "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 459        "tftpflash=tftpboot $loadaddr $uboot && "               \
 460        "protect off $ubootaddr +$filesize && "                 \
 461        "erase $ubootaddr +$filesize && "                       \
 462        "cp.b $loadaddr $ubootaddr $filesize && "               \
 463        "protect on $ubootaddr +$filesize && "                  \
 464        "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 465        "consoledev=ttyS0\0"                                    \
 466        "ramdiskaddr=2000000\0"                                 \
 467        "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 468        "fdtaddr=1e00000\0"                                     \
 469        "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 470        "bdev=sda3\0"
 471
 472/*
 473 * For emulation this causes u-boot to jump to the start of the
 474 * proof point app code automatically
 475 */
 476#define PROOF_POINTS                            \
 477        "setenv bootargs root=/dev/$bdev rw "           \
 478        "console=$consoledev,$baudrate $othbootargs;"   \
 479        "cpu 1 release 0x29000000 - - -;"               \
 480        "cpu 2 release 0x29000000 - - -;"               \
 481        "cpu 3 release 0x29000000 - - -;"               \
 482        "cpu 4 release 0x29000000 - - -;"               \
 483        "cpu 5 release 0x29000000 - - -;"               \
 484        "cpu 6 release 0x29000000 - - -;"               \
 485        "cpu 7 release 0x29000000 - - -;"               \
 486        "go 0x29000000"
 487
 488#define HVBOOT                          \
 489        "setenv bootargs config-addr=0x60000000; "      \
 490        "bootm 0x01000000 - 0x00f00000"
 491
 492#define ALU                             \
 493        "setenv bootargs root=/dev/$bdev rw "           \
 494        "console=$consoledev,$baudrate $othbootargs;"   \
 495        "cpu 1 release 0x01000000 - - -;"               \
 496        "cpu 2 release 0x01000000 - - -;"               \
 497        "cpu 3 release 0x01000000 - - -;"               \
 498        "cpu 4 release 0x01000000 - - -;"               \
 499        "cpu 5 release 0x01000000 - - -;"               \
 500        "cpu 6 release 0x01000000 - - -;"               \
 501        "cpu 7 release 0x01000000 - - -;"               \
 502        "go 0x01000000"
 503
 504#include <asm/fsl_secure_boot.h>
 505
 506#endif  /* __T208xQDS_H */
 507