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7#ifndef _ASM_ARCH_CRU_RK3588_H
8#define _ASM_ARCH_CRU_RK3588_H
9
10#define MHz 1000000
11#define KHz 1000
12#define OSC_HZ (24 * MHz)
13
14#define CPU_PVTPLL_HZ (1008 * MHz)
15#define LPLL_HZ (816 * MHz)
16#define GPLL_HZ (1188 * MHz)
17#define CPLL_HZ (1500 * MHz)
18#define NPLL_HZ (850 * MHz)
19#define PPLL_HZ (1100 * MHz)
20
21
22enum rk3588_pll_id {
23 B0PLL,
24 B1PLL,
25 LPLL,
26 CPLL,
27 GPLL,
28 NPLL,
29 V0PLL,
30 AUPLL,
31 PPLL,
32 PLL_COUNT,
33};
34
35struct rk3588_clk_info {
36 unsigned long id;
37 char *name;
38 bool is_cru;
39};
40
41struct rk3588_clk_priv {
42 struct rk3588_cru *cru;
43 struct rk3588_grf *grf;
44 ulong ppll_hz;
45 ulong gpll_hz;
46 ulong cpll_hz;
47 ulong npll_hz;
48 ulong v0pll_hz;
49 ulong aupll_hz;
50 ulong armclk_hz;
51 ulong armclk_enter_hz;
52 ulong armclk_init_hz;
53 bool sync_kernel;
54 bool set_armclk_rate;
55};
56
57struct rk3588_pll {
58 unsigned int con0;
59 unsigned int con1;
60 unsigned int con2;
61 unsigned int con3;
62 unsigned int con4;
63 unsigned int reserved0[3];
64};
65
66struct rk3588_cru {
67 struct rk3588_pll pll[18];
68 unsigned int reserved0[16];
69 unsigned int mode_con00;
70 unsigned int reserved1[31];
71 unsigned int clksel_con[178];
72 unsigned int reserved2[142];
73 unsigned int clkgate_con[78];
74 unsigned int reserved3[50];
75 unsigned int softrst_con[78];
76 unsigned int reserved4[50];
77 unsigned int glb_cnt_th;
78 unsigned int glb_rst_st;
79 unsigned int glb_srst_fst;
80 unsigned int glb_srsr_snd;
81 unsigned int glb_rst_con;
82 unsigned int reserved5[4];
83 unsigned int sdio_con[2];
84 unsigned int reserved7;
85 unsigned int sdmmc_con[2];
86 unsigned int reserved8[48562];
87 unsigned int pmuclksel_con[21];
88 unsigned int reserved9[299];
89 unsigned int pmuclkgate_con[9];
90};
91
92check_member(rk3588_cru, mode_con00, 0x280);
93check_member(rk3588_cru, pmuclksel_con[1], 0x30304);
94
95struct pll_rate_table {
96 unsigned long rate;
97 unsigned int m;
98 unsigned int p;
99 unsigned int s;
100 unsigned int k;
101};
102
103#define RK3588_PLL_CON(x) ((x) * 0x4)
104#define RK3588_MODE_CON 0x280
105
106#define RK3588_PHP_CRU_BASE 0x8000
107#define RK3588_PMU_CRU_BASE 0x30000
108#define RK3588_BIGCORE0_CRU_BASE 0x50000
109#define RK3588_BIGCORE1_CRU_BASE 0x52000
110#define RK3588_DSU_CRU_BASE 0x58000
111
112#define RK3588_PLL_CON(x) ((x) * 0x4)
113#define RK3588_MODE_CON0 0x280
114#define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
115#define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
116#define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
117#define RK3588_GLB_CNT_TH 0xc00
118#define RK3588_GLB_SRST_FST 0xc08
119#define RK3588_GLB_SRST_SND 0xc0c
120#define RK3588_GLB_RST_CON 0xc10
121#define RK3588_GLB_RST_ST 0xc04
122#define RK3588_SDIO_CON0 0xC24
123#define RK3588_SDIO_CON1 0xC28
124#define RK3588_SDMMC_CON0 0xC30
125#define RK3588_SDMMC_CON1 0xC34
126
127#define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
128#define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
129
130#define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
131#define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
132#define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
133#define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
134
135#define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
136#define RK3588_B0_PLL_MODE_CON (RK3588_BIGCORE0_CRU_BASE + 0x280)
137#define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
138#define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
139#define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
140#define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
141#define RK3588_B1_PLL_MODE_CON (RK3588_BIGCORE1_CRU_BASE + 0x280)
142#define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
143#define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
144#define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
145#define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
146#define RK3588_LPLL_MODE_CON (RK3588_DSU_CRU_BASE + 0x280)
147#define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
148#define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
149#define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
150
151enum {
152
153 ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT = 14,
154 ACLK_LOW_TOP_ROOT_SRC_SEL_MASK = 1 << ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT,
155 ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL = 0,
156 ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL,
157 ACLK_LOW_TOP_ROOT_DIV_SHIFT = 9,
158 ACLK_LOW_TOP_ROOT_DIV_MASK = 0x1f << ACLK_LOW_TOP_ROOT_DIV_SHIFT,
159 PCLK_TOP_ROOT_SEL_SHIFT = 7,
160 PCLK_TOP_ROOT_SEL_MASK = 3 << PCLK_TOP_ROOT_SEL_SHIFT,
161 PCLK_TOP_ROOT_SEL_100M = 0,
162 PCLK_TOP_ROOT_SEL_50M,
163 PCLK_TOP_ROOT_SEL_24M,
164 ACLK_TOP_ROOT_SRC_SEL_SHIFT = 5,
165 ACLK_TOP_ROOT_SRC_SEL_MASK = 3 << ACLK_TOP_ROOT_SRC_SEL_SHIFT,
166 ACLK_TOP_ROOT_SRC_SEL_GPLL = 0,
167 ACLK_TOP_ROOT_SRC_SEL_CPLL,
168 ACLK_TOP_ROOT_SRC_SEL_AUPLL,
169 ACLK_TOP_ROOT_DIV_SHIFT = 0,
170 ACLK_TOP_ROOT_DIV_MASK = 0x1f << ACLK_TOP_ROOT_DIV_SHIFT,
171
172
173 ACLK_TOP_S400_SEL_SHIFT = 8,
174 ACLK_TOP_S400_SEL_MASK = 3 << ACLK_TOP_S400_SEL_SHIFT,
175 ACLK_TOP_S400_SEL_400M = 0,
176 ACLK_TOP_S400_SEL_200M,
177 ACLK_TOP_S200_SEL_SHIFT = 6,
178 ACLK_TOP_S200_SEL_MASK = 3 << ACLK_TOP_S200_SEL_SHIFT,
179 ACLK_TOP_S200_SEL_200M = 0,
180 ACLK_TOP_S200_SEL_100M,
181
182
183 CLK_I2C8_SEL_SHIFT = 13,
184 CLK_I2C8_SEL_MASK = 1 << CLK_I2C8_SEL_SHIFT,
185 CLK_I2C7_SEL_SHIFT = 12,
186 CLK_I2C7_SEL_MASK = 1 << CLK_I2C7_SEL_SHIFT,
187 CLK_I2C6_SEL_SHIFT = 11,
188 CLK_I2C6_SEL_MASK = 1 << CLK_I2C6_SEL_SHIFT,
189 CLK_I2C5_SEL_SHIFT = 10,
190 CLK_I2C5_SEL_MASK = 1 << CLK_I2C5_SEL_SHIFT,
191 CLK_I2C4_SEL_SHIFT = 9,
192 CLK_I2C4_SEL_MASK = 1 << CLK_I2C4_SEL_SHIFT,
193 CLK_I2C3_SEL_SHIFT = 8,
194 CLK_I2C3_SEL_MASK = 1 << CLK_I2C3_SEL_SHIFT,
195 CLK_I2C2_SEL_SHIFT = 7,
196 CLK_I2C2_SEL_MASK = 1 << CLK_I2C2_SEL_SHIFT,
197 CLK_I2C1_SEL_SHIFT = 6,
198 CLK_I2C1_SEL_MASK = 1 << CLK_I2C1_SEL_SHIFT,
199 ACLK_BUS_ROOT_SEL_SHIFT = 5,
200 ACLK_BUS_ROOT_SEL_MASK = 3 << ACLK_BUS_ROOT_SEL_SHIFT,
201 ACLK_BUS_ROOT_SEL_GPLL = 0,
202 ACLK_BUS_ROOT_SEL_CPLL,
203 ACLK_BUS_ROOT_DIV_SHIFT = 0,
204 ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
205
206
207 CLK_SARADC_SEL_SHIFT = 14,
208 CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
209 CLK_SARADC_SEL_GPLL = 0,
210 CLK_SARADC_SEL_24M,
211 CLK_SARADC_DIV_SHIFT = 6,
212 CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
213
214
215 CLK_UART_SRC_SEL_SHIFT = 14,
216 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
217 CLK_UART_SRC_SEL_GPLL = 0,
218 CLK_UART_SRC_SEL_CPLL,
219 CLK_UART_SRC_DIV_SHIFT = 9,
220 CLK_UART_SRC_DIV_MASK = 0x1f << CLK_UART_SRC_DIV_SHIFT,
221 CLK_TSADC_SEL_SHIFT = 8,
222 CLK_TSADC_SEL_MASK = 0x1 << CLK_TSADC_SEL_SHIFT,
223 CLK_TSADC_SEL_GPLL = 0,
224 CLK_TSADC_SEL_24M,
225 CLK_TSADC_DIV_SHIFT = 0,
226 CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
227
228
229 CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
230 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
231 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
232 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
233
234
235 CLK_UART_SEL_SHIFT = 0,
236 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
237 CLK_UART_SEL_SRC = 0,
238 CLK_UART_SEL_FRAC,
239 CLK_UART_SEL_XIN24M,
240
241
242 CLK_PWM2_SEL_SHIFT = 14,
243 CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
244 CLK_PWM1_SEL_SHIFT = 12,
245 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
246 CLK_SPI4_SEL_SHIFT = 10,
247 CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
248 CLK_SPI3_SEL_SHIFT = 8,
249 CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
250 CLK_SPI2_SEL_SHIFT = 6,
251 CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
252 CLK_SPI1_SEL_SHIFT = 4,
253 CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
254 CLK_SPI0_SEL_SHIFT = 2,
255 CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
256 CLK_SPI_SEL_200M = 0,
257 CLK_SPI_SEL_150M,
258 CLK_SPI_SEL_24M,
259
260
261 CLK_PWM3_SEL_SHIFT = 0,
262 CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
263 CLK_PWM_SEL_100M = 0,
264 CLK_PWM_SEL_50M,
265 CLK_PWM_SEL_24M,
266
267
268 DCLK_DECOM_SEL_SHIFT = 5,
269 DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
270 DCLK_DECOM_SEL_GPLL = 0,
271 DCLK_DECOM_SEL_SPLL,
272 DCLK_DECOM_DIV_SHIFT = 0,
273 DCLK_DECOM_DIV_MASK = 0x1F << DCLK_DECOM_DIV_SHIFT,
274
275
276 CCLK_EMMC_SEL_SHIFT = 14,
277 CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
278 CCLK_EMMC_SEL_GPLL = 0,
279 CCLK_EMMC_SEL_CPLL,
280 CCLK_EMMC_SEL_24M,
281 CCLK_EMMC_DIV_SHIFT = 8,
282 CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
283
284
285 SCLK_SFC_SEL_SHIFT = 12,
286 SCLK_SFC_SEL_MASK = 3 << SCLK_SFC_SEL_SHIFT,
287 SCLK_SFC_SEL_GPLL = 0,
288 SCLK_SFC_SEL_CPLL,
289 SCLK_SFC_SEL_24M,
290 SCLK_SFC_DIV_SHIFT = 6,
291 SCLK_SFC_DIV_MASK = 0x3f << SCLK_SFC_DIV_SHIFT,
292 BCLK_EMMC_SEL_SHIFT = 5,
293 BCLK_EMMC_SEL_MASK = 1 << BCLK_EMMC_SEL_SHIFT,
294 BCLK_EMMC_SEL_GPLL = 0,
295 BCLK_EMMC_SEL_CPLL,
296 BCLK_EMMC_DIV_SHIFT = 0,
297 BCLK_EMMC_DIV_MASK = 0x1f << BCLK_EMMC_DIV_SHIFT,
298
299
300 CLK_GMAC1_PTP_SEL_SHIFT = 13,
301 CLK_GMAC1_PTP_SEL_MASK = 1 << CLK_GMAC1_PTP_SEL_SHIFT,
302 CLK_GMAC1_PTP_SEL_CPLL = 0,
303 CLK_GMAC1_PTP_DIV_SHIFT = 7,
304 CLK_GMAC1_PTP_DIV_MASK = 0x3f << CLK_GMAC1_PTP_DIV_SHIFT,
305 CLK_GMAC0_PTP_SEL_SHIFT = 6,
306 CLK_GMAC0_PTP_SEL_MASK = 1 << CLK_GMAC0_PTP_SEL_SHIFT,
307 CLK_GMAC0_PTP_SEL_CPLL = 0,
308 CLK_GMAC0_PTP_DIV_SHIFT = 0,
309 CLK_GMAC0_PTP_DIV_MASK = 0x3f << CLK_GMAC0_PTP_DIV_SHIFT,
310
311
312 CLK_GMAC_125M_SEL_SHIFT = 15,
313 CLK_GMAC_125M_SEL_MASK = 1 << CLK_GMAC_125M_SEL_SHIFT,
314 CLK_GMAC_125M_SEL_GPLL = 0,
315 CLK_GMAC_125M_SEL_CPLL,
316 CLK_GMAC_125M_DIV_SHIFT = 8,
317 CLK_GMAC_125M_DIV_MASK = 0x7f << CLK_GMAC_125M_DIV_SHIFT,
318
319
320 CLK_GMAC_50M_SEL_SHIFT = 7,
321 CLK_GMAC_50M_SEL_MASK = 1 << CLK_GMAC_50M_SEL_SHIFT,
322 CLK_GMAC_50M_SEL_GPLL = 0,
323 CLK_GMAC_50M_SEL_CPLL,
324 CLK_GMAC_50M_DIV_SHIFT = 0,
325 CLK_GMAC_50M_DIV_MASK = 0x7f << CLK_GMAC_50M_DIV_SHIFT,
326
327
328 HCLK_VOP_ROOT_SEL_SHIFT = 10,
329 HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
330 HCLK_VOP_ROOT_SEL_200M = 0,
331 HCLK_VOP_ROOT_SEL_100M,
332 HCLK_VOP_ROOT_SEL_50M,
333 HCLK_VOP_ROOT_SEL_24M,
334 ACLK_VOP_LOW_ROOT_SEL_SHIFT = 8,
335 ACLK_VOP_LOW_ROOT_SEL_MASK = 3 << ACLK_VOP_LOW_ROOT_SEL_SHIFT,
336 ACLK_VOP_LOW_ROOT_SEL_400M = 0,
337 ACLK_VOP_LOW_ROOT_SEL_200M,
338 ACLK_VOP_LOW_ROOT_SEL_100M,
339 ACLK_VOP_LOW_ROOT_SEL_24M,
340 ACLK_VOP_ROOT_SEL_SHIFT = 5,
341 ACLK_VOP_ROOT_SEL_MASK = 3 << ACLK_VOP_ROOT_SEL_SHIFT,
342 ACLK_VOP_ROOT_SEL_GPLL = 0,
343 ACLK_VOP_ROOT_SEL_CPLL,
344 ACLK_VOP_ROOT_SEL_AUPLL,
345 ACLK_VOP_ROOT_SEL_NPLL,
346 ACLK_VOP_ROOT_SEL_SPLL,
347 ACLK_VOP_ROOT_DIV_SHIFT = 0,
348 ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
349
350
351 DCLK1_VOP_SRC_SEL_SHIFT = 14,
352 DCLK1_VOP_SRC_SEL_MASK = 3 << DCLK1_VOP_SRC_SEL_SHIFT,
353 DCLK1_VOP_SRC_DIV_SHIFT = 9,
354 DCLK1_VOP_SRC_DIV_MASK = 0x1f << DCLK1_VOP_SRC_DIV_SHIFT,
355 DCLK0_VOP_SRC_SEL_SHIFT = 7,
356 DCLK0_VOP_SRC_SEL_MASK = 3 << DCLK0_VOP_SRC_SEL_SHIFT,
357 DCLK_VOP_SRC_SEL_GPLL = 0,
358 DCLK_VOP_SRC_SEL_CPLL,
359 DCLK_VOP_SRC_SEL_V0PLL,
360 DCLK_VOP_SRC_SEL_AUPLL,
361 DCLK0_VOP_SRC_DIV_SHIFT = 0,
362 DCLK0_VOP_SRC_DIV_MASK = 0x7f << DCLK0_VOP_SRC_DIV_SHIFT,
363
364
365 DCLK2_VOP_SEL_SHIFT = 11,
366 DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
367 DCLK1_VOP_SEL_SHIFT = 9,
368 DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
369 DCLK0_VOP_SEL_SHIFT = 7,
370 DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
371 DCLK2_VOP_SRC_SEL_SHIFT = 5,
372 DCLK2_VOP_SRC_SEL_MASK = 3 << DCLK2_VOP_SRC_SEL_SHIFT,
373 DCLK2_VOP_SRC_DIV_SHIFT = 0,
374 DCLK2_VOP_SRC_DIV_MASK = 0x1f << DCLK2_VOP_SRC_DIV_SHIFT,
375
376
377 DCLK3_VOP_SRC_SEL_SHIFT = 7,
378 DCLK3_VOP_SRC_SEL_MASK = 3 << DCLK3_VOP_SRC_SEL_SHIFT,
379 DCLK3_VOP_SRC_DIV_SHIFT = 0,
380 DCLK3_VOP_SRC_DIV_MASK = 0x7f << DCLK3_VOP_SRC_DIV_SHIFT,
381
382
383 CLK_AUX16MHZ_1_DIV_SHIFT = 8,
384 CLK_AUX16MHZ_1_DIV_MASK = 0xff << CLK_AUX16MHZ_1_DIV_SHIFT,
385 CLK_AUX16MHZ_0_DIV_SHIFT = 0,
386 CLK_AUX16MHZ_0_DIV_MASK = 0xff << CLK_AUX16MHZ_0_DIV_SHIFT,
387
388
389 PCLK_CENTER_ROOT_SEL_SHIFT = 6,
390 PCLK_CENTER_ROOT_SEL_MASK = 3 << PCLK_CENTER_ROOT_SEL_SHIFT,
391 PCLK_CENTER_ROOT_SEL_200M = 0,
392 PCLK_CENTER_ROOT_SEL_100M,
393 PCLK_CENTER_ROOT_SEL_50M,
394 PCLK_CENTER_ROOT_SEL_24M,
395 HCLK_CENTER_ROOT_SEL_SHIFT = 4,
396 HCLK_CENTER_ROOT_SEL_MASK = 3 << HCLK_CENTER_ROOT_SEL_SHIFT,
397 HCLK_CENTER_ROOT_SEL_400M = 0,
398 HCLK_CENTER_ROOT_SEL_200M,
399 HCLK_CENTER_ROOT_SEL_100M,
400 HCLK_CENTER_ROOT_SEL_24M,
401 ACLK_CENTER_LOW_ROOT_SEL_SHIFT = 2,
402 ACLK_CENTER_LOW_ROOT_SEL_MASK = 3 << ACLK_CENTER_LOW_ROOT_SEL_SHIFT,
403 ACLK_CENTER_LOW_ROOT_SEL_500M = 0,
404 ACLK_CENTER_LOW_ROOT_SEL_250M,
405 ACLK_CENTER_LOW_ROOT_SEL_100M,
406 ACLK_CENTER_LOW_ROOT_SEL_24M,
407 ACLK_CENTER_ROOT_SEL_SHIFT = 0,
408 ACLK_CENTER_ROOT_SEL_MASK = 3 << ACLK_CENTER_ROOT_SEL_SHIFT,
409 ACLK_CENTER_ROOT_SEL_700M = 0,
410 ACLK_CENTER_ROOT_SEL_400M,
411 ACLK_CENTER_ROOT_SEL_200M,
412 ACLK_CENTER_ROOT_SEL_24M,
413
414
415 CCLK_SDIO_SRC_SEL_SHIFT = 8,
416 CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
417 CCLK_SDIO_SRC_SEL_GPLL = 0,
418 CCLK_SDIO_SRC_SEL_CPLL,
419 CCLK_SDIO_SRC_SEL_24M,
420 CCLK_SDIO_SRC_DIV_SHIFT = 2,
421 CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
422
423
424 CLK_PCIE_PHY1_PLL_DIV_SHIFT = 6,
425 CLK_PCIE_PHY1_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY1_PLL_DIV_SHIFT,
426 CLK_PCIE_PHY0_PLL_DIV_SHIFT = 0,
427 CLK_PCIE_PHY0_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY0_PLL_DIV_SHIFT,
428
429
430 CLK_PCIE_PHY2_REF_SEL_SHIFT = 8,
431 CLK_PCIE_PHY2_REF_SEL_MASK = 1 << CLK_PCIE_PHY2_REF_SEL_SHIFT,
432 CLK_PCIE_PHY1_REF_SEL_SHIFT = 7,
433 CLK_PCIE_PHY1_REF_SEL_MASK = 1 << CLK_PCIE_PHY1_REF_SEL_SHIFT,
434 CLK_PCIE_PHY0_REF_SEL_SHIFT = 6,
435 CLK_PCIE_PHY0_REF_SEL_MASK = 1 << CLK_PCIE_PHY0_REF_SEL_SHIFT,
436 CLK_PCIE_PHY_REF_SEL_24M = 0,
437 CLK_PCIE_PHY_REF_SEL_PPLL,
438 CLK_PCIE_PHY2_PLL_DIV_SHIFT = 0,
439 CLK_PCIE_PHY2_PLL_DIV_MASK = 0x3f << CLK_PCIE_PHY2_PLL_DIV_SHIFT,
440
441
442 CLK_PMU1PWM_SEL_SHIFT = 9,
443 CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
444
445
446 CLK_I2C0_SEL_SHIFT = 6,
447 CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT,
448 CLK_I2C_SEL_200M = 0,
449 CLK_I2C_SEL_100M,
450};
451#endif
452
