LXR uboot/arch/arm/include/asm/arch-rockchip/sdram.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
   4 */
   5
   6#ifndef _ASM_ARCH_SDRAM_H
   7#define _ASM_ARCH_SDRAM_H
   8
   9enum {
  10        DDR4 = 0,
  11        DDR3 = 3,
  12        LPDDR2 = 5,
  13        LPDDR3 = 6,
  14        LPDDR4 = 7,
  15        LPDDR4X = 8,
  16        LPDDR5 = 9,
  17        DDR5 = 10,
  18        UNUSED = 0xFF
  19};
  20
  21/*
  22 * sys_reg2 bitfield struct
  23 * [31]         row_3_4_ch1
  24 * [30]         row_3_4_ch0
  25 * [29:28]      chinfo
  26 * [27]         rank_ch1
  27 * [26:25]      cs0_col_ch1
  28 * [24]         bk_ch1
  29 * [23:22]      low bits of cs0_row_ch1
  30 * [21:20]      low bits of cs1_row_ch1
  31 * [19:18]      bw_ch1
  32 * [17:16]      dbw_ch1
  33 * [15:13]      low bits of ddrtype
  34 * [12]         channelnum
  35 * [11]         low bit of rank_ch0
  36 * [10:9]       cs0_col_ch0
  37 * [8]          bk_ch0
  38 * [7:6]        low bits of cs0_row_ch0
  39 * [5:4]        low bits of cs1_row_ch0
  40 * [3:2]        bw_ch0
  41 * [1:0]        dbw_ch0
  42 */
  43#define SYS_REG_DDRTYPE_SHIFT           13
  44#define SYS_REG_DDRTYPE_MASK            7
  45#define SYS_REG_NUM_CH_SHIFT            12
  46#define SYS_REG_NUM_CH_MASK             1
  47#define SYS_REG_ROW_3_4_SHIFT(ch)       (30 + (ch))
  48#define SYS_REG_ROW_3_4_MASK            1
  49#define SYS_REG_CHINFO_SHIFT(ch)        (28 + (ch))
  50#define SYS_REG_RANK_SHIFT(ch)          (11 + (ch) * 16)
  51#define SYS_REG_RANK_MASK               1
  52#define SYS_REG_COL_SHIFT(ch)           (9 + (ch) * 16)
  53#define SYS_REG_COL_MASK                3
  54#define SYS_REG_BK_SHIFT(ch)            (8 + (ch) * 16)
  55#define SYS_REG_BK_MASK                 1
  56#define SYS_REG_CS0_ROW_SHIFT(ch)       (6 + (ch) * 16)
  57#define SYS_REG_CS0_ROW_MASK            3
  58#define SYS_REG_CS1_ROW_SHIFT(ch)       (4 + (ch) * 16)
  59#define SYS_REG_CS1_ROW_MASK            3
  60#define SYS_REG_BW_SHIFT(ch)            (2 + (ch) * 16)
  61#define SYS_REG_BW_MASK                 3
  62#define SYS_REG_DBW_SHIFT(ch)           ((ch) * 16)
  63#define SYS_REG_DBW_MASK                3
  64
  65/*
  66 * sys_reg3 bitfield struct
  67 * [31:28]      version
  68 * [16]         cs3_delta_row
  69 * [15]         cs2_delta_row
  70 * [14]         high bit of rank_ch0
  71 * [13:12]      high bits of ddrtype
  72 * [7]          high bit of cs0_row_ch1
  73 * [6]          high bit of cs1_row_ch1
  74 * [5]          high bit of cs0_row_ch0
  75 * [4]          high bit of cs1_row_ch0
  76 * [3:2]        cs1_col_ch1
  77 * [1:0]        cs1_col_ch0
  78 */
  79#define SYS_REG_VERSION_SHIFT                   28
  80#define SYS_REG_VERSION_MASK                    0xf
  81#define SYS_REG_EXTEND_DDRTYPE_SHIFT            12
  82#define SYS_REG_EXTEND_DDRTYPE_MASK             3
  83#define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch)        (5 + (ch) * 2)
  84#define SYS_REG_EXTEND_CS0_ROW_MASK             1
  85#define SYS_REG_EXTEND_CS1_ROW_SHIFT(ch)        (4 + (ch) * 2)
  86#define SYS_REG_EXTEND_CS1_ROW_MASK             1
  87#define SYS_REG_CS1_COL_SHIFT(ch)               (0 + (ch) * 2)
  88#define SYS_REG_CS1_COL_MASK                    3
  89
  90/* Get sdram size decode from reg */
  91size_t rockchip_sdram_size(phys_addr_t reg);
  92
  93/* Called by U-Boot board_init_r for Rockchip SoCs */
  94int dram_init(void);
  95
  96#endif
  97