LXR uboot/arch/arm/mach-sunxi/board.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   4 *
   5 * (C) Copyright 2007-2011
   6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7 * Tom Cubie <tangliang@allwinnertech.com>
   8 *
   9 * Some init for sunxi platform.
  10 */
  11
  12#include <common.h>
  13#include <cpu_func.h>
  14#include <init.h>
  15#include <log.h>
  16#include <mmc.h>
  17#include <i2c.h>
  18#include <serial.h>
  19#include <spl.h>
  20#include <asm/cache.h>
  21#include <asm/gpio.h>
  22#include <asm/io.h>
  23#include <asm/arch/clock.h>
  24#include <asm/arch/spl.h>
  25#include <asm/arch/sys_proto.h>
  26#include <asm/arch/timer.h>
  27#include <asm/arch/tzpc.h>
  28#include <asm/arch/mmc.h>
  29
  30#include <linux/compiler.h>
  31
  32struct fel_stash {
  33        uint32_t sp;
  34        uint32_t lr;
  35        uint32_t cpsr;
  36        uint32_t sctlr;
  37        uint32_t vbar;
  38};
  39
  40struct fel_stash fel_stash __section(".data");
  41
  42#ifdef CONFIG_ARM64
  43#include <asm/armv8/mmu.h>
  44
  45static struct mm_region sunxi_mem_map[] = {
  46        {
  47                /* SRAM, MMIO regions */
  48                .virt = 0x0UL,
  49                .phys = 0x0UL,
  50                .size = 0x40000000UL,
  51                .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  52                         PTE_BLOCK_NON_SHARE
  53        }, {
  54                /* RAM */
  55                .virt = 0x40000000UL,
  56                .phys = 0x40000000UL,
  57                .size = CONFIG_SUNXI_DRAM_MAX_SIZE,
  58                .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  59                         PTE_BLOCK_INNER_SHARE
  60        }, {
  61                /* List terminator */
  62                0,
  63        }
  64};
  65struct mm_region *mem_map = sunxi_mem_map;
  66
  67phys_size_t board_get_usable_ram_top(phys_size_t total_size)
  68{
  69        /* Some devices (like the EMAC) have a 32-bit DMA limit. */
  70        if (gd->ram_top > (1ULL << 32))
  71                return 1ULL << 32;
  72
  73        return gd->ram_top;
  74}
  75#endif /* CONFIG_ARM64 */
  76
  77#ifdef CONFIG_SPL_BUILD
  78static int gpio_init(void)
  79{
  80        __maybe_unused uint val;
  81#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  82#if defined(CONFIG_MACH_SUN4I) || \
  83    defined(CONFIG_MACH_SUN7I) || \
  84    defined(CONFIG_MACH_SUN8I_R40)
  85        /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  86        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  87        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  88#endif
  89#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || \
  90    defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I_R40) || \
  91    defined(CONFIG_MACH_SUN9I)
  92        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  93        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  94#else
  95        sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  96        sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  97#endif
  98        sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP);
  99#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
 100        sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
 101        sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
 102        sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
 103#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
 104                                 defined(CONFIG_MACH_SUN7I) || \
 105                                 defined(CONFIG_MACH_SUN8I_R40))
 106        sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
 107        sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 108        sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 109#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
 110        sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
 111        sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
 112        sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 113#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
 114        sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
 115        sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 116        sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 117#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
 118        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
 119        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
 120        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 121#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
 122        sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 123        sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 124        sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
 125#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
 126        sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
 127        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
 128        sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 129#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
 130        sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
 131        sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
 132        sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
 133#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
 134        sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
 135        sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
 136        sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
 137#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
 138        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
 139        sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
 140        sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 141#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
 142        sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
 143        sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
 144        sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 145#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 146        sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 147        sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 148        sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 149#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
 150        sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
 151        sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
 152        sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
 153#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 154        sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 155        sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 156        sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 157#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
 158        sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
 159        sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
 160        sunxi_gpio_set_pull(SUNXI_GPA(1), SUNXI_GPIO_PULL_UP);
 161#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
 162        sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
 163        sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
 164        sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 165#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
 166        sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
 167        sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 168        sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 169#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
 170                                !defined(CONFIG_MACH_SUN8I_R40)
 171        sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
 172        sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
 173        sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
 174#else
 175#error Unsupported console port number. Please fix pin mux settings in board.c
 176#endif
 177
 178#ifdef CONFIG_SUN50I_GEN_H6
 179        /* Update PIO power bias configuration by copy hardware detected value */
 180        val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 181        writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
 182        val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
 183        writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
 184#endif
 185
 186        return 0;
 187}
 188
 189static int spl_board_load_image(struct spl_image_info *spl_image,
 190                                struct spl_boot_device *bootdev)
 191{
 192        debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
 193        return_to_fel(fel_stash.sp, fel_stash.lr);
 194
 195        return 0;
 196}
 197SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
 198#endif /* CONFIG_SPL_BUILD */
 199
 200#define SUNXI_INVALID_BOOT_SOURCE       -1
 201
 202static int suniv_get_boot_source(void)
 203{
 204        /* Get the last function call from BootROM's stack. */
 205        u32 brom_call = *(u32 *)(uintptr_t)(fel_stash.sp - 4);
 206
 207        /* translate SUNIV BootROM stack to standard SUNXI boot sources */
 208        switch (brom_call) {
 209        case SUNIV_BOOTED_FROM_MMC0:
 210                return SUNXI_BOOTED_FROM_MMC0;
 211        case SUNIV_BOOTED_FROM_SPI:
 212                return SUNXI_BOOTED_FROM_SPI;
 213        case SUNIV_BOOTED_FROM_MMC1:
 214                return SUNXI_BOOTED_FROM_MMC2;
 215        /* SPI NAND is not supported yet. */
 216        case SUNIV_BOOTED_FROM_NAND:
 217                return SUNXI_INVALID_BOOT_SOURCE;
 218        }
 219        /* If we get here something went wrong try to boot from FEL.*/
 220        printf("Unknown boot source from BROM: 0x%x\n", brom_call);
 221        return SUNXI_INVALID_BOOT_SOURCE;
 222}
 223
 224static int sunxi_egon_valid(struct boot_file_head *egon_head)
 225{
 226        return !memcmp(egon_head->magic, BOOT0_MAGIC, 8); /* eGON.BT0 */
 227}
 228
 229static int sunxi_toc0_valid(struct toc0_main_info *toc0_info)
 230{
 231        return !memcmp(toc0_info->name, TOC0_MAIN_INFO_NAME, 8); /* TOC0.GLH */
 232}
 233
 234static int sunxi_get_boot_source(void)
 235{
 236        struct boot_file_head *egon_head = (void *)SPL_ADDR;
 237        struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
 238
 239        /*
 240         * On the ARMv5 SoCs, the SPL header in SRAM is overwritten by the
 241         * exception vectors in U-Boot proper, so we won't find any
 242         * information there. Also the FEL stash is only valid in the SPL,
 243         * so we can't use that either. So if this is called from U-Boot
 244         * proper, just return MMC0 as a placeholder, for now.
 245         */
 246        if (IS_ENABLED(CONFIG_MACH_SUNIV) &&
 247            !IS_ENABLED(CONFIG_SPL_BUILD))
 248                return SUNXI_BOOTED_FROM_MMC0;
 249
 250        if (IS_ENABLED(CONFIG_MACH_SUNIV))
 251                return suniv_get_boot_source();
 252        if (sunxi_egon_valid(egon_head))
 253                return readb(&egon_head->boot_media);
 254        if (sunxi_toc0_valid(toc0_info))
 255                return readb(&toc0_info->platform[0]);
 256
 257        /* Not a valid image, so we must have been booted via FEL. */
 258        return SUNXI_INVALID_BOOT_SOURCE;
 259}
 260
 261/* The sunxi internal brom will try to loader external bootloader
 262 * from mmc0, nand flash, mmc2.
 263 */
 264uint32_t sunxi_get_boot_device(void)
 265{
 266        int boot_source = sunxi_get_boot_source();
 267
 268        /*
 269         * When booting from the SD card or NAND memory, the "eGON.BT0"
 270         * signature is expected to be found in memory at the address 0x0004
 271         * (see the "mksunxiboot" tool, which generates this header).
 272         *
 273         * When booting in the FEL mode over USB, this signature is patched in
 274         * memory and replaced with something else by the 'fel' tool. This other
 275         * signature is selected in such a way, that it can't be present in a
 276         * valid bootable SD card image (because the BROM would refuse to
 277         * execute the SPL in this case).
 278         *
 279         * This checks for the signature and if it is not found returns to
 280         * the FEL code in the BROM to wait and receive the main u-boot
 281         * binary over USB. If it is found, it determines where SPL was
 282         * read from.
 283         */
 284        switch (boot_source) {
 285        case SUNXI_INVALID_BOOT_SOURCE:
 286                return BOOT_DEVICE_BOARD;
 287        case SUNXI_BOOTED_FROM_MMC0:
 288        case SUNXI_BOOTED_FROM_MMC0_HIGH:
 289                return BOOT_DEVICE_MMC1;
 290        case SUNXI_BOOTED_FROM_NAND:
 291                return BOOT_DEVICE_NAND;
 292        case SUNXI_BOOTED_FROM_MMC2:
 293        case SUNXI_BOOTED_FROM_MMC2_HIGH:
 294                return BOOT_DEVICE_MMC2;
 295        case SUNXI_BOOTED_FROM_SPI:
 296                return BOOT_DEVICE_SPI;
 297        }
 298
 299        panic("Unknown boot source %d\n", boot_source);
 300        return -1;              /* Never reached */
 301}
 302
 303#ifdef CONFIG_SPL_BUILD
 304uint32_t sunxi_get_spl_size(void)
 305{
 306        struct boot_file_head *egon_head = (void *)SPL_ADDR;
 307        struct toc0_main_info *toc0_info = (void *)SPL_ADDR;
 308
 309        if (sunxi_egon_valid(egon_head))
 310                return readl(&egon_head->length);
 311        if (sunxi_toc0_valid(toc0_info))
 312                return readl(&toc0_info->length);
 313
 314        /* Not a valid image, so use the default U-Boot offset. */
 315        return 0;
 316}
 317
 318/*
 319 * The eGON SPL image can be located at 8KB or at 128KB into an SD card or
 320 * an eMMC device. The boot source has bit 4 set in the latter case.
 321 * By adding 120KB to the normal offset when booting from a "high" location
 322 * we can support both cases.
 323 * Also U-Boot proper is located at least 32KB after the SPL, but will
 324 * immediately follow the SPL if that is bigger than that.
 325 */
 326unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
 327                                           unsigned long raw_sect)
 328{
 329        unsigned long spl_size = sunxi_get_spl_size();
 330        unsigned long sector;
 331
 332        sector = max(raw_sect, spl_size / 512);
 333
 334        switch (sunxi_get_boot_source()) {
 335        case SUNXI_BOOTED_FROM_MMC0_HIGH:
 336        case SUNXI_BOOTED_FROM_MMC2_HIGH:
 337                sector += (128 - 8) * 2;
 338                break;
 339        }
 340
 341        return sector;
 342}
 343
 344u32 spl_boot_device(void)
 345{
 346        return sunxi_get_boot_device();
 347}
 348
 349__weak void sunxi_sram_init(void)
 350{
 351}
 352
 353/*
 354 * When booting from an eMMC boot partition, the SPL puts the same boot
 355 * source code into SRAM A1 as when loading the SPL from the normal
 356 * eMMC user data partition: 0x2. So to know where we have been loaded
 357 * from, we repeat the BROM algorithm here: checking for a valid eGON boot
 358 * image at offset 0 of a (potentially) selected boot partition.
 359 * If any of the conditions is not met, it must have been the eMMC user
 360 * data partition.
 361 */
 362static bool sunxi_valid_emmc_boot(struct mmc *mmc)
 363{
 364        struct blk_desc *bd = mmc_get_blk_desc(mmc);
 365        u32 *buffer = (void *)(uintptr_t)CONFIG_TEXT_BASE;
 366        struct boot_file_head *egon_head = (void *)buffer;
 367        struct toc0_main_info *toc0_info = (void *)buffer;
 368        int bootpart = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 369        uint32_t spl_size, emmc_checksum, chksum = 0;
 370        ulong count;
 371
 372        /* The BROM requires BOOT_ACK to be enabled. */
 373        if (!EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config))
 374                return false;
 375
 376        /*
 377         * The BOOT_BUS_CONDITION register must be 4-bit SDR, with (0x09)
 378         * or without (0x01) high speed timings.
 379         */
 380        if ((mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x01 &&
 381            (mmc->ext_csd[EXT_CSD_BOOT_BUS_WIDTH] & 0x1b) != 0x09)
 382                return false;
 383
 384        /* Partition 0 is the user data partition, bootpart must be 1 or 2. */
 385        if (bootpart != 1 && bootpart != 2)
 386                return false;
 387
 388        /* Failure to switch to the boot partition is fatal. */
 389        if (mmc_switch_part(mmc, bootpart))
 390                return false;
 391
 392        /* Read the first block to do some sanity checks on the eGON header. */
 393        count = blk_dread(bd, 0, 1, buffer);
 394        if (count != 1)
 395                return false;
 396
 397        if (sunxi_egon_valid(egon_head))
 398                spl_size = egon_head->length;
 399        else if (sunxi_toc0_valid(toc0_info))
 400                spl_size = toc0_info->length;
 401        else
 402                return false;
 403
 404        /* Read the rest of the SPL now we know it's halfway sane. */
 405        count = blk_dread(bd, 1, DIV_ROUND_UP(spl_size, bd->blksz) - 1,
 406                          buffer + bd->blksz / 4);
 407
 408        /* Save the checksum and replace it with the "stamp value". */
 409        emmc_checksum = buffer[3];
 410        buffer[3] = 0x5f0a6c39;
 411
 412        /* The checksum is a simple ignore-carry addition of all words. */
 413        for (count = 0; count < spl_size / 4; count++)
 414                chksum += buffer[count];
 415
 416        debug("eMMC boot part SPL checksum: stored: 0x%08x, computed: 0x%08x\n",
 417               emmc_checksum, chksum);
 418
 419        return emmc_checksum == chksum;
 420}
 421
 422u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
 423{
 424        static u32 result = ~0;
 425
 426        if (result != ~0)
 427                return result;
 428
 429        result = MMCSD_MODE_RAW;
 430        if (!IS_SD(mmc) && IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
 431                if (sunxi_valid_emmc_boot(mmc))
 432                        result = MMCSD_MODE_EMMCBOOT;
 433                else
 434                        mmc_switch_part(mmc, 0);
 435        }
 436
 437        debug("%s(): %s part\n", __func__,
 438              result == MMCSD_MODE_RAW ? "user" : "boot");
 439
 440        return result;
 441}
 442
 443void board_init_f(ulong dummy)
 444{
 445        sunxi_sram_init();
 446
 447#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 448        /* Enable non-secure access to some peripherals */
 449        tzpc_init();
 450#endif
 451
 452        clock_init();
 453        timer_init();
 454        gpio_init();
 455
 456        spl_init();
 457        preloader_console_init();
 458
 459#if CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
 460        /* Needed early by sunxi_board_init if PMU is enabled */
 461        i2c_init_board();
 462        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 463#endif
 464        sunxi_board_init();
 465}
 466#endif /* CONFIG_SPL_BUILD */
 467
 468#if !CONFIG_IS_ENABLED(SYSRESET)
 469void reset_cpu(void)
 470{
 471#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
 472        static const struct sunxi_wdog *wdog =
 473                 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 474
 475        /* Set the watchdog for its shortest interval (.5s) and wait */
 476        writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 477        writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 478
 479        while (1) {
 480                /* sun5i sometimes gets stuck without this */
 481                writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 482        }
 483#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
 484#if defined(CONFIG_MACH_SUN50I_H6)
 485        /* WDOG is broken for some H6 rev. use the R_WDOG instead */
 486        static const struct sunxi_wdog *wdog =
 487                (struct sunxi_wdog *)SUNXI_R_WDOG_BASE;
 488#else
 489        static const struct sunxi_wdog *wdog =
 490                ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 491#endif
 492        /* Set the watchdog for its shortest interval (.5s) and wait */
 493        writel(WDT_CFG_RESET, &wdog->cfg);
 494        writel(WDT_MODE_EN, &wdog->mode);
 495        writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 496        while (1) { }
 497#endif
 498}
 499#endif /* CONFIG_SYSRESET */
 500
 501#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
 502void enable_caches(void)
 503{
 504        /* Enable D-cache. I-cache is already enabled in start.S */
 505        dcache_enable();
 506}
 507#endif
 508