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9#ifndef __CVMX_FPA1_HW_H__
10#define __CVMX_FPA1_HW_H__
11
12#include "cvmx-scratch.h"
13#include "cvmx-fpa-defs.h"
14#include "cvmx-fpa3.h"
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16
17typedef int cvmx_fpa1_pool_t;
18
19#define CVMX_FPA1_NUM_POOLS 8
20#define CVMX_FPA1_INVALID_POOL ((cvmx_fpa1_pool_t)-1)
21#define CVMX_FPA1_NAME_SIZE 16
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26typedef union {
27 u64 u64;
28 struct {
29 u64 scraddr : 8;
30 u64 len : 8;
31 u64 did : 8;
32 u64 addr : 40;
33 } s;
34} cvmx_fpa1_iobdma_data_t;
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44cvmx_fpa1_pool_t cvmx_fpa1_reserve_pool(cvmx_fpa1_pool_t pool);
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51int cvmx_fpa1_release_pool(cvmx_fpa1_pool_t pool);
52
53static inline void cvmx_fpa1_free(void *ptr, cvmx_fpa1_pool_t pool, u64 num_cache_lines)
54{
55 cvmx_addr_t newptr;
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57 newptr.u64 = cvmx_ptr_to_phys(ptr);
58 newptr.sfilldidspace.didspace = CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
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62
63 CVMX_SYNCWS;
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65 cvmx_write_io(newptr.u64, num_cache_lines);
66}
67
68static inline void cvmx_fpa1_free_nosync(void *ptr, cvmx_fpa1_pool_t pool,
69 unsigned int num_cache_lines)
70{
71 cvmx_addr_t newptr;
72
73 newptr.u64 = cvmx_ptr_to_phys(ptr);
74 newptr.sfilldidspace.didspace = CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
75
76 asm volatile("" : : : "memory");
77
78 cvmx_write_io(newptr.u64, num_cache_lines);
79}
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84
85static inline void cvmx_fpa1_enable(void)
86{
87 cvmx_fpa_ctl_status_t status;
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89 status.u64 = csr_rd(CVMX_FPA_CTL_STATUS);
90 if (status.s.enb) {
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96 return;
97 }
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99 status.u64 = 0;
100 status.s.enb = 1;
101 csr_wr(CVMX_FPA_CTL_STATUS, status.u64);
102}
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108static inline void cvmx_fpa1_disable(void)
109{
110 cvmx_fpa_ctl_status_t status;
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112 if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1))
113 return;
114
115 status.u64 = csr_rd(CVMX_FPA_CTL_STATUS);
116 status.s.reset = 1;
117 csr_wr(CVMX_FPA_CTL_STATUS, status.u64);
118}
119
120static inline void *cvmx_fpa1_alloc(cvmx_fpa1_pool_t pool)
121{
122 u64 address;
123
124 for (;;) {
125 address = csr_rd(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
126 if (cvmx_likely(address)) {
127 return cvmx_phys_to_ptr(address);
128 } else {
129 if (csr_rd(CVMX_FPA_QUEX_AVAILABLE(pool)) > 0)
130 udelay(50);
131 else
132 return NULL;
133 }
134 }
135}
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148static inline void cvmx_fpa1_async_alloc(u64 scr_addr, cvmx_fpa1_pool_t pool)
149{
150 cvmx_fpa1_iobdma_data_t data;
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155 data.u64 = 0ull;
156 data.s.scraddr = scr_addr >> 3;
157 data.s.len = 1;
158 data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
159 data.s.addr = 0;
160
161 cvmx_scratch_write64(scr_addr, 0ull);
162 CVMX_SYNCW;
163 cvmx_send_single(data.u64);
164}
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178static inline void *cvmx_fpa1_async_alloc_finish(u64 scr_addr, cvmx_fpa1_pool_t pool)
179{
180 u64 address;
181
182 CVMX_SYNCIOBDMA;
183
184 address = cvmx_scratch_read64(scr_addr);
185 if (cvmx_likely(address))
186 return cvmx_phys_to_ptr(address);
187 else
188 return cvmx_fpa1_alloc(pool);
189}
190
191static inline u64 cvmx_fpa1_get_available(cvmx_fpa1_pool_t pool)
192{
193 return csr_rd(CVMX_FPA_QUEX_AVAILABLE(pool));
194}
195
196#endif
197