LXR uboot/arch/powerpc/cpu/mpc85xx/p1021

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <config.h>
   7#include <common.h>
   8#include <log.h>
   9#include <asm/io.h>
  10#include <asm/immap_85xx.h>
  11#include <asm/fsl_serdes.h>
  12#include <linux/delay.h>
  13
  14typedef struct serdes_85xx {
  15        u32     srdscr0;        /* 0x00 - SRDS Control Register 0 */
  16        u32     srdscr1;        /* 0x04 - SRDS Control Register 1 */
  17        u32     srdscr2;        /* 0x08 - SRDS Control Register 2 */
  18        u32     srdscr3;        /* 0x0C - SRDS Control Register 3 */
  19        u32     srdscr4;        /* 0x10 - SRDS Control Register 4 */
  20} serdes_85xx_t;
  21#define FSL_SRDSCR3_EIC0(x)     (((x) & 0x1f) << 8)
  22#define FSL_SRDSCR3_EIC0_MASK   FSL_SRDSCR3_EIC0(0x1f)
  23#define FSL_SRDSCR3_EIC1(x)     (((x) & 0x1f) << 0)
  24#define FSL_SRDSCR3_EIC1_MASK   FSL_SRDSCR3_EIC1(0x1f)
  25#define FSL_SRDSCR4_EIC2(x)     (((x) & 0x1f) << 8)
  26#define FSL_SRDSCR4_EIC2_MASK   FSL_SRDSCR4_EIC2(0x1f)
  27#define FSL_SRDSCR4_EIC3(x)     (((x) & 0x1f) << 0)
  28#define FSL_SRDSCR4_EIC3_MASK   FSL_SRDSCR4_EIC3(0x1f)
  29#define EIC_PCIE        0x13
  30#define EIC_SGMII       0x04
  31
  32#define SRDS1_MAX_LANES         4
  33
  34static u32 serdes1_prtcl_map;
  35
  36static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
  37        [0x0] = {PCIE1, NONE, NONE, NONE},
  38        [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1},
  39        [0xe] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
  40        [0xf] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
  41};
  42
  43int is_serdes_configured(enum srds_prtcl prtcl)
  44{
  45        if (!(serdes1_prtcl_map & (1 << NONE)))
  46                fsl_serdes_init();
  47
  48        return (1 << prtcl) & serdes1_prtcl_map;
  49}
  50
  51void fsl_serdes_init(void)
  52{
  53        ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
  54        serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
  55
  56        u32 pordevsr = in_be32(&gur->pordevsr);
  57        u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  58                                MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  59        int lane;
  60        u32 mask, val;
  61
  62        if (serdes1_prtcl_map & (1 << NONE))
  63                return;
  64
  65        debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
  66
  67        if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
  68                printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
  69                return;
  70        }
  71
  72        for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
  73                enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
  74                serdes1_prtcl_map |= (1 << lane_prtcl);
  75        }
  76
  77        /* Set the first bit to indicate serdes has been initialized */
  78        serdes1_prtcl_map |= (1 << NONE);
  79
  80        /* Init SERDES Receiver electrical idle detection control for PCIe */
  81
  82        /* Lane 0 is always PCIe 1 */
  83        mask = FSL_SRDSCR3_EIC0_MASK;
  84        val = FSL_SRDSCR3_EIC0(EIC_PCIE);
  85
  86        /* Lane 1 */
  87        if ((serdes1_cfg_tbl[srds_cfg][1] == PCIE1) ||
  88            (serdes1_cfg_tbl[srds_cfg][1] == PCIE2)) {
  89                mask |= FSL_SRDSCR3_EIC1_MASK;
  90                val |= FSL_SRDSCR3_EIC1(EIC_PCIE);
  91        }
  92
  93        /* Handle lanes 0 & 1 */
  94        clrsetbits_be32(&serdes->srdscr3, mask, val);
  95
  96        /* Handle lanes 2 & 3 */
  97        if (srds_cfg == 0x6) {
  98                mask = FSL_SRDSCR4_EIC2_MASK | FSL_SRDSCR4_EIC3_MASK;
  99                val = FSL_SRDSCR4_EIC2(EIC_PCIE) | FSL_SRDSCR4_EIC3(EIC_PCIE);
 100                clrsetbits_be32(&serdes->srdscr4, mask, val);
 101        }
 102
 103        /* 100 ms delay */
 104        udelay(100000);
 105}
 106