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18#include <common.h>
19#include <dm.h>
20#include <init.h>
21#include <net.h>
22#include <asm/global_data.h>
23#include <asm/io.h>
24#include <asm/arch/at91sam9_sdramc.h>
25#include <asm/arch/at91sam9260_matrix.h>
26#include <asm/arch/at91sam9_smc.h>
27#include <asm/arch/at91_common.h>
28#include <asm/arch/atmel_serial.h>
29#include <asm/arch/at91_spi.h>
30#include <spi.h>
31#include <asm/arch/clk.h>
32#include <asm/arch/gpio.h>
33#include <asm/gpio.h>
34#include <watchdog.h>
35# include <net.h>
36#ifndef CONFIG_DM_ETH
37# include <netdev.h>
38#endif
39#include <g_dnl.h>
40
41DECLARE_GLOBAL_DATA_PTR;
42
43static void smartweb_request_gpio(void)
44{
45 gpio_request(CFG_SYS_NAND_ENABLE_PIN, "nand ena");
46 gpio_request(CFG_SYS_NAND_READY_PIN, "nand rdy");
47 gpio_request(AT91_PIN_PA26, "ena PHY");
48}
49
50static void smartweb_nand_hw_init(void)
51{
52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 unsigned long csa;
55
56
57 csa = readl(&matrix->ebicsa);
58 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
59 writel(csa, &matrix->ebicsa);
60
61
62 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
63 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
64 &smc->cs[3].setup);
65 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
66 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
67 &smc->cs[3].pulse);
68 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
69 &smc->cs[3].cycle);
70 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
71 AT91_SMC_MODE_TDF_CYCLE(2),
72 &smc->cs[3].mode);
73
74
75 at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
76
77
78 at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
79}
80
81static void smartweb_macb_hw_init(void)
82{
83 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
84
85
86 at91_set_gpio_output(AT91_PIN_PA26, 0);
87
88
89
90
91
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95
96
97
98
99 writel(pin_to_mask(AT91_PIN_PA14) |
100 pin_to_mask(AT91_PIN_PA15) |
101 pin_to_mask(AT91_PIN_PA17) |
102 pin_to_mask(AT91_PIN_PA25) |
103 pin_to_mask(AT91_PIN_PA26) |
104 pin_to_mask(AT91_PIN_PA28) |
105 pin_to_mask(AT91_PIN_PA29),
106 &pioa->pudr);
107
108 at91_phy_reset();
109
110
111 writel(pin_to_mask(AT91_PIN_PA14) |
112 pin_to_mask(AT91_PIN_PA15) |
113 pin_to_mask(AT91_PIN_PA17) |
114 pin_to_mask(AT91_PIN_PA25) |
115 pin_to_mask(AT91_PIN_PA26) |
116 pin_to_mask(AT91_PIN_PA28) |
117 pin_to_mask(AT91_PIN_PA29),
118 &pioa->puer);
119
120
121 at91_macb_hw_init();
122}
123
124#ifdef CONFIG_USB_GADGET_AT91
125#include <linux/usb/at91_udc.h>
126
127void at91_udp_hw_init(void)
128{
129
130 at91_pllb_clk_enable(get_pllb_init());
131
132
133 at91_periph_clk_enable(ATMEL_ID_UDP);
134
135 at91_system_clk_enable(AT91SAM926x_PMC_UDP);
136}
137
138struct at91_udc_data board_udc_data = {
139 .baseaddr = ATMEL_BASE_UDP0,
140};
141#endif
142
143int board_early_init_f(void)
144{
145
146 at91_seriald_hw_init();
147 smartweb_request_gpio();
148 return 0;
149}
150
151int board_init(void)
152{
153 smartweb_request_gpio();
154
155 at91_set_gpio_output(AT91_PIN_PC6, 0);
156 at91_set_gpio_output(AT91_PIN_PC7, 1);
157
158 at91_set_gpio_output(AT91_PIN_PC8, 0);
159 at91_set_gpio_output(AT91_PIN_PC9, 0);
160
161 at91_set_gpio_output(AT91_PIN_PC10, 0);
162 at91_set_gpio_output(AT91_PIN_PC11, 1);
163
164#ifdef CONFIG_USB_GADGET_AT91
165 at91_udp_hw_init();
166 at91_udc_probe(&board_udc_data);
167#endif
168
169
170 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
171
172 smartweb_nand_hw_init();
173 smartweb_macb_hw_init();
174 return 0;
175}
176
177int dram_init(void)
178{
179 gd->ram_size = get_ram_size(
180 (void *)CFG_SYS_SDRAM_BASE,
181 CFG_SYS_SDRAM_SIZE);
182 return 0;
183}
184
185#ifndef CONFIG_DM_ETH
186#ifdef CONFIG_MACB
187int board_eth_init(struct bd_info *bis)
188{
189 return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
190}
191#endif
192#endif
193
194#if defined(CONFIG_SPL_BUILD)
195#include <spl.h>
196#include <nand.h>
197#include <spi_flash.h>
198
199void matrix_init(void)
200{
201 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
202
203 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
204 | AT91_MATRIX_SLOT_CYCLE_(0x40),
205 &mat->scfg[3]);
206}
207
208void at91_spl_board_init(void)
209{
210 smartweb_request_gpio();
211
212 at91_set_gpio_output(AT91_PIN_PC6, 1);
213 at91_set_gpio_output(AT91_PIN_PC7, 1);
214
215 at91_set_gpio_output(AT91_PIN_PC8, 1);
216 at91_set_gpio_output(AT91_PIN_PC9, 1);
217
218 at91_set_gpio_output(AT91_PIN_PC10, 0);
219 at91_set_gpio_output(AT91_PIN_PC11, 1);
220
221 smartweb_nand_hw_init();
222 at91_set_gpio_input(AT91_PIN_PA28, 1);
223 at91_set_gpio_input(AT91_PIN_PA29, 1);
224
225
226 if (at91_get_gpio_value(AT91_PIN_PA28) == 0 &&
227 at91_get_gpio_value(AT91_PIN_PA29) == 0) {
228 smartweb_nand_hw_init();
229 nand_init();
230 spl_nand_erase_one(0, 0);
231 }
232}
233
234#define SDRAM_BASE_CONF (AT91_SDRAMC_NC_9 | AT91_SDRAMC_NR_13 \
235 | AT91_SDRAMC_CAS_2 \
236 | AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
237 | AT91_SDRAMC_TWR_VAL(2) | AT91_SDRAMC_TRC_VAL(7) \
238 | AT91_SDRAMC_TRP_VAL(2) | AT91_SDRAMC_TRCD_VAL(2) \
239 | AT91_SDRAMC_TRAS_VAL(5) | AT91_SDRAMC_TXSR_VAL(8))
240
241void mem_init(void)
242{
243 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
244 struct at91_port *port = (struct at91_port *)ATMEL_BASE_PIOC;
245 struct sdramc_reg setting;
246
247 setting.cr = SDRAM_BASE_CONF;
248 setting.mdr = AT91_SDRAMC_MD_SDRAM;
249 setting.tr = (CFG_SYS_MASTER_CLOCK * 7) / 1000000;
250
251
252
253
254
255
256 writel(0xffff0000, &port->pdr);
257
258 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC, &ma->ebicsa);
259 sdramc_initialize(ATMEL_BASE_CS1, &setting);
260}
261#endif
262
263int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
264{
265 g_dnl_set_serialnumber("1");
266 return 0;
267}
268
