uboot/drivers/ata/dwc_ahsata.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   4 * Terry Lv <r65388@freescale.com>
   5 */
   6
   7#include <common.h>
   8#include <ahci.h>
   9#include <blk.h>
  10#include <cpu_func.h>
  11#include <dm.h>
  12#include <dwc_ahsata.h>
  13#include <fis.h>
  14#include <libata.h>
  15#include <log.h>
  16#include <malloc.h>
  17#include <memalign.h>
  18#include <part.h>
  19#include <sata.h>
  20#include <asm/cache.h>
  21#include <asm/io.h>
  22#include <asm/arch/clock.h>
  23#include <asm/arch/sys_proto.h>
  24#include <asm/mach-imx/sata.h>
  25#include <linux/bitops.h>
  26#include <linux/ctype.h>
  27#include <linux/delay.h>
  28#include <linux/errno.h>
  29#include "dwc_ahsata_priv.h"
  30
  31struct sata_port_regs {
  32        u32 clb;
  33        u32 clbu;
  34        u32 fb;
  35        u32 fbu;
  36        u32 is;
  37        u32 ie;
  38        u32 cmd;
  39        u32 res1[1];
  40        u32 tfd;
  41        u32 sig;
  42        u32 ssts;
  43        u32 sctl;
  44        u32 serr;
  45        u32 sact;
  46        u32 ci;
  47        u32 sntf;
  48        u32 res2[1];
  49        u32 dmacr;
  50        u32 res3[1];
  51        u32 phycr;
  52        u32 physr;
  53};
  54
  55struct sata_host_regs {
  56        u32 cap;
  57        u32 ghc;
  58        u32 is;
  59        u32 pi;
  60        u32 vs;
  61        u32 ccc_ctl;
  62        u32 ccc_ports;
  63        u32 res1[2];
  64        u32 cap2;
  65        u32 res2[30];
  66        u32 bistafr;
  67        u32 bistcr;
  68        u32 bistfctr;
  69        u32 bistsr;
  70        u32 bistdecr;
  71        u32 res3[2];
  72        u32 oobr;
  73        u32 res4[8];
  74        u32 timer1ms;
  75        u32 res5[1];
  76        u32 gparam1r;
  77        u32 gparam2r;
  78        u32 pparamr;
  79        u32 testr;
  80        u32 versionr;
  81        u32 idr;
  82};
  83
  84#define MAX_DATA_BYTES_PER_SG  (4 * 1024 * 1024)
  85#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  86
  87#define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  88
  89static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  90{
  91        return base + 0x100 + (port * 0x80);
  92}
  93
  94static int waiting_for_cmd_completed(u8 *offset,
  95                                        int timeout_msec,
  96                                        u32 sign)
  97{
  98        int i;
  99        u32 status;
 100
 101        for (i = 0;
 102                ((status = readl(offset)) & sign) && i < timeout_msec;
 103                ++i)
 104                mdelay(1);
 105
 106        return (i < timeout_msec) ? 0 : -1;
 107}
 108
 109static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
 110{
 111        struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 112
 113        writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
 114        writel(0x02060b14, &host_mmio->oobr);
 115
 116        return 0;
 117}
 118
 119static int ahci_host_init(struct ahci_uc_priv *uc_priv)
 120{
 121        u32 tmp, cap_save, num_ports;
 122        int i, j, timeout = 1000;
 123        struct sata_port_regs *port_mmio = NULL;
 124        struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 125        int clk = mxc_get_clock(MXC_SATA_CLK);
 126
 127        cap_save = readl(&host_mmio->cap);
 128        cap_save |= SATA_HOST_CAP_SSS;
 129
 130        /* global controller reset */
 131        tmp = readl(&host_mmio->ghc);
 132        if ((tmp & SATA_HOST_GHC_HR) == 0)
 133                writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
 134
 135        while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
 136                ;
 137
 138        if (timeout <= 0) {
 139                debug("controller reset failed (0x%x)\n", tmp);
 140                return -1;
 141        }
 142
 143        /* Set timer 1ms */
 144        writel(clk / 1000, &host_mmio->timer1ms);
 145
 146        ahci_setup_oobr(uc_priv, 0);
 147
 148        writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
 149        writel(cap_save, &host_mmio->cap);
 150        num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
 151        writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
 152
 153        /*
 154         * Determine which Ports are implemented by the DWC_ahsata,
 155         * by reading the PI register. This bit map value aids the
 156         * software to determine how many Ports are available and
 157         * which Port registers need to be initialized.
 158         */
 159        uc_priv->cap = readl(&host_mmio->cap);
 160        uc_priv->port_map = readl(&host_mmio->pi);
 161
 162        /* Determine how many command slots the HBA supports */
 163        uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
 164
 165        debug("cap 0x%x  port_map 0x%x  n_ports %d\n",
 166                uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
 167
 168        for (i = 0; i < uc_priv->n_ports; i++) {
 169                uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
 170                port_mmio = uc_priv->port[i].port_mmio;
 171
 172                /* Ensure that the DWC_ahsata is in idle state */
 173                tmp = readl(&port_mmio->cmd);
 174
 175                /*
 176                 * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
 177                 * are all cleared, the Port is in an idle state.
 178                 */
 179                if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
 180                        SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
 181
 182                        /*
 183                         * System software places a Port into the idle state by
 184                         * clearing P#CMD.ST and waiting for P#CMD.CR to return
 185                         * 0 when read.
 186                         */
 187                        tmp &= ~SATA_PORT_CMD_ST;
 188                        writel_with_flush(tmp, &port_mmio->cmd);
 189
 190                        /*
 191                         * spec says 500 msecs for each bit, so
 192                         * this is slightly incorrect.
 193                         */
 194                        mdelay(500);
 195
 196                        timeout = 1000;
 197                        while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
 198                                && --timeout)
 199                                ;
 200
 201                        if (timeout <= 0) {
 202                                debug("port reset failed (0x%x)\n", tmp);
 203                                return -1;
 204                        }
 205                }
 206
 207                /* Spin-up device */
 208                tmp = readl(&port_mmio->cmd);
 209                writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
 210
 211                /* Wait for spin-up to finish */
 212                timeout = 1000;
 213                while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
 214                        && --timeout)
 215                        ;
 216                if (timeout <= 0) {
 217                        debug("Spin-Up can't finish!\n");
 218                        return -1;
 219                }
 220
 221                for (j = 0; j < 100; ++j) {
 222                        mdelay(10);
 223                        tmp = readl(&port_mmio->ssts);
 224                        if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
 225                                ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
 226                                break;
 227                }
 228
 229                /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
 230                timeout = 1000;
 231                while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
 232                        && --timeout)
 233                        ;
 234                if (timeout <= 0) {
 235                        debug("Can't find DIAG_X set!\n");
 236                        return -1;
 237                }
 238
 239                /*
 240                 * For each implemented Port, clear the P#SERR
 241                 * register, by writing ones to each implemented\
 242                 * bit location.
 243                 */
 244                tmp = readl(&port_mmio->serr);
 245                debug("P#SERR 0x%x\n",
 246                                tmp);
 247                writel(tmp, &port_mmio->serr);
 248
 249                /* Ack any pending irq events for this port */
 250                tmp = readl(&host_mmio->is);
 251                debug("IS 0x%x\n", tmp);
 252                if (tmp)
 253                        writel(tmp, &host_mmio->is);
 254
 255                writel(1 << i, &host_mmio->is);
 256
 257                /* set irq mask (enables interrupts) */
 258                writel(DEF_PORT_IRQ, &port_mmio->ie);
 259
 260                /* register linkup ports */
 261                tmp = readl(&port_mmio->ssts);
 262                debug("Port %d status: 0x%x\n", i, tmp);
 263                if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
 264                        uc_priv->link_port_map |= (0x01 << i);
 265        }
 266
 267        tmp = readl(&host_mmio->ghc);
 268        debug("GHC 0x%x\n", tmp);
 269        writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
 270        tmp = readl(&host_mmio->ghc);
 271        debug("GHC 0x%x\n", tmp);
 272
 273        return 0;
 274}
 275
 276static void ahci_print_info(struct ahci_uc_priv *uc_priv)
 277{
 278        struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 279        u32 vers, cap, impl, speed;
 280        const char *speed_s;
 281        const char *scc_s;
 282
 283        vers = readl(&host_mmio->vs);
 284        cap = uc_priv->cap;
 285        impl = uc_priv->port_map;
 286
 287        speed = (cap & SATA_HOST_CAP_ISS_MASK)
 288                >> SATA_HOST_CAP_ISS_OFFSET;
 289        if (speed == 1)
 290                speed_s = "1.5";
 291        else if (speed == 2)
 292                speed_s = "3";
 293        else
 294                speed_s = "?";
 295
 296        scc_s = "SATA";
 297
 298        printf("AHCI %02x%02x.%02x%02x "
 299                "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
 300                (vers >> 24) & 0xff,
 301                (vers >> 16) & 0xff,
 302                (vers >> 8) & 0xff,
 303                vers & 0xff,
 304                ((cap >> 8) & 0x1f) + 1,
 305                (cap & 0x1f) + 1,
 306                speed_s,
 307                impl,
 308                scc_s);
 309
 310        printf("flags: "
 311                "%s%s%s%s%s%s"
 312                "%s%s%s%s%s%s%s\n",
 313                cap & (1 << 31) ? "64bit " : "",
 314                cap & (1 << 30) ? "ncq " : "",
 315                cap & (1 << 28) ? "ilck " : "",
 316                cap & (1 << 27) ? "stag " : "",
 317                cap & (1 << 26) ? "pm " : "",
 318                cap & (1 << 25) ? "led " : "",
 319                cap & (1 << 24) ? "clo " : "",
 320                cap & (1 << 19) ? "nz " : "",
 321                cap & (1 << 18) ? "only " : "",
 322                cap & (1 << 17) ? "pmp " : "",
 323                cap & (1 << 15) ? "pio " : "",
 324                cap & (1 << 14) ? "slum " : "",
 325                cap & (1 << 13) ? "part " : "");
 326}
 327
 328static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
 329                        unsigned char *buf, int buf_len)
 330{
 331        struct ahci_ioports *pp = &uc_priv->port[port];
 332        struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
 333        u32 sg_count, max_bytes;
 334        int i;
 335
 336        max_bytes = MAX_DATA_BYTES_PER_SG;
 337        sg_count = ((buf_len - 1) / max_bytes) + 1;
 338        if (sg_count > AHCI_MAX_SG) {
 339                printf("Error:Too much sg!\n");
 340                return -1;
 341        }
 342
 343        for (i = 0; i < sg_count; i++) {
 344                ahci_sg->addr =
 345                        cpu_to_le32((u32)buf + i * max_bytes);
 346                ahci_sg->addr_hi = 0;
 347                ahci_sg->flags_size = cpu_to_le32(0x3fffff &
 348                                        (buf_len < max_bytes
 349                                        ? (buf_len - 1)
 350                                        : (max_bytes - 1)));
 351                ahci_sg++;
 352                buf_len -= max_bytes;
 353        }
 354
 355        return sg_count;
 356}
 357
 358static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
 359{
 360        struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
 361                                        AHCI_CMD_SLOT_SZ * cmd_slot);
 362
 363        memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
 364        cmd_hdr->opts = cpu_to_le32(opts);
 365        cmd_hdr->status = 0;
 366        pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
 367#ifdef CONFIG_PHYS_64BIT
 368        pp->cmd_slot->tbl_addr_hi =
 369            cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
 370#endif
 371}
 372
 373#define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
 374
 375static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
 376                             struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
 377                             s32 is_write)
 378{
 379        struct ahci_ioports *pp = &uc_priv->port[port];
 380        struct sata_port_regs *port_mmio = pp->port_mmio;
 381        u32 opts;
 382        int sg_count = 0, cmd_slot = 0;
 383
 384        cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
 385        if (32 == cmd_slot) {
 386                printf("Can't find empty command slot!\n");
 387                return 0;
 388        }
 389
 390        /* Check xfer length */
 391        if (buf_len > MAX_BYTES_PER_TRANS) {
 392                printf("Max transfer length is %dB\n\r",
 393                        MAX_BYTES_PER_TRANS);
 394                return 0;
 395        }
 396
 397        memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
 398        if (buf && buf_len)
 399                sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
 400        opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
 401        if (is_write) {
 402                opts |= 0x40;
 403                flush_cache((ulong)buf, buf_len);
 404        }
 405        ahci_fill_cmd_slot(pp, cmd_slot, opts);
 406
 407        flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
 408        writel_with_flush(1 << cmd_slot, &port_mmio->ci);
 409
 410        if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
 411                                      0x1 << cmd_slot)) {
 412                printf("timeout exit!\n");
 413                return -1;
 414        }
 415        invalidate_dcache_range((int)(pp->cmd_slot),
 416                                (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
 417        debug("ahci_exec_ata_cmd: %d byte transferred.\n",
 418              pp->cmd_slot->status);
 419        if (!is_write)
 420                invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
 421
 422        return buf_len;
 423}
 424
 425static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
 426{
 427        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 428        struct sata_fis_h2d *cfis = &h2d;
 429
 430        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 431        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 432        cfis->pm_port_c = 1 << 7;
 433        cfis->command = ATA_CMD_SET_FEATURES;
 434        cfis->features = SETFEATURES_XFER;
 435        cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
 436
 437        ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
 438}
 439
 440static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
 441{
 442        struct ahci_ioports *pp = &uc_priv->port[port];
 443        struct sata_port_regs *port_mmio = pp->port_mmio;
 444        u32 port_status;
 445        u32 mem;
 446        int timeout = 10000000;
 447
 448        debug("Enter start port: %d\n", port);
 449        port_status = readl(&port_mmio->ssts);
 450        debug("Port %d status: %x\n", port, port_status);
 451        if ((port_status & 0xf) != 0x03) {
 452                printf("No Link on this port!\n");
 453                return -1;
 454        }
 455
 456        mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
 457        if (!mem) {
 458                printf("No mem for table!\n");
 459                return -ENOMEM;
 460        }
 461
 462        mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
 463        memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
 464
 465        /*
 466         * First item in chunk of DMA memory: 32-slot command table,
 467         * 32 bytes each in size
 468         */
 469        pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
 470        debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
 471        mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
 472
 473        /*
 474         * Second item: Received-FIS area, 256-Byte aligned
 475         */
 476        pp->rx_fis = mem;
 477        mem += AHCI_RX_FIS_SZ;
 478
 479        /*
 480         * Third item: data area for storing a single command
 481         * and its scatter-gather table
 482         */
 483        pp->cmd_tbl = mem;
 484        debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
 485
 486        mem += AHCI_CMD_TBL_HDR;
 487
 488        writel_with_flush(0x00004444, &port_mmio->dmacr);
 489        pp->cmd_tbl_sg = (struct ahci_sg *)mem;
 490        writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
 491        writel_with_flush(pp->rx_fis, &port_mmio->fb);
 492
 493        /* Enable FRE */
 494        writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
 495                          &port_mmio->cmd);
 496
 497        /* Wait device ready */
 498        while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
 499                SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
 500                && --timeout)
 501                ;
 502        if (timeout <= 0) {
 503                debug("Device not ready for BSY, DRQ and"
 504                        "ERR in TFD!\n");
 505                return -1;
 506        }
 507
 508        writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
 509                          PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
 510                          PORT_CMD_START, &port_mmio->cmd);
 511
 512        debug("Exit start port %d\n", port);
 513
 514        return 0;
 515}
 516
 517static void dwc_ahsata_print_info(struct blk_desc *pdev)
 518{
 519        printf("SATA Device Info:\n\r");
 520        printf("S/N: %s\n\rProduct model number: %s\n\r"
 521                "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
 522                pdev->product, pdev->vendor, pdev->revision, pdev->lba);
 523}
 524
 525static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
 526{
 527        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 528        struct sata_fis_h2d *cfis = &h2d;
 529        u8 port = uc_priv->hard_port_no;
 530
 531        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 532
 533        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 534        cfis->pm_port_c = 0x80; /* is command */
 535        cfis->command = ATA_CMD_ID_ATA;
 536
 537        ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
 538                          READ_CMD);
 539        ata_swap_buf_le16(id, ATA_ID_WORDS);
 540}
 541
 542static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
 543{
 544        uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
 545        uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
 546        debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
 547}
 548
 549static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
 550                             u32 blkcnt, u8 *buffer, int is_write)
 551{
 552        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 553        struct sata_fis_h2d *cfis = &h2d;
 554        u8 port = uc_priv->hard_port_no;
 555        u32 block;
 556
 557        block = start;
 558
 559        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 560
 561        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 562        cfis->pm_port_c = 0x80; /* is command */
 563        cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
 564        cfis->device = ATA_LBA;
 565
 566        cfis->device |= (block >> 24) & 0xf;
 567        cfis->lba_high = (block >> 16) & 0xff;
 568        cfis->lba_mid = (block >> 8) & 0xff;
 569        cfis->lba_low = block & 0xff;
 570        cfis->sector_count = (u8)(blkcnt & 0xff);
 571
 572        if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
 573                              ATA_SECT_SIZE * blkcnt, is_write) > 0)
 574                return blkcnt;
 575        else
 576                return 0;
 577}
 578
 579static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
 580{
 581        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 582        struct sata_fis_h2d *cfis = &h2d;
 583        u8 port = uc_priv->hard_port_no;
 584
 585        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 586
 587        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 588        cfis->pm_port_c = 0x80; /* is command */
 589        cfis->command = ATA_CMD_FLUSH;
 590
 591        ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
 592}
 593
 594static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
 595                                 lbaint_t blkcnt, u8 *buffer, int is_write)
 596{
 597        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 598        struct sata_fis_h2d *cfis = &h2d;
 599        u8 port = uc_priv->hard_port_no;
 600        u64 block;
 601
 602        block = (u64)start;
 603
 604        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 605
 606        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 607        cfis->pm_port_c = 0x80; /* is command */
 608
 609        cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
 610                                 : ATA_CMD_READ_EXT;
 611
 612        cfis->lba_high_exp = (block >> 40) & 0xff;
 613        cfis->lba_mid_exp = (block >> 32) & 0xff;
 614        cfis->lba_low_exp = (block >> 24) & 0xff;
 615        cfis->lba_high = (block >> 16) & 0xff;
 616        cfis->lba_mid = (block >> 8) & 0xff;
 617        cfis->lba_low = block & 0xff;
 618        cfis->device = ATA_LBA;
 619        cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
 620        cfis->sector_count = blkcnt & 0xff;
 621
 622        if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
 623                              ATA_SECT_SIZE * blkcnt, is_write) > 0)
 624                return blkcnt;
 625        else
 626                return 0;
 627}
 628
 629static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
 630{
 631        struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
 632        struct sata_fis_h2d *cfis = &h2d;
 633        u8 port = uc_priv->hard_port_no;
 634
 635        memset(cfis, 0, sizeof(struct sata_fis_h2d));
 636
 637        cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
 638        cfis->pm_port_c = 0x80; /* is command */
 639        cfis->command = ATA_CMD_FLUSH_EXT;
 640
 641        ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
 642}
 643
 644static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
 645{
 646        if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
 647                uc_priv->flags |= SATA_FLAG_WCACHE;
 648        if (ata_id_has_flush(id))
 649                uc_priv->flags |= SATA_FLAG_FLUSH;
 650        if (ata_id_has_flush_ext(id))
 651                uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
 652}
 653
 654static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
 655                                  lbaint_t blkcnt, const void *buffer,
 656                                  int is_write)
 657{
 658        u32 start, blks;
 659        u8 *addr;
 660        int max_blks;
 661
 662        start = blknr;
 663        blks = blkcnt;
 664        addr = (u8 *)buffer;
 665
 666        max_blks = ATA_MAX_SECTORS_LBA48;
 667
 668        do {
 669                if (blks > max_blks) {
 670                        if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
 671                                                              max_blks, addr,
 672                                                              is_write))
 673                                return 0;
 674                        start += max_blks;
 675                        blks -= max_blks;
 676                        addr += ATA_SECT_SIZE * max_blks;
 677                } else {
 678                        if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
 679                                                          addr, is_write))
 680                                return 0;
 681                        start += blks;
 682                        blks = 0;
 683                        addr += ATA_SECT_SIZE * blks;
 684                }
 685        } while (blks != 0);
 686
 687        return blkcnt;
 688}
 689
 690static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
 691                                  lbaint_t blkcnt, const void *buffer,
 692                                  int is_write)
 693{
 694        u32 start, blks;
 695        u8 *addr;
 696        int max_blks;
 697
 698        start = blknr;
 699        blks = blkcnt;
 700        addr = (u8 *)buffer;
 701
 702        max_blks = ATA_MAX_SECTORS;
 703        do {
 704                if (blks > max_blks) {
 705                        if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
 706                                                          max_blks, addr,
 707                                                          is_write))
 708                                return 0;
 709                        start += max_blks;
 710                        blks -= max_blks;
 711                        addr += ATA_SECT_SIZE * max_blks;
 712                } else {
 713                        if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
 714                                                      addr, is_write))
 715                                return 0;
 716                        start += blks;
 717                        blks = 0;
 718                        addr += ATA_SECT_SIZE * blks;
 719                }
 720        } while (blks != 0);
 721
 722        return blkcnt;
 723}
 724
 725static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
 726{
 727        u32 linkmap;
 728        int i;
 729
 730        linkmap = uc_priv->link_port_map;
 731
 732        if (0 == linkmap) {
 733                printf("No port device detected!\n");
 734                return -ENXIO;
 735        }
 736
 737        for (i = 0; i < uc_priv->n_ports; i++) {
 738                if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
 739                        if (ahci_port_start(uc_priv, (u8)i)) {
 740                                printf("Can not start port %d\n", i);
 741                                return 1;
 742                        }
 743                        uc_priv->hard_port_no = i;
 744                        break;
 745                }
 746        }
 747
 748        return 0;
 749}
 750
 751static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
 752                                  struct blk_desc *pdev)
 753{
 754        u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
 755        u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
 756        u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
 757        u8 port = uc_priv->hard_port_no;
 758        ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
 759
 760        /* Identify device to get information */
 761        dwc_ahsata_identify(uc_priv, id);
 762
 763        /* Serial number */
 764        ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
 765        memcpy(pdev->product, serial, sizeof(serial));
 766
 767        /* Firmware version */
 768        ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
 769        memcpy(pdev->revision, firmware, sizeof(firmware));
 770
 771        /* Product model */
 772        ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
 773        memcpy(pdev->vendor, product, sizeof(product));
 774
 775        /* Total sectors */
 776        pdev->lba = ata_id_n_sectors(id);
 777
 778        pdev->type = DEV_TYPE_HARDDISK;
 779        pdev->blksz = ATA_SECT_SIZE;
 780        pdev->lun = 0;
 781
 782        /* Check if support LBA48 */
 783        if (ata_id_has_lba48(id)) {
 784                pdev->lba48 = 1;
 785                debug("Device support LBA48\n\r");
 786        }
 787
 788        /* Get the NCQ queue depth from device */
 789        uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
 790        uc_priv->flags |= ata_id_queue_depth(id);
 791
 792        /* Get the xfer mode from device */
 793        dwc_ahsata_xfer_mode(uc_priv, id);
 794
 795        /* Get the write cache status from device */
 796        dwc_ahsata_init_wcache(uc_priv, id);
 797
 798        /* Set the xfer mode to highest speed */
 799        ahci_set_feature(uc_priv, port);
 800
 801        dwc_ahsata_print_info(pdev);
 802
 803        return 0;
 804}
 805
 806/*
 807 * SATA interface between low level driver and command layer
 808 */
 809static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
 810                              struct blk_desc *desc, ulong blknr,
 811                              lbaint_t blkcnt, void *buffer)
 812{
 813        u32 rc;
 814
 815        if (desc->lba48)
 816                rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
 817                                            READ_CMD);
 818        else
 819                rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
 820                                            READ_CMD);
 821
 822        return rc;
 823}
 824
 825static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
 826                               struct blk_desc *desc, ulong blknr,
 827                               lbaint_t blkcnt, const void *buffer)
 828{
 829        u32 rc;
 830        u32 flags = uc_priv->flags;
 831
 832        if (desc->lba48) {
 833                rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
 834                                            WRITE_CMD);
 835                if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
 836                        dwc_ahsata_flush_cache_ext(uc_priv);
 837        } else {
 838                rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
 839                                            WRITE_CMD);
 840                if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
 841                        dwc_ahsata_flush_cache(uc_priv);
 842        }
 843
 844        return rc;
 845}
 846
 847int dwc_ahsata_port_status(struct udevice *dev, int port)
 848{
 849        struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 850        struct sata_port_regs *port_mmio;
 851
 852        port_mmio = uc_priv->port[port].port_mmio;
 853        return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
 854}
 855
 856int dwc_ahsata_bus_reset(struct udevice *dev)
 857{
 858        struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 859        struct sata_host_regs *host_mmio = uc_priv->mmio_base;
 860
 861        setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
 862        while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
 863                udelay(100);
 864
 865        return 0;
 866}
 867
 868int dwc_ahsata_scan(struct udevice *dev)
 869{
 870        struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 871        struct blk_desc *desc;
 872        struct udevice *blk;
 873        int ret;
 874
 875        /*
 876        * Create only one block device and do detection
 877        * to make sure that there won't be a lot of
 878        * block devices created
 879        */
 880        device_find_first_child(dev, &blk);
 881        if (!blk) {
 882                ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
 883                                         UCLASS_AHCI, -1, 512, 0, &blk);
 884                if (ret) {
 885                        debug("Can't create device\n");
 886                        return ret;
 887                }
 888        }
 889
 890        desc = dev_get_uclass_plat(blk);
 891        ret = dwc_ahsata_scan_common(uc_priv, desc);
 892        if (ret) {
 893                debug("%s: Failed to scan bus\n", __func__);
 894                return ret;
 895        }
 896
 897        ret = blk_probe_or_unbind(dev);
 898        if (ret < 0)
 899                /* TODO: undo create */
 900                return ret;
 901
 902        return 0;
 903}
 904
 905int dwc_ahsata_probe(struct udevice *dev)
 906{
 907        struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
 908        int ret;
 909
 910#if defined(CONFIG_MX6)
 911        setup_sata();
 912#endif
 913        uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 914                        ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
 915        uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
 916
 917        /* initialize adapter */
 918        ret = ahci_host_init(uc_priv);
 919        if (ret)
 920                return ret;
 921
 922        ahci_print_info(uc_priv);
 923
 924        return dwc_ahci_start_ports(uc_priv);
 925}
 926
 927static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
 928                             lbaint_t blkcnt, void *buffer)
 929{
 930        struct blk_desc *desc = dev_get_uclass_plat(blk);
 931        struct udevice *dev = dev_get_parent(blk);
 932        struct ahci_uc_priv *uc_priv;
 933
 934        uc_priv = dev_get_uclass_priv(dev);
 935        return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
 936}
 937
 938static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
 939                              lbaint_t blkcnt, const void *buffer)
 940{
 941        struct blk_desc *desc = dev_get_uclass_plat(blk);
 942        struct udevice *dev = dev_get_parent(blk);
 943        struct ahci_uc_priv *uc_priv;
 944
 945        uc_priv = dev_get_uclass_priv(dev);
 946        return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
 947}
 948
 949static const struct blk_ops dwc_ahsata_blk_ops = {
 950        .read   = dwc_ahsata_read,
 951        .write  = dwc_ahsata_write,
 952};
 953
 954U_BOOT_DRIVER(dwc_ahsata_blk) = {
 955        .name           = "dwc_ahsata_blk",
 956        .id             = UCLASS_BLK,
 957        .ops            = &dwc_ahsata_blk_ops,
 958};
 959
 960#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
 961struct ahci_ops dwc_ahsata_ahci_ops = {
 962        .port_status = dwc_ahsata_port_status,
 963        .reset       = dwc_ahsata_bus_reset,
 964        .scan        = dwc_ahsata_scan,
 965};
 966
 967static const struct udevice_id dwc_ahsata_ahci_ids[] = {
 968        { .compatible = "fsl,imx6q-ahci" },
 969        { }
 970};
 971
 972U_BOOT_DRIVER(dwc_ahsata_ahci) = {
 973        .name     = "dwc_ahsata_ahci",
 974        .id       = UCLASS_AHCI,
 975        .of_match = dwc_ahsata_ahci_ids,
 976        .ops      = &dwc_ahsata_ahci_ops,
 977        .probe    = dwc_ahsata_probe,
 978};
 979#endif
 980