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18#include <common.h>
19#include <clk.h>
20#include <cpu_func.h>
21#include <dm.h>
22#include <dma-uclass.h>
23#include <log.h>
24#include <malloc.h>
25#include <memalign.h>
26#include <net.h>
27#include <reset.h>
28#include <asm/io.h>
29#include <linux/bitops.h>
30#include <linux/delay.h>
31
32#define DMA_RX_DESC 6
33#define DMA_TX_DESC 1
34
35
36#define DMA_CHAN_FLOWC(x) ((x) >> 1)
37#define DMA_CHAN_MAX 16
38#define DMA_CHAN_SIZE 0x10
39#define DMA_CHAN_TOUT 500
40
41
42#define DMA_CFG_REG 0x00
43#define DMA_CFG_ENABLE_SHIFT 0
44#define DMA_CFG_ENABLE_MASK (1 << DMA_CFG_ENABLE_SHIFT)
45#define DMA_CFG_FLOWC_ENABLE(x) BIT(DMA_CHAN_FLOWC(x) + 1)
46#define DMA_CFG_NCHANS_SHIFT 24
47#define DMA_CFG_NCHANS_MASK (0xf << DMA_CFG_NCHANS_SHIFT)
48
49
50#define DMA_FLOWC_THR_LO_REG(x) (0x04 + DMA_CHAN_FLOWC(x) * 0x0c)
51#define DMA_FLOWC_THR_HI_REG(x) (0x08 + DMA_CHAN_FLOWC(x) * 0x0c)
52#define DMA_FLOWC_ALLOC_REG(x) (0x0c + DMA_CHAN_FLOWC(x) * 0x0c)
53#define DMA_FLOWC_ALLOC_FORCE_SHIFT 31
54#define DMA_FLOWC_ALLOC_FORCE_MASK (1 << DMA_FLOWC_ALLOC_FORCE_SHIFT)
55
56
57#define DMA_RST_REG 0x34
58#define DMA_RST_CHAN_SHIFT 0
59#define DMA_RST_CHAN_MASK(x) (1 << x)
60
61
62#define DMAC_CFG_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
63#define DMAC_CFG_ENABLE_SHIFT 0
64#define DMAC_CFG_ENABLE_MASK (1 << DMAC_CFG_ENABLE_SHIFT)
65#define DMAC_CFG_PKT_HALT_SHIFT 1
66#define DMAC_CFG_PKT_HALT_MASK (1 << DMAC_CFG_PKT_HALT_SHIFT)
67#define DMAC_CFG_BRST_HALT_SHIFT 2
68#define DMAC_CFG_BRST_HALT_MASK (1 << DMAC_CFG_BRST_HALT_SHIFT)
69
70
71#define DMAC_BURST_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
72
73
74#define DMAS_RSTART_REG(x) (DMA_CHAN_SIZE * (x) + 0x00)
75
76
77#define DMAS_STATE_DATA_REG(x) (DMA_CHAN_SIZE * (x) + 0x04)
78
79
80#define DMAS_DESC_LEN_STATUS_REG(x) (DMA_CHAN_SIZE * (x) + 0x08)
81
82
83#define DMAS_DESC_BASE_BUFPTR_REG(x) (DMA_CHAN_SIZE * (x) + 0x0c)
84
85
86#define DMAD_ST_CRC_SHIFT 8
87#define DMAD_ST_CRC_MASK (1 << DMAD_ST_CRC_SHIFT)
88#define DMAD_ST_WRAP_SHIFT 12
89#define DMAD_ST_WRAP_MASK (1 << DMAD_ST_WRAP_SHIFT)
90#define DMAD_ST_SOP_SHIFT 13
91#define DMAD_ST_SOP_MASK (1 << DMAD_ST_SOP_SHIFT)
92#define DMAD_ST_EOP_SHIFT 14
93#define DMAD_ST_EOP_MASK (1 << DMAD_ST_EOP_SHIFT)
94#define DMAD_ST_OWN_SHIFT 15
95#define DMAD_ST_OWN_MASK (1 << DMAD_ST_OWN_SHIFT)
96
97#define DMAD6348_ST_OV_ERR_SHIFT 0
98#define DMAD6348_ST_OV_ERR_MASK (1 << DMAD6348_ST_OV_ERR_SHIFT)
99#define DMAD6348_ST_CRC_ERR_SHIFT 1
100#define DMAD6348_ST_CRC_ERR_MASK (1 << DMAD6348_ST_CRC_ERR_SHIFT)
101#define DMAD6348_ST_RX_ERR_SHIFT 2
102#define DMAD6348_ST_RX_ERR_MASK (1 << DMAD6348_ST_RX_ERR_SHIFT)
103#define DMAD6348_ST_OS_ERR_SHIFT 4
104#define DMAD6348_ST_OS_ERR_MASK (1 << DMAD6348_ST_OS_ERR_SHIFT)
105#define DMAD6348_ST_UN_ERR_SHIFT 9
106#define DMAD6348_ST_UN_ERR_MASK (1 << DMAD6348_ST_UN_ERR_SHIFT)
107
108struct bcm6348_dma_desc {
109 uint16_t length;
110 uint16_t status;
111 uint32_t address;
112};
113
114struct bcm6348_chan_priv {
115 void __iomem *dma_ring;
116 uint8_t dma_ring_size;
117 uint8_t desc_id;
118 uint8_t desc_cnt;
119 bool *busy_desc;
120 bool running;
121};
122
123struct bcm6348_iudma_hw {
124 uint16_t err_mask;
125};
126
127struct bcm6348_iudma_priv {
128 const struct bcm6348_iudma_hw *hw;
129 void __iomem *base;
130 void __iomem *chan;
131 void __iomem *sram;
132 struct bcm6348_chan_priv **ch_priv;
133 uint8_t n_channels;
134};
135
136static inline bool bcm6348_iudma_chan_is_rx(uint8_t ch)
137{
138 return !(ch & 1);
139}
140
141static inline void bcm6348_iudma_fdc(void *ptr, ulong size)
142{
143 ulong start = (ulong) ptr;
144
145 flush_dcache_range(start, start + size);
146}
147
148static inline void bcm6348_iudma_idc(void *ptr, ulong size)
149{
150 ulong start = (ulong) ptr;
151
152 invalidate_dcache_range(start, start + size);
153}
154
155static void bcm6348_iudma_chan_stop(struct bcm6348_iudma_priv *priv,
156 uint8_t ch)
157{
158 unsigned int timeout = DMA_CHAN_TOUT;
159
160 do {
161 uint32_t cfg, halt;
162
163 if (timeout > DMA_CHAN_TOUT / 2)
164 halt = DMAC_CFG_PKT_HALT_MASK;
165 else
166 halt = DMAC_CFG_BRST_HALT_MASK;
167
168
169 writel_be(halt, priv->chan + DMAC_CFG_REG(ch));
170 mb();
171
172
173 cfg = readl_be(priv->chan + DMAC_CFG_REG(ch));
174 if (!(cfg & DMAC_CFG_ENABLE_MASK))
175 break;
176
177 udelay(1);
178 } while (--timeout);
179
180 if (!timeout)
181 pr_err("unable to stop channel %u\n", ch);
182
183
184 setbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
185 mb();
186 clrbits_be32(priv->base + DMA_RST_REG, DMA_RST_CHAN_MASK(ch));
187}
188
189static int bcm6348_iudma_disable(struct dma *dma)
190{
191 struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
192 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
193
194
195 bcm6348_iudma_chan_stop(priv, dma->id);
196
197
198 if (bcm6348_iudma_chan_is_rx(dma->id))
199 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK,
200 DMA_FLOWC_ALLOC_REG(dma->id));
201
202
203 ch_priv->running = false;
204 ch_priv->desc_id = 0;
205 if (bcm6348_iudma_chan_is_rx(dma->id))
206 ch_priv->desc_cnt = 0;
207 else
208 ch_priv->desc_cnt = ch_priv->dma_ring_size;
209
210 return 0;
211}
212
213static int bcm6348_iudma_enable(struct dma *dma)
214{
215 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
216 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
217 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
218 uint8_t i;
219
220
221 for (i = 0; i < ch_priv->desc_cnt; i++) {
222 if (bcm6348_iudma_chan_is_rx(dma->id)) {
223 ch_priv->busy_desc[i] = false;
224 dma_desc->status |= DMAD_ST_OWN_MASK;
225 } else {
226 dma_desc->status = 0;
227 dma_desc->length = 0;
228 dma_desc->address = 0;
229 }
230
231 if (i == ch_priv->desc_cnt - 1)
232 dma_desc->status |= DMAD_ST_WRAP_MASK;
233
234 dma_desc++;
235 }
236
237
238 ch_priv->desc_id = 0;
239
240
241 bcm6348_iudma_fdc(ch_priv->dma_ring,
242 sizeof(*dma_desc) * ch_priv->desc_cnt);
243
244
245 writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id));
246 writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id));
247 writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id));
248
249
250 writel_be(virt_to_phys(ch_priv->dma_ring),
251 priv->sram + DMAS_RSTART_REG(dma->id));
252
253
254 if (bcm6348_iudma_chan_is_rx(dma->id)) {
255 u32 val;
256
257 setbits_be32(priv->base + DMA_CFG_REG,
258 DMA_CFG_FLOWC_ENABLE(dma->id));
259
260 val = ch_priv->desc_cnt / 3;
261 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id));
262
263 val = (ch_priv->desc_cnt * 2) / 3;
264 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id));
265
266 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id));
267 }
268
269
270 writel_be(ch_priv->desc_cnt,
271 priv->chan + DMAC_BURST_REG(dma->id));
272
273
274 if (bcm6348_iudma_chan_is_rx(dma->id))
275 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
276 DMAC_CFG_ENABLE_MASK);
277
278
279 ch_priv->running = true;
280
281 return 0;
282}
283
284static int bcm6348_iudma_request(struct dma *dma)
285{
286 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
287 struct bcm6348_chan_priv *ch_priv;
288
289
290 if (dma->id >= priv->n_channels)
291 return -ENODEV;
292
293
294 priv->ch_priv[dma->id] = calloc(1, sizeof(struct bcm6348_chan_priv));
295 if (!priv->ch_priv[dma->id])
296 return -ENOMEM;
297 ch_priv = priv->ch_priv[dma->id];
298
299
300 if (bcm6348_iudma_chan_is_rx(dma->id))
301 ch_priv->dma_ring_size = DMA_RX_DESC;
302 else
303 ch_priv->dma_ring_size = DMA_TX_DESC;
304
305 ch_priv->dma_ring =
306 malloc_cache_aligned(sizeof(struct bcm6348_dma_desc) *
307 ch_priv->dma_ring_size);
308 if (!ch_priv->dma_ring)
309 return -ENOMEM;
310
311
312 ch_priv->running = false;
313 ch_priv->desc_id = 0;
314 if (bcm6348_iudma_chan_is_rx(dma->id)) {
315 ch_priv->desc_cnt = 0;
316 ch_priv->busy_desc = NULL;
317 } else {
318 ch_priv->desc_cnt = ch_priv->dma_ring_size;
319 ch_priv->busy_desc = calloc(ch_priv->desc_cnt, sizeof(bool));
320 }
321
322 return 0;
323}
324
325static int bcm6348_iudma_receive(struct dma *dma, void **dst, void *metadata)
326{
327 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
328 const struct bcm6348_iudma_hw *hw = priv->hw;
329 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
330 struct bcm6348_dma_desc *dma_desc = dma_desc = ch_priv->dma_ring;
331 int ret;
332
333 if (!ch_priv->running)
334 return -EINVAL;
335
336
337 dma_desc += ch_priv->desc_id;
338
339
340 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
341
342
343 if (dma_desc->status & DMAD_ST_OWN_MASK)
344 return -EAGAIN;
345
346
347 if (!(dma_desc->status & DMAD_ST_EOP_MASK) ||
348 !(dma_desc->status & DMAD_ST_SOP_MASK) ||
349 (dma_desc->status & hw->err_mask)) {
350 pr_err("invalid pkt received (ch=%ld desc=%u) (st=%04x)\n",
351 dma->id, ch_priv->desc_id, dma_desc->status);
352 ret = -EAGAIN;
353 } else {
354
355 *dst = phys_to_virt(dma_desc->address);
356
357
358 bcm6348_iudma_idc(*dst, dma_desc->length);
359
360
361 ret = dma_desc->length;
362 }
363
364
365 ch_priv->busy_desc[ch_priv->desc_id] = true;
366
367
368 ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
369
370 return ret;
371}
372
373static int bcm6348_iudma_send(struct dma *dma, void *src, size_t len,
374 void *metadata)
375{
376 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
377 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
378 struct bcm6348_dma_desc *dma_desc;
379 uint16_t status;
380
381 if (!ch_priv->running)
382 return -EINVAL;
383
384
385 bcm6348_iudma_fdc(src, len);
386
387
388 dma_desc = ch_priv->dma_ring;
389 dma_desc += ch_priv->desc_id;
390
391
392 status = (DMAD_ST_OWN_MASK |
393 DMAD_ST_EOP_MASK |
394 DMAD_ST_CRC_MASK |
395 DMAD_ST_SOP_MASK);
396 if (ch_priv->desc_id == ch_priv->desc_cnt - 1)
397 status |= DMAD_ST_WRAP_MASK;
398
399
400 dma_desc->address = virt_to_phys(src);
401 dma_desc->length = len;
402 dma_desc->status = status;
403
404
405 bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
406
407
408 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id), DMAC_CFG_ENABLE_MASK);
409
410
411 do {
412
413 bcm6348_iudma_idc(dma_desc, sizeof(*dma_desc));
414
415 if (!(dma_desc->status & DMAD_ST_OWN_MASK))
416 break;
417 } while(1);
418
419
420 ch_priv->desc_id = (ch_priv->desc_id + 1) % ch_priv->desc_cnt;
421
422 return 0;
423}
424
425static int bcm6348_iudma_free_rcv_buf(struct dma *dma, void *dst, size_t size)
426{
427 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
428 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
429 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
430 uint16_t status;
431 uint8_t i;
432 u32 cfg;
433
434
435 for (i = 0; i < ch_priv->desc_cnt; i++) {
436 if (phys_to_virt(dma_desc->address) == dst)
437 break;
438
439 dma_desc++;
440 }
441
442
443 if (i == ch_priv->desc_cnt) {
444 pr_err("dirty dma descriptor not found\n");
445 return -ENOENT;
446 }
447
448
449 bcm6348_iudma_idc(ch_priv->dma_ring,
450 sizeof(*dma_desc) * ch_priv->desc_cnt);
451
452
453 ch_priv->busy_desc[i] = false;
454
455 status = DMAD_ST_OWN_MASK;
456 if (i == ch_priv->desc_cnt - 1)
457 status |= DMAD_ST_WRAP_MASK;
458
459 dma_desc->status |= status;
460 dma_desc->length = PKTSIZE_ALIGN;
461
462
463 writel_be(1, DMA_FLOWC_ALLOC_REG(dma->id));
464
465
466 bcm6348_iudma_fdc(ch_priv->dma_ring,
467 sizeof(*dma_desc) * ch_priv->desc_cnt);
468
469
470 cfg = readl_be(priv->chan + DMAC_CFG_REG(dma->id));
471 if (!(cfg & DMAC_CFG_ENABLE_MASK))
472 setbits_be32(priv->chan + DMAC_CFG_REG(dma->id),
473 DMAC_CFG_ENABLE_MASK);
474
475 return 0;
476}
477
478static int bcm6348_iudma_add_rcv_buf(struct dma *dma, void *dst, size_t size)
479{
480 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
481 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
482 struct bcm6348_dma_desc *dma_desc = ch_priv->dma_ring;
483
484
485 if (ch_priv->desc_cnt == ch_priv->dma_ring_size) {
486 pr_err("max number of buffers reached\n");
487 return -EINVAL;
488 }
489
490
491 dma_desc += ch_priv->desc_cnt;
492
493
494 dma_desc->address = virt_to_phys(dst);
495 dma_desc->length = size;
496 dma_desc->status = 0;
497
498
499 bcm6348_iudma_fdc(dma_desc, sizeof(*dma_desc));
500
501
502 ch_priv->desc_cnt++;
503
504 return 0;
505}
506
507static int bcm6348_iudma_prepare_rcv_buf(struct dma *dma, void *dst,
508 size_t size)
509{
510 const struct bcm6348_iudma_priv *priv = dev_get_priv(dma->dev);
511 struct bcm6348_chan_priv *ch_priv = priv->ch_priv[dma->id];
512
513
514 if (ch_priv->running)
515 return bcm6348_iudma_free_rcv_buf(dma, dst, size);
516 else
517 return bcm6348_iudma_add_rcv_buf(dma, dst, size);
518}
519
520static const struct dma_ops bcm6348_iudma_ops = {
521 .disable = bcm6348_iudma_disable,
522 .enable = bcm6348_iudma_enable,
523 .prepare_rcv_buf = bcm6348_iudma_prepare_rcv_buf,
524 .request = bcm6348_iudma_request,
525 .receive = bcm6348_iudma_receive,
526 .send = bcm6348_iudma_send,
527};
528
529static const struct bcm6348_iudma_hw bcm6348_hw = {
530 .err_mask = (DMAD6348_ST_OV_ERR_MASK |
531 DMAD6348_ST_CRC_ERR_MASK |
532 DMAD6348_ST_RX_ERR_MASK |
533 DMAD6348_ST_OS_ERR_MASK |
534 DMAD6348_ST_UN_ERR_MASK),
535};
536
537static const struct bcm6348_iudma_hw bcm6368_hw = {
538 .err_mask = 0,
539};
540
541static const struct udevice_id bcm6348_iudma_ids[] = {
542 {
543 .compatible = "brcm,bcm6348-iudma",
544 .data = (ulong)&bcm6348_hw,
545 }, {
546 .compatible = "brcm,bcm6368-iudma",
547 .data = (ulong)&bcm6368_hw,
548 }, { }
549};
550
551static int bcm6348_iudma_probe(struct udevice *dev)
552{
553 struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
554 struct bcm6348_iudma_priv *priv = dev_get_priv(dev);
555 const struct bcm6348_iudma_hw *hw =
556 (const struct bcm6348_iudma_hw *)dev_get_driver_data(dev);
557 uint8_t ch;
558 int i;
559
560 uc_priv->supported = (DMA_SUPPORTS_DEV_TO_MEM |
561 DMA_SUPPORTS_MEM_TO_DEV);
562 priv->hw = hw;
563
564
565 priv->base = dev_remap_addr_name(dev, "dma");
566 if (!priv->base)
567 return -EINVAL;
568
569
570 priv->chan = dev_remap_addr_name(dev, "dma-channels");
571 if (!priv->chan)
572 return -EINVAL;
573
574
575 priv->sram = dev_remap_addr_name(dev, "dma-sram");
576 if (!priv->sram)
577 return -EINVAL;
578
579
580 priv->n_channels = dev_read_u32_default(dev, "dma-channels", 8);
581 if (priv->n_channels > DMA_CHAN_MAX)
582 return -EINVAL;
583
584
585 for (i = 0; ; i++) {
586 struct clk clk;
587 int ret;
588
589 ret = clk_get_by_index(dev, i, &clk);
590 if (ret < 0)
591 break;
592
593 ret = clk_enable(&clk);
594 if (ret < 0) {
595 pr_err("error enabling clock %d\n", i);
596 return ret;
597 }
598
599 clk_free(&clk);
600 }
601
602
603 for (i = 0; ; i++) {
604 struct reset_ctl reset;
605 int ret;
606
607 ret = reset_get_by_index(dev, i, &reset);
608 if (ret < 0)
609 break;
610
611 ret = reset_deassert(&reset);
612 if (ret < 0) {
613 pr_err("error deasserting reset %d\n", i);
614 return ret;
615 }
616
617 ret = reset_free(&reset);
618 if (ret < 0) {
619 pr_err("error freeing reset %d\n", i);
620 return ret;
621 }
622 }
623
624
625 clrbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
626
627
628 priv->ch_priv = calloc(priv->n_channels,
629 sizeof(struct bcm6348_chan_priv*));
630 if (!priv->ch_priv)
631 return -ENOMEM;
632
633
634 for (ch = 0; ch < priv->n_channels; ch++)
635 bcm6348_iudma_chan_stop(priv, ch);
636
637
638 setbits_be32(priv->base + DMA_CFG_REG, DMA_CFG_ENABLE_MASK);
639
640 return 0;
641}
642
643U_BOOT_DRIVER(bcm6348_iudma) = {
644 .name = "bcm6348_iudma",
645 .id = UCLASS_DMA,
646 .of_match = bcm6348_iudma_ids,
647 .ops = &bcm6348_iudma_ops,
648 .priv_auto = sizeof(struct bcm6348_iudma_priv),
649 .probe = bcm6348_iudma_probe,
650};
651