LXR uboot/drivers/i2c/ast2600

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright ASPEED Technology Inc.
   4 */
   5#ifndef __AST2600_I2C_H_
   6#define __AST2600_I2C_H_
   7
   8struct ast2600_i2c_regs {
   9        u32 fun_ctrl;
  10        u32 ac_timing;
  11        u32 trx_buff;
  12        u32 icr;
  13        u32 ier;
  14        u32 isr;
  15        u32 cmd_sts;
  16};
  17
  18/* 0x00 : I2CC Master/Slave Function Control Register  */
  19#define I2CC_SLAVE_ADDR_RX_EN   BIT(20)
  20#define I2CC_MASTER_RETRY_MASK  GENMASK(19, 18)
  21#define I2CC_MASTER_RETRY(x)    (((x) & GENMASK(1, 0)) << 18)
  22#define I2CC_BUS_AUTO_RELEASE   BIT(17)
  23#define I2CC_M_SDA_LOCK_EN              BIT(16)
  24#define I2CC_MULTI_MASTER_DIS   BIT(15)
  25#define I2CC_M_SCL_DRIVE_EN             BIT(14)
  26#define I2CC_MSB_STS                    BIT(9)
  27#define I2CC_SDA_DRIVE_1T_EN    BIT(8)
  28#define I2CC_M_SDA_DRIVE_1T_EN  BIT(7)
  29#define I2CC_M_HIGH_SPEED_EN    BIT(6)
  30/* reserved 5 : 2 */
  31#define I2CC_SLAVE_EN                   BIT(1)
  32#define I2CC_MASTER_EN                  BIT(0)
  33
  34/* 0x04 : I2CD Clock and AC Timing Control Register #1 */
  35/* Base register value. These bits are always set by the driver. */
  36#define I2CD_CACTC_BASE         0xfff00300
  37#define I2CD_TCKHIGH_SHIFT      16
  38#define I2CD_TCKLOW_SHIFT       12
  39#define I2CD_THDDAT_SHIFT       10
  40#define I2CD_TO_DIV_SHIFT       8
  41#define I2CD_BASE_DIV_SHIFT     0
  42
  43/* 0x08 : I2CC Master/Slave Transmit/Receive Byte Buffer Register */
  44#define I2CC_TX_DIR_MASK                GENMASK(31, 29)
  45#define I2CC_SDA_OE                             BIT(28)
  46#define I2CC_SDA_O                              BIT(27)
  47#define I2CC_SCL_OE                             BIT(26)
  48#define I2CC_SCL_O                              BIT(25)
  49
  50#define I2CC_SCL_LINE_STS               BIT(18)
  51#define I2CC_SDA_LINE_STS               BIT(17)
  52#define I2CC_BUS_BUSY_STS               BIT(16)
  53#define I2CC_GET_RX_BUFF(x)             (((x) >> 8) & GENMASK(7, 0))
  54
  55/* 0x10 : I2CM Master Interrupt Control Register */
  56/* 0x14 : I2CM Master Interrupt Status Register  */
  57#define I2CM_PKT_TIMEOUT                BIT(18)
  58#define I2CM_PKT_ERROR                  BIT(17)
  59#define I2CM_PKT_DONE                   BIT(16)
  60
  61#define I2CM_BUS_RECOVER_FAIL   BIT(15)
  62#define I2CM_SDA_DL_TO                  BIT(14)
  63#define I2CM_BUS_RECOVER                BIT(13)
  64#define I2CM_SMBUS_ALT                  BIT(12)
  65
  66#define I2CM_SCL_LOW_TO                 BIT(6)
  67#define I2CM_ABNORMAL                   BIT(5)
  68#define I2CM_NORMAL_STOP                BIT(4)
  69#define I2CM_ARBIT_LOSS                 BIT(3)
  70#define I2CM_RX_DONE                    BIT(2)
  71#define I2CM_TX_NAK                             BIT(1)
  72#define I2CM_TX_ACK                             BIT(0)
  73
  74/* 0x18 : I2CM Master Command/Status Register   */
  75#define I2CM_PKT_ADDR(x)                (((x) & GENMASK(6, 0)) << 24)
  76#define I2CM_PKT_EN                             BIT(16)
  77#define I2CM_SDA_OE_OUT_DIR             BIT(15)
  78#define I2CM_SDA_O_OUT_DIR              BIT(14)
  79#define I2CM_SCL_OE_OUT_DIR             BIT(13)
  80#define I2CM_SCL_O_OUT_DIR              BIT(12)
  81#define I2CM_RECOVER_CMD_EN             BIT(11)
  82
  83#define I2CM_RX_DMA_EN                  BIT(9)
  84#define I2CM_TX_DMA_EN                  BIT(8)
  85/* Command Bit */
  86#define I2CM_RX_BUFF_EN                 BIT(7)
  87#define I2CM_TX_BUFF_EN                 BIT(6)
  88#define I2CM_STOP_CMD                   BIT(5)
  89#define I2CM_RX_CMD_LAST                BIT(4)
  90#define I2CM_RX_CMD                             BIT(3)
  91
  92#define I2CM_TX_CMD                             BIT(1)
  93#define I2CM_START_CMD                  BIT(0)
  94
  95#define I2C_TIMEOUT_US 100000
  96
  97/* I2C Global Register */
  98#define I2CG_ISR                        0x00
  99#define I2CG_SLAVE_ISR          0x04
 100#define I2CG_OWNER                  0x08
 101#define I2CG_CTRL                   0x0C
 102#define I2CG_CLK_DIV_CTRL       0x10
 103
 104#define I2CG_SLAVE_PKT_NAK          BIT(4)
 105#define I2CG_M_S_SEPARATE_INTR  BIT(3)
 106#define I2CG_CTRL_NEW_REG           BIT(2)
 107#define I2CG_CTRL_NEW_CLK_DIV   BIT(1)
 108
 109#define GLOBAL_INIT                                     \
 110                        (I2CG_SLAVE_PKT_NAK |   \
 111                        I2CG_CTRL_NEW_REG |             \
 112                        I2CG_CTRL_NEW_CLK_DIV)
 113#define I2CCG_DIV_CTRL 0xc6411208
 114
 115#define GET_CLK1_DIV(x) ((x) & 0xff)
 116#define GET_CLK2_DIV(x) (((x) >> 8) & 0xff)
 117#define GET_CLK3_DIV(x) (((x) >> 16) & 0xff)
 118#define GET_CLK4_DIV(x) (((x) >> 24) & 0xff)
 119
 120#endif                          /* __AST2600_I2C_H_ */
 121