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7
8
9#include <common.h>
10#include <dm.h>
11#include <errno.h>
12#include <dm/pinctrl.h>
13#include <linux/kernel.h>
14
15#include "sh_pfc.h"
16
17
18
19
20
21#define CPU_ALL_GP(fn, sfx) \
22 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
30 PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
31 PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
32 PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
33 PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
34 PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
35 PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
36 PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
37 PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38 PORT_GP_1(7, 7, fn, sfx), \
39 PORT_GP_1(7, 8, fn, sfx), \
40 PORT_GP_1(7, 9, fn, sfx), \
41 PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
42 PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
43 PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
44 PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
45 PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
46 PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
47 PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
48 PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
49 PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
50 PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
51 PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
52 PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
53 PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
54 PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
55 PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
56 PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
57
58#define CPU_ALL_NOGP(fn) \
59 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
60 PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
61 PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \
62 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
63 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
64 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
65 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
66
67enum {
68 PINMUX_RESERVED = 0,
69
70 PINMUX_DATA_BEGIN,
71 GP_ALL(DATA),
72 PINMUX_DATA_END,
73
74 PINMUX_FUNCTION_BEGIN,
75 GP_ALL(FN),
76
77
78 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
79 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
80 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
81 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
82 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
83 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
84
85
86 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
87 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
88 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
89 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
90 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
91 FN_IP3_21_20,
92
93
94 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
95 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
96 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
97 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
98 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
99 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
100 FN_IP6_5_3, FN_IP6_7_6,
101
102
103 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
104 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
105 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
106 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
107 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
108 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
109 FN_IP9_18_17,
110
111
112 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
113 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
114 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
115 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
116 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
117 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
118 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
119 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
120
121
122 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
123 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
124 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
125 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
126 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
127 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
128 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
129
130
131 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
132 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
133 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
134 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
135 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
136 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
137 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
138 FN_USB1_OVC, FN_DU0_DOTCLKIN,
139
140
141 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
142 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
143 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
144 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
145 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
146 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
147
148
149 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
150 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
151 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
152 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
153 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
154 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
155
156
157 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
158 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
159 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
160 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
161 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
162 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
163 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
164 FN_A15, FN_BPFCLK_C,
165 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
166 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
167 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
168
169
170 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
171 FN_A20, FN_SPCLK,
172 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
173 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
174 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
175 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
176 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
177 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
178 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
179 FN_EX_CS1_N, FN_MSIOF2_SCK,
180 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
181 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
182
183
184 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
185 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
186 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
187 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
188 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
189 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
190 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
191 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
192 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
193 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
194 FN_DACK0, FN_DRACK0, FN_REMOCON,
195 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
196 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
197 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
198 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
199
200
201 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
202 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
203 FN_GLO_I0_D,
204 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
205 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
206 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
207 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
208 FN_GLO_Q1_D, FN_HCTS1_N_E,
209 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
210 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
211 FN_SSI_SCK4, FN_GLO_SS_D,
212 FN_SSI_WS4, FN_GLO_RFON_D,
213 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
214 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
215 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
216
217
218 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
219 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
220 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
221 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
222 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
223 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
224 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
225 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
226 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
227 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
228 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
229 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
230 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
231 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
232 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
233
234
235 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
236 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
237 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
238 FN_SCIFA2_RXD, FN_FMIN_E,
239 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
240 FN_IRQ0, FN_SCIFB1_RXD_D,
241 FN_IRQ1, FN_SCIFB1_SCK_C,
242 FN_IRQ2, FN_SCIFB1_TXD_D,
243 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E,
244 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
245 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
246 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
247 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
248 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
249
250
251 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
252 FN_SCIF_CLK_B, FN_GPS_MAG_D,
253 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
254 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
255 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
256 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
257 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
258 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
259 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
260 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
261 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
262 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
263 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
264 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
265 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
266 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
267 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
268 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
269
270
271 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
272 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
273 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
274 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
275 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
276 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
277 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
278 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
279 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
280 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
281 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
282 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
283 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
284 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
285 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
286 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
287 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
288
289
290 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
291 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
292 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
293 FN_DU1_DOTCLKOUT0, FN_QCLK,
294 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
295 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
296 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
297 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
298 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
299 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
300 FN_DU1_DISP, FN_QPOLA,
301 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
302 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
303 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
304 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
305 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
306 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
307 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
308 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
309
310
311 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
312 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
313 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
314 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
315 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
316 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
317 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
318 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
319 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
320 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
321 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
322 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
323 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
324 FN_TS_SDATA0_C, FN_ATACS11_N,
325 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
326 FN_TS_SCK0_C, FN_ATAG1_N,
327 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
328 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
329 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
330
331
332 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
333 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
334 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
335 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
336 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
337 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
338 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
339 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
340 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
341 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
342 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
343 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
344 FN_VI1_DATA7, FN_AVB_MDC,
345 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
346 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
347
348
349 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
350 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
351 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
352 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
353 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
354 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
355 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
356 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
357 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
358 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
359 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
360 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
361 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
362 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
363 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
364 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
365 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
366
367
368 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
369 FN_ADICLK_B, FN_MSIOF0_SS1_C,
370 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
371 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
372 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
373 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
374 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
375 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
376 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
377 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
378 FN_SCIFA5_TXD_B, FN_TX3_C,
379 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
380 FN_SCIFA5_RXD_B, FN_RX3_C,
381 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
382 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
383 FN_SD1_DATA3, FN_IERX_B,
384 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
385
386
387 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
388 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
389 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
390 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
391 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
392 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
393 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
394 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
395 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
396 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
397 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
398 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
399 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
400 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
401
402
403 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
404 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
405 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
406 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
407 FN_PWM5_B, FN_SCIFA3_TXD_C,
408 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
409 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
410 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
411 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
412 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
413 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
414 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
415 FN_TCLK2, FN_VI1_DATA3_C,
416 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
417 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
418
419
420 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
421 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
422 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
423 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
424 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
425
426
427 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
428 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
429 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
430 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
431 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
432 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
433 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
434 FN_SEL_QSP_0, FN_SEL_QSP_1,
435 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
436 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
437 FN_SEL_HSCIF1_4,
438 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
439 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
440 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
441 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
442 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
443
444
445 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
446 FN_SEL_SCIF0_4,
447 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
448 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
449 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
450 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
452 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
453 FN_SEL_ADG_0, FN_SEL_ADG_1,
454 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
455 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
456 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
457 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
458 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
459 FN_SEL_SIM_0, FN_SEL_SIM_1,
460 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
461
462
463 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
464 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
465 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
466 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
467 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
468 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
469 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
470 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
471 FN_SEL_MMC_0, FN_SEL_MMC_1,
472 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
473 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
474 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
475 FN_SEL_I2C1_4,
476 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
477
478
479 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
480 FN_SEL_SOF1_4,
481 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
482 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
483 FN_SEL_RAD_0, FN_SEL_RAD_1,
484 FN_SEL_RCN_0, FN_SEL_RCN_1,
485 FN_SEL_RSP_0, FN_SEL_RSP_1,
486 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
487 FN_SEL_SCIF2_4,
488 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
489 FN_SEL_SOF2_4,
490 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
491 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
492 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
493 PINMUX_FUNCTION_END,
494
495 PINMUX_MARK_BEGIN,
496
497 EX_CS0_N_MARK, RD_N_MARK,
498
499 AUDIO_CLKA_MARK,
500
501 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
502 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
503 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
504
505 SD1_CLK_MARK,
506
507 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
508 DU0_DOTCLKIN_MARK,
509
510
511 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
512 D6_MARK, D7_MARK, D8_MARK,
513 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
514 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
515 PWM2_B_MARK,
516 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
517 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
518 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
519
520
521 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
522 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
523 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
524 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
525 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
526 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
527 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
528 A15_MARK, BPFCLK_C_MARK,
529 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
530 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
531 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
532
533
534 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
535 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
536 A20_MARK, SPCLK_MARK,
537 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
538 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
539 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
540 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
541 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
542 RX1_MARK, SCIFA1_RXD_MARK,
543 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
544 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
545 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
546 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
547 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
548 ATAG0_N_MARK, EX_WAIT1_MARK,
549
550
551 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
552 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
553 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
554 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
555 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
556 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
557 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
558 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
559 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
560 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
561 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
562 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
563 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
564 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
565 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
566 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
567 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
568 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
569
570
571 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
572 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
573 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
574 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
575 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
576 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
577 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
578 HSCK1_E_MARK,
579 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
580 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
581 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
582 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
583 SSI_SCK4_MARK, GLO_SS_D_MARK,
584 SSI_WS4_MARK, GLO_RFON_D_MARK,
585 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
586 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
587 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
588
589
590 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
591 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
592 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
593 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
594 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
595 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
596 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
597 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
598 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
599 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
600 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
601 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
602 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
603 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
604 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
605
606
607 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
608 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
609 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
610 SCIFA2_RXD_MARK, FMIN_E_MARK,
611 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
612 IRQ0_MARK, SCIFB1_RXD_D_MARK,
613 IRQ1_MARK, SCIFB1_SCK_C_MARK,
614 IRQ2_MARK, SCIFB1_TXD_D_MARK,
615 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK,
616 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
617 MSIOF2_RXD_E_MARK,
618 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
619 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
620 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
621 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
622 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
623 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
624 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
625
626
627 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
628 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
629 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
630 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
631 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
632 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
633 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
634 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
635 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
636 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
637 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
638 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
639 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
640 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
641 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
642 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
643 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
644 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
645
646
647 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
648 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
649 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
650 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
651 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
652 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
653 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
654 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
655 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
656 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
657 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
658 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
659 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
660 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
661 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
662 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
663 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
664 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
665
666
667 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
668 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
669 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
670 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
671 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
672 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
673 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
674 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
675 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
676 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
677 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
678 DU1_DISP_MARK, QPOLA_MARK,
679 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
680 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
681 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
682 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
683 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
684 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
685 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
686 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
687
688
689 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
690 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
691 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
692 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
693 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
694 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
695 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
696 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
697 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
698 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
699 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
700 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
701 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
702 TS_SDATA0_C_MARK, ATACS11_N_MARK,
703 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
704 TS_SCK0_C_MARK, ATAG1_N_MARK,
705 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
706 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
707 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
708 I2C1_SCL_D_MARK,
709
710
711 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
712 I2C1_SDA_D_MARK,
713 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
714 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
715 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
716 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
717 TX4_B_MARK, SCIFA4_TXD_B_MARK,
718 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
719 RX4_B_MARK, SCIFA4_RXD_B_MARK,
720 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
721 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
722 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
723 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
724 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
725 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
726 VI1_DATA7_MARK, AVB_MDC_MARK,
727 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
728 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
729
730
731 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
732 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
733 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
734 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
735 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
736 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
737 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
738 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
739 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
740 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
741 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
742 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
743 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
744 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
745 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
746 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
747 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
748 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
749
750
751 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
752 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
753 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
754 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
755 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
756 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
757 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
758 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
759 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
760 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
761 SCIFA5_TXD_B_MARK, TX3_C_MARK,
762 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
763 SCIFA5_RXD_B_MARK, RX3_C_MARK,
764 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
765 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
766 SD1_DATA3_MARK, IERX_B_MARK,
767 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
768
769
770 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
771 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
772 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
773 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
774 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
775 SCIFA5_TXD_C_MARK,
776 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
777 SCIFA5_RXD_C_MARK,
778 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
779 VI1_CLK_C_MARK, VI1_G0_B_MARK,
780 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
781 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
782 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
783 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
784 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
785 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
786 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
787 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
788
789
790 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
791 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
792 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
793 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
794 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
795 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
796 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
797 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
798 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
799 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
800 TCLK1_MARK, VI1_DATA1_C_MARK,
801 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
802 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
803 TCLK2_MARK, VI1_DATA3_C_MARK,
804 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
805 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
806 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
807 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
808
809
810 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
811 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
812 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
813 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
814 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
815 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
816 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
817 PINMUX_MARK_END,
818};
819
820static const u16 pinmux_data[] = {
821 PINMUX_DATA_GP_ALL(),
822
823 PINMUX_SINGLE(EX_CS0_N),
824 PINMUX_SINGLE(RD_N),
825 PINMUX_SINGLE(AUDIO_CLKA),
826 PINMUX_SINGLE(VI0_CLK),
827 PINMUX_SINGLE(VI0_DATA0_VI0_B0),
828 PINMUX_SINGLE(VI0_DATA1_VI0_B1),
829 PINMUX_SINGLE(VI0_DATA2_VI0_B2),
830 PINMUX_SINGLE(VI0_DATA4_VI0_B4),
831 PINMUX_SINGLE(VI0_DATA5_VI0_B5),
832 PINMUX_SINGLE(VI0_DATA6_VI0_B6),
833 PINMUX_SINGLE(VI0_DATA7_VI0_B7),
834 PINMUX_SINGLE(USB0_PWEN),
835 PINMUX_SINGLE(USB0_OVC),
836 PINMUX_SINGLE(USB1_PWEN),
837 PINMUX_SINGLE(USB1_OVC),
838 PINMUX_SINGLE(DU0_DOTCLKIN),
839 PINMUX_SINGLE(SD1_CLK),
840
841
842 PINMUX_IPSR_GPSR(IP0_0, D0),
843 PINMUX_IPSR_GPSR(IP0_1, D1),
844 PINMUX_IPSR_GPSR(IP0_2, D2),
845 PINMUX_IPSR_GPSR(IP0_3, D3),
846 PINMUX_IPSR_GPSR(IP0_4, D4),
847 PINMUX_IPSR_GPSR(IP0_5, D5),
848 PINMUX_IPSR_GPSR(IP0_6, D6),
849 PINMUX_IPSR_GPSR(IP0_7, D7),
850 PINMUX_IPSR_GPSR(IP0_8, D8),
851 PINMUX_IPSR_GPSR(IP0_9, D9),
852 PINMUX_IPSR_GPSR(IP0_10, D10),
853 PINMUX_IPSR_GPSR(IP0_11, D11),
854 PINMUX_IPSR_GPSR(IP0_12, D12),
855 PINMUX_IPSR_GPSR(IP0_13, D13),
856 PINMUX_IPSR_GPSR(IP0_14, D14),
857 PINMUX_IPSR_GPSR(IP0_15, D15),
858 PINMUX_IPSR_GPSR(IP0_18_16, A0),
859 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
860 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
861 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
862 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
863 PINMUX_IPSR_GPSR(IP0_20_19, A1),
864 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
865 PINMUX_IPSR_GPSR(IP0_22_21, A2),
866 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
867 PINMUX_IPSR_GPSR(IP0_24_23, A3),
868 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
869 PINMUX_IPSR_GPSR(IP0_26_25, A4),
870 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
871 PINMUX_IPSR_GPSR(IP0_28_27, A5),
872 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
873 PINMUX_IPSR_GPSR(IP0_30_29, A6),
874 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
875
876
877 PINMUX_IPSR_GPSR(IP1_1_0, A7),
878 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
879 PINMUX_IPSR_GPSR(IP1_3_2, A8),
880 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
881 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
882 PINMUX_IPSR_GPSR(IP1_5_4, A9),
883 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
884 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
885 PINMUX_IPSR_GPSR(IP1_7_6, A10),
886 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
887 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
888 PINMUX_IPSR_GPSR(IP1_10_8, A11),
889 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
890 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
891 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
892 PINMUX_IPSR_GPSR(IP1_13_11, A12),
893 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
894 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
895 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
896 PINMUX_IPSR_GPSR(IP1_16_14, A13),
897 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
898 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
899 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
900 PINMUX_IPSR_GPSR(IP1_19_17, A14),
901 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
902 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
903 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
904 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
905 PINMUX_IPSR_GPSR(IP1_22_20, A15),
906 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
907 PINMUX_IPSR_GPSR(IP1_25_23, A16),
908 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
909 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
910 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
911 PINMUX_IPSR_GPSR(IP1_28_26, A17),
912 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
913 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
914 PINMUX_IPSR_GPSR(IP1_31_29, A18),
915 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
916 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
917 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
918
919
920 PINMUX_IPSR_GPSR(IP2_2_0, A19),
921 PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
922 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
923 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
924 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
925 PINMUX_IPSR_GPSR(IP2_2_0, A20),
926 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
927 PINMUX_IPSR_GPSR(IP2_6_5, A21),
928 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
929 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
930 PINMUX_IPSR_GPSR(IP2_9_7, A22),
931 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
932 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
933 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
934 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
935 PINMUX_IPSR_GPSR(IP2_12_10, A23),
936 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
937 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
938 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
939 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
940 PINMUX_IPSR_GPSR(IP2_15_13, A24),
941 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
942 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
943 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
944 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
945 PINMUX_IPSR_GPSR(IP2_18_16, A25),
946 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
947 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
948 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
949 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
950 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
951 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
952 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
953 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
954 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
955 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
956 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
957 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
958 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
959 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
960 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
961 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
962 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
963 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
964 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
965 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
966 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
967
968
969 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
970 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
971 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
972 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
973 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
974 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
975 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
976 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
977 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
978 PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
979 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
980 PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
981 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
982 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
983 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
984 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
985 PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
986 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
987 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
988 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
989 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
990 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
991 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
992 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
993 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
994 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
995 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
996 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
997 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
998 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
999 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
1000 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
1001 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1002 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
1003 PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
1004 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
1005 PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
1006 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
1007 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
1008 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
1009 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
1010 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
1011 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
1012 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
1013 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
1014 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
1015 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
1016 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
1017 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
1018 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
1019 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
1020 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
1021 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
1022 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
1023 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
1024 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
1025
1026
1027 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
1028 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1029 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1030 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1031 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1032 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1033 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1034 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1035 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1036 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1037 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1038 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1039 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1040 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1041 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1042 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1043 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1044 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1045 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1046 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1047 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1048 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1049 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1050 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1051 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1052 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1053 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1054 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1055 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1056 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1057 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1058 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1059 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1060 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1061 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1062 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1063 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1064 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1065 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1066 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1067 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1068 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1069 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1070 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1071 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1072 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1073 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1074 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1075
1076
1077 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1078 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1079 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1080 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1081 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1082 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1083 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1084 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1085 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1086 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1087 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1088 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1089 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1090 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1091 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1092 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1093 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1094 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1095 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1096 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1097 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1098 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1099 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1100 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1101 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1102 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1103 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1104 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1105 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1106 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1107 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1108 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1109 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1110 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1111 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1112 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1113 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1114 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1115 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1116 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1117 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1118 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1119 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1120 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1121 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1122 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1123 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1124 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1125 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1126
1127
1128 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1129 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1130 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1131 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1132 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1133 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1134 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1135 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1136 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1137 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1138 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1139 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1140 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1141 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1142 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1143 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1144 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1145 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1146 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1147 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1148 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1149 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1150 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1151 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1152 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1153 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1154 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1155 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1156 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1157 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1158 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1159 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1160 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1161 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1162 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1163 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1164 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1165 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1166 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1167 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1168 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1169 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1170 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1171 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1172 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1173 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1174 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1175 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1176
1177
1178 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1179 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1180 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1181 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1182 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1183 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1184 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1185 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1186 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1187 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1188 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1189 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1190 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1191 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1192 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1193 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1194 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1195 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1196 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1197 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1198 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1199 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1200 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1201 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1202 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1203 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1204 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1205 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1206 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1207 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1208 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1209 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1210 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1211 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1212 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1213 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1214 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1215 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1216 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1217 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1218 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1219 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1220 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1221 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1222 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1223 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1224 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1225 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1226 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1227 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1228 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1229 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1230 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1231 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1232
1233
1234 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1235 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1236 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1237 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1238 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1239 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1240 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1241 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1242 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1243 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1244 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1245 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1246 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1247 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1248 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1249 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1250 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1251 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1252 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1253 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1254 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1255 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1256 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1257 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1258 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1259 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1260 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1261 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1262 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1263 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1264 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1265 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1266 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1267 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1268 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1269 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1270 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1271 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1272 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1273 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1274 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1275 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1276 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1277 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1278 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1279 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1280 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1281 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1282 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1283 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1284 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1285 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1286 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1287 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1288 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1289 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1290
1291
1292 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1293 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1294 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1295 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1296 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1297 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1298 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1299 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1300 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1301 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1302 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1303 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1304 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1305 PINMUX_IPSR_GPSR(IP9_7, QCLK),
1306 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1307 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1308 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1309 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1310 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1311 PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1312 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1313 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1314 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1315 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1316 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1317 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1318 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1319 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1320 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1321 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1322 PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1323 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1324 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1325 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1326 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1327 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1328 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1329 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1330 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1331 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1332 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1333 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1334 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1335 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1336 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1337 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1338 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1339 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1340 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1341 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1342 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1343 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1344 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1345 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1346 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1347 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1348 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1349 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1351 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1352
1353
1354 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1355 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1356 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1357 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1358 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1359 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1360 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1361 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1362 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1363 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1364 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1365 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1366 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1367 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1368 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1369 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1370 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1371 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1372 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1373 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1374 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1375 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1376 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1377 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1378 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1379 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1380 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1381 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1382 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1383 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1384 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1385 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1386 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1387 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1388 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1389 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1390 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1391 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1392 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1393 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1394 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1395 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1396 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1397 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1398 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1399 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1400 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1401 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1402 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1403 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1404 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1405 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1406 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1407 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1408 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1409 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1410 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1411 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1412 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1413 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1414 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1415 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1416 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1417
1418
1419 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1420 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1421 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1422 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1423 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1424 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1425 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1426 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1427 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1428 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1429 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1430 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1431 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1432 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1433 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1434 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1435 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1436 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1437 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1438 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1439 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1440 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1441 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1442 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1443 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1444 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1445 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1446 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1447 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1448 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1449 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1450 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1451 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1452 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1453 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1454 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1455 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1456 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1457 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1458 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1459 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1460 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1461 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1462 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1463 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1464 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1465 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1466 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1467 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1468 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1469 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1470 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1471 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1472 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1473 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1474 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1475 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1476
1477
1478 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1479 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1480 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1481 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1482 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1483 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1484 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1485 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1486 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1487 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1488 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1489 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1490 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1491 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1492 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1493 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1494 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1495 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1496 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1497 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1498 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1499 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1500 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1501 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1502 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1503 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1504 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1505 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1506 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1507 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1508 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1509 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1510 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1511 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1512 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1513 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1514 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1515 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1516 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1517 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1518 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1519 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1520 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1521 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1522 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1523 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1524 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1525 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1526 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1527 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1528 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1529
1530
1531 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1532 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1533 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1534 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1535 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1536 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1537 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1538 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1539 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1540 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1541 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1542 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1543 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1544 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1545 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1546 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1547 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1548 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1549 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1550 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1551 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1552 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1553 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1554 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1555 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1556 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1557 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1558 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1559 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1560 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1561 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1562 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1563 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1564 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1565 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1566 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1567 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1568 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1569 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1570 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1571 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1572 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1573 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1574 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1575 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1576 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1577 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1578 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1579 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1580 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1581 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1582 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1583 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1584 PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1585 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1586 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1587
1588
1589 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1590 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1591 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1592 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1593 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1594 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1595 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1596 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1597 PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1598 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1599 PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1600 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1601 PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1602 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1603 PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1604 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1605 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1606 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1607 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1608 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1609 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1610 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1611 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1612 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1613 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1614 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1615 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1616 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1617 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1618 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1619 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1620 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1621 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1622 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1623 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1624 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1625 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1626 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1627 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1628 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1629 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1630 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1631 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1632 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1633 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1634 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1635 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1636 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1637 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1638 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1639 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1640 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1641 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1642 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1643 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1644 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1645 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1646
1647
1648 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1649 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1650 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1651 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1652 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1653 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1654 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1655 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1656 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1657 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1658 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1659 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1660 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1661 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1662 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1663 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1664 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1665 PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1666 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1667 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1668 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1669 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1670 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1671 PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1672 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1673 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1674 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1675 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1676 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1677 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1678 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1679 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1680 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1681 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1682 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1683 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1684 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1685 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1686 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1687 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1688 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1689 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1690 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1691 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1692 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1693 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1694 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1695 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1696 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1697 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1698 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1699
1700
1701 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1702 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1703 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1704 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1705 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1706 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1707 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1708 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1709 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1710 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1711 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1712 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1713 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1714 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1715 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1716 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1717 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1718 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1719 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1720 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1721 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1722 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1723};
1724
1725
1726
1727
1728enum {
1729 GP_ASSIGN_LAST(),
1730 NOGP_ALL(),
1731};
1732
1733static const struct sh_pfc_pin pinmux_pins[] = {
1734 PINMUX_GPIO_GP_ALL(),
1735 PINMUX_NOGP_ALL(),
1736};
1737
1738#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
1739
1740static const unsigned int adi_common_pins[] = {
1741
1742 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1743};
1744static const unsigned int adi_common_mux[] = {
1745
1746 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1747};
1748static const unsigned int adi_chsel0_pins[] = {
1749
1750 RCAR_GP_PIN(6, 27),
1751};
1752static const unsigned int adi_chsel0_mux[] = {
1753
1754 ADICHS0_MARK,
1755};
1756static const unsigned int adi_chsel1_pins[] = {
1757
1758 RCAR_GP_PIN(6, 28),
1759};
1760static const unsigned int adi_chsel1_mux[] = {
1761
1762 ADICHS1_MARK,
1763};
1764static const unsigned int adi_chsel2_pins[] = {
1765
1766 RCAR_GP_PIN(6, 29),
1767};
1768static const unsigned int adi_chsel2_mux[] = {
1769
1770 ADICHS2_MARK,
1771};
1772static const unsigned int adi_common_b_pins[] = {
1773
1774 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1775};
1776static const unsigned int adi_common_b_mux[] = {
1777
1778 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1779};
1780static const unsigned int adi_chsel0_b_pins[] = {
1781
1782 RCAR_GP_PIN(5, 28),
1783};
1784static const unsigned int adi_chsel0_b_mux[] = {
1785
1786 ADICHS0_B_MARK,
1787};
1788static const unsigned int adi_chsel1_b_pins[] = {
1789
1790 RCAR_GP_PIN(5, 29),
1791};
1792static const unsigned int adi_chsel1_b_mux[] = {
1793
1794 ADICHS1_B_MARK,
1795};
1796static const unsigned int adi_chsel2_b_pins[] = {
1797
1798 RCAR_GP_PIN(5, 30),
1799};
1800static const unsigned int adi_chsel2_b_mux[] = {
1801
1802 ADICHS2_B_MARK,
1803};
1804#endif
1805
1806
1807static const unsigned int audio_clk_a_pins[] = {
1808
1809 RCAR_GP_PIN(2, 28),
1810};
1811
1812static const unsigned int audio_clk_a_mux[] = {
1813 AUDIO_CLKA_MARK,
1814};
1815
1816static const unsigned int audio_clk_b_pins[] = {
1817
1818 RCAR_GP_PIN(2, 29),
1819};
1820
1821static const unsigned int audio_clk_b_mux[] = {
1822 AUDIO_CLKB_MARK,
1823};
1824
1825static const unsigned int audio_clk_b_b_pins[] = {
1826
1827 RCAR_GP_PIN(7, 20),
1828};
1829
1830static const unsigned int audio_clk_b_b_mux[] = {
1831 AUDIO_CLKB_B_MARK,
1832};
1833
1834static const unsigned int audio_clk_c_pins[] = {
1835
1836 RCAR_GP_PIN(2, 30),
1837};
1838
1839static const unsigned int audio_clk_c_mux[] = {
1840 AUDIO_CLKC_MARK,
1841};
1842
1843static const unsigned int audio_clkout_pins[] = {
1844
1845 RCAR_GP_PIN(2, 31),
1846};
1847
1848static const unsigned int audio_clkout_mux[] = {
1849 AUDIO_CLKOUT_MARK,
1850};
1851
1852
1853static const unsigned int avb_link_pins[] = {
1854 RCAR_GP_PIN(5, 14),
1855};
1856static const unsigned int avb_link_mux[] = {
1857 AVB_LINK_MARK,
1858};
1859static const unsigned int avb_magic_pins[] = {
1860 RCAR_GP_PIN(5, 11),
1861};
1862static const unsigned int avb_magic_mux[] = {
1863 AVB_MAGIC_MARK,
1864};
1865static const unsigned int avb_phy_int_pins[] = {
1866 RCAR_GP_PIN(5, 16),
1867};
1868static const unsigned int avb_phy_int_mux[] = {
1869 AVB_PHY_INT_MARK,
1870};
1871static const unsigned int avb_mdio_pins[] = {
1872 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1873};
1874static const unsigned int avb_mdio_mux[] = {
1875 AVB_MDC_MARK, AVB_MDIO_MARK,
1876};
1877static const unsigned int avb_mii_pins[] = {
1878 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1879 RCAR_GP_PIN(5, 21),
1880
1881 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1882 RCAR_GP_PIN(5, 3),
1883
1884 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1885 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1886 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1887};
1888static const unsigned int avb_mii_mux[] = {
1889 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1890 AVB_TXD3_MARK,
1891
1892 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1893 AVB_RXD3_MARK,
1894
1895 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1896 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1897 AVB_TX_CLK_MARK, AVB_COL_MARK,
1898};
1899static const unsigned int avb_gmii_pins[] = {
1900 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1901 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1902 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1903
1904 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1905 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1906 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1907
1908 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1909 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1910 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1911 RCAR_GP_PIN(5, 29),
1912};
1913static const unsigned int avb_gmii_mux[] = {
1914 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1915 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1916 AVB_TXD6_MARK, AVB_TXD7_MARK,
1917
1918 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1919 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1920 AVB_RXD6_MARK, AVB_RXD7_MARK,
1921
1922 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1923 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1924 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1925 AVB_COL_MARK,
1926};
1927
1928
1929
1930static const unsigned int can0_data_pins[] = {
1931
1932 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1933};
1934
1935static const unsigned int can0_data_mux[] = {
1936 CAN0_TX_MARK, CAN0_RX_MARK,
1937};
1938
1939static const unsigned int can0_data_b_pins[] = {
1940
1941 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1942};
1943
1944static const unsigned int can0_data_b_mux[] = {
1945 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1946};
1947
1948static const unsigned int can0_data_c_pins[] = {
1949
1950 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1951};
1952
1953static const unsigned int can0_data_c_mux[] = {
1954 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1955};
1956
1957static const unsigned int can0_data_d_pins[] = {
1958
1959 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1960};
1961
1962static const unsigned int can0_data_d_mux[] = {
1963 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1964};
1965
1966static const unsigned int can0_data_e_pins[] = {
1967
1968 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1969};
1970
1971static const unsigned int can0_data_e_mux[] = {
1972 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1973};
1974
1975static const unsigned int can0_data_f_pins[] = {
1976
1977 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1978};
1979
1980static const unsigned int can0_data_f_mux[] = {
1981 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1982};
1983
1984static const unsigned int can1_data_pins[] = {
1985
1986 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1987};
1988
1989static const unsigned int can1_data_mux[] = {
1990 CAN1_TX_MARK, CAN1_RX_MARK,
1991};
1992
1993static const unsigned int can1_data_b_pins[] = {
1994
1995 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1996};
1997
1998static const unsigned int can1_data_b_mux[] = {
1999 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
2000};
2001
2002static const unsigned int can1_data_c_pins[] = {
2003
2004 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
2005};
2006
2007static const unsigned int can1_data_c_mux[] = {
2008 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
2009};
2010
2011static const unsigned int can1_data_d_pins[] = {
2012
2013 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
2014};
2015
2016static const unsigned int can1_data_d_mux[] = {
2017 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
2018};
2019
2020static const unsigned int can_clk_pins[] = {
2021
2022 RCAR_GP_PIN(7, 2),
2023};
2024
2025static const unsigned int can_clk_mux[] = {
2026 CAN_CLK_MARK,
2027};
2028
2029static const unsigned int can_clk_b_pins[] = {
2030
2031 RCAR_GP_PIN(5, 21),
2032};
2033
2034static const unsigned int can_clk_b_mux[] = {
2035 CAN_CLK_B_MARK,
2036};
2037
2038static const unsigned int can_clk_c_pins[] = {
2039
2040 RCAR_GP_PIN(4, 30),
2041};
2042
2043static const unsigned int can_clk_c_mux[] = {
2044 CAN_CLK_C_MARK,
2045};
2046
2047static const unsigned int can_clk_d_pins[] = {
2048
2049 RCAR_GP_PIN(7, 19),
2050};
2051
2052static const unsigned int can_clk_d_mux[] = {
2053 CAN_CLK_D_MARK,
2054};
2055
2056
2057static const unsigned int du_rgb666_pins[] = {
2058
2059 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2060 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2061 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2062 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2063 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2064 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2065};
2066static const unsigned int du_rgb666_mux[] = {
2067 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2068 DU1_DR3_MARK, DU1_DR2_MARK,
2069 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2070 DU1_DG3_MARK, DU1_DG2_MARK,
2071 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2072 DU1_DB3_MARK, DU1_DB2_MARK,
2073};
2074static const unsigned int du_rgb888_pins[] = {
2075
2076 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2077 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2078 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2079 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2080 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2081 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2082 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2083 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2084 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2085};
2086static const unsigned int du_rgb888_mux[] = {
2087 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2088 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2089 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2090 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2091 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2092 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2093};
2094static const unsigned int du_clk_out_0_pins[] = {
2095
2096 RCAR_GP_PIN(3, 25),
2097};
2098static const unsigned int du_clk_out_0_mux[] = {
2099 DU1_DOTCLKOUT0_MARK
2100};
2101static const unsigned int du_clk_out_1_pins[] = {
2102
2103 RCAR_GP_PIN(3, 26),
2104};
2105static const unsigned int du_clk_out_1_mux[] = {
2106 DU1_DOTCLKOUT1_MARK
2107};
2108static const unsigned int du_sync_pins[] = {
2109
2110 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2111};
2112static const unsigned int du_sync_mux[] = {
2113 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2114};
2115static const unsigned int du_oddf_pins[] = {
2116
2117 RCAR_GP_PIN(3, 29),
2118};
2119static const unsigned int du_oddf_mux[] = {
2120 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2121};
2122static const unsigned int du_cde_pins[] = {
2123
2124 RCAR_GP_PIN(3, 31),
2125};
2126static const unsigned int du_cde_mux[] = {
2127 DU1_CDE_MARK,
2128};
2129static const unsigned int du_disp_pins[] = {
2130
2131 RCAR_GP_PIN(3, 30),
2132};
2133static const unsigned int du_disp_mux[] = {
2134 DU1_DISP_MARK,
2135};
2136static const unsigned int du0_clk_in_pins[] = {
2137
2138 RCAR_GP_PIN(6, 31),
2139};
2140static const unsigned int du0_clk_in_mux[] = {
2141 DU0_DOTCLKIN_MARK
2142};
2143static const unsigned int du1_clk_in_pins[] = {
2144
2145 RCAR_GP_PIN(3, 24),
2146};
2147static const unsigned int du1_clk_in_mux[] = {
2148 DU1_DOTCLKIN_MARK
2149};
2150static const unsigned int du1_clk_in_b_pins[] = {
2151
2152 RCAR_GP_PIN(7, 19),
2153};
2154static const unsigned int du1_clk_in_b_mux[] = {
2155 DU1_DOTCLKIN_B_MARK,
2156};
2157static const unsigned int du1_clk_in_c_pins[] = {
2158
2159 RCAR_GP_PIN(7, 20),
2160};
2161static const unsigned int du1_clk_in_c_mux[] = {
2162 DU1_DOTCLKIN_C_MARK,
2163};
2164
2165static const unsigned int eth_link_pins[] = {
2166
2167 RCAR_GP_PIN(5, 18),
2168};
2169static const unsigned int eth_link_mux[] = {
2170 ETH_LINK_MARK,
2171};
2172static const unsigned int eth_magic_pins[] = {
2173
2174 RCAR_GP_PIN(5, 22),
2175};
2176static const unsigned int eth_magic_mux[] = {
2177 ETH_MAGIC_MARK,
2178};
2179static const unsigned int eth_mdio_pins[] = {
2180
2181 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2182};
2183static const unsigned int eth_mdio_mux[] = {
2184 ETH_MDC_MARK, ETH_MDIO_MARK,
2185};
2186static const unsigned int eth_rmii_pins[] = {
2187
2188 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2189 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2190 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2191};
2192static const unsigned int eth_rmii_mux[] = {
2193 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2194 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2195};
2196
2197
2198static const unsigned int hscif0_data_pins[] = {
2199
2200 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2201};
2202static const unsigned int hscif0_data_mux[] = {
2203 HRX0_MARK, HTX0_MARK,
2204};
2205static const unsigned int hscif0_clk_pins[] = {
2206
2207 RCAR_GP_PIN(7, 2),
2208};
2209static const unsigned int hscif0_clk_mux[] = {
2210 HSCK0_MARK,
2211};
2212static const unsigned int hscif0_ctrl_pins[] = {
2213
2214 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2215};
2216static const unsigned int hscif0_ctrl_mux[] = {
2217 HRTS0_N_MARK, HCTS0_N_MARK,
2218};
2219static const unsigned int hscif0_data_b_pins[] = {
2220
2221 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2222};
2223static const unsigned int hscif0_data_b_mux[] = {
2224 HRX0_B_MARK, HTX0_B_MARK,
2225};
2226static const unsigned int hscif0_ctrl_b_pins[] = {
2227
2228 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2229};
2230static const unsigned int hscif0_ctrl_b_mux[] = {
2231 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2232};
2233static const unsigned int hscif0_data_c_pins[] = {
2234
2235 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2236};
2237static const unsigned int hscif0_data_c_mux[] = {
2238 HRX0_C_MARK, HTX0_C_MARK,
2239};
2240static const unsigned int hscif0_clk_c_pins[] = {
2241
2242 RCAR_GP_PIN(5, 31),
2243};
2244static const unsigned int hscif0_clk_c_mux[] = {
2245 HSCK0_C_MARK,
2246};
2247
2248static const unsigned int hscif1_data_pins[] = {
2249
2250 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2251};
2252static const unsigned int hscif1_data_mux[] = {
2253 HRX1_MARK, HTX1_MARK,
2254};
2255static const unsigned int hscif1_clk_pins[] = {
2256
2257 RCAR_GP_PIN(7, 7),
2258};
2259static const unsigned int hscif1_clk_mux[] = {
2260 HSCK1_MARK,
2261};
2262static const unsigned int hscif1_ctrl_pins[] = {
2263
2264 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2265};
2266static const unsigned int hscif1_ctrl_mux[] = {
2267 HRTS1_N_MARK, HCTS1_N_MARK,
2268};
2269static const unsigned int hscif1_data_b_pins[] = {
2270
2271 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2272};
2273static const unsigned int hscif1_data_b_mux[] = {
2274 HRX1_B_MARK, HTX1_B_MARK,
2275};
2276static const unsigned int hscif1_data_c_pins[] = {
2277
2278 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2279};
2280static const unsigned int hscif1_data_c_mux[] = {
2281 HRX1_C_MARK, HTX1_C_MARK,
2282};
2283static const unsigned int hscif1_clk_c_pins[] = {
2284
2285 RCAR_GP_PIN(7, 16),
2286};
2287static const unsigned int hscif1_clk_c_mux[] = {
2288 HSCK1_C_MARK,
2289};
2290static const unsigned int hscif1_ctrl_c_pins[] = {
2291
2292 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2293};
2294static const unsigned int hscif1_ctrl_c_mux[] = {
2295 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2296};
2297static const unsigned int hscif1_data_d_pins[] = {
2298
2299 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2300};
2301static const unsigned int hscif1_data_d_mux[] = {
2302 HRX1_D_MARK, HTX1_D_MARK,
2303};
2304static const unsigned int hscif1_clk_e_pins[] = {
2305
2306 RCAR_GP_PIN(2, 6),
2307};
2308static const unsigned int hscif1_clk_e_mux[] = {
2309 HSCK1_E_MARK,
2310};
2311static const unsigned int hscif1_ctrl_e_pins[] = {
2312
2313 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2314};
2315static const unsigned int hscif1_ctrl_e_mux[] = {
2316 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2317};
2318
2319static const unsigned int hscif2_data_pins[] = {
2320
2321 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2322};
2323static const unsigned int hscif2_data_mux[] = {
2324 HRX2_MARK, HTX2_MARK,
2325};
2326static const unsigned int hscif2_clk_pins[] = {
2327
2328 RCAR_GP_PIN(4, 15),
2329};
2330static const unsigned int hscif2_clk_mux[] = {
2331 HSCK2_MARK,
2332};
2333static const unsigned int hscif2_ctrl_pins[] = {
2334
2335 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2336};
2337static const unsigned int hscif2_ctrl_mux[] = {
2338 HRTS2_N_MARK, HCTS2_N_MARK,
2339};
2340static const unsigned int hscif2_data_b_pins[] = {
2341
2342 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2343};
2344static const unsigned int hscif2_data_b_mux[] = {
2345 HRX2_B_MARK, HTX2_B_MARK,
2346};
2347static const unsigned int hscif2_ctrl_b_pins[] = {
2348
2349 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2350};
2351static const unsigned int hscif2_ctrl_b_mux[] = {
2352 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2353};
2354static const unsigned int hscif2_data_c_pins[] = {
2355
2356 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2357};
2358static const unsigned int hscif2_data_c_mux[] = {
2359 HRX2_C_MARK, HTX2_C_MARK,
2360};
2361static const unsigned int hscif2_clk_c_pins[] = {
2362
2363 RCAR_GP_PIN(5, 31),
2364};
2365static const unsigned int hscif2_clk_c_mux[] = {
2366 HSCK2_C_MARK,
2367};
2368static const unsigned int hscif2_data_d_pins[] = {
2369
2370 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2371};
2372static const unsigned int hscif2_data_d_mux[] = {
2373 HRX2_B_MARK, HTX2_D_MARK,
2374};
2375
2376static const unsigned int i2c0_pins[] = {
2377
2378 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2379};
2380static const unsigned int i2c0_mux[] = {
2381 I2C0_SCL_MARK, I2C0_SDA_MARK,
2382};
2383static const unsigned int i2c0_b_pins[] = {
2384
2385 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2386};
2387static const unsigned int i2c0_b_mux[] = {
2388 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2389};
2390static const unsigned int i2c0_c_pins[] = {
2391
2392 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2393};
2394static const unsigned int i2c0_c_mux[] = {
2395 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2396};
2397
2398static const unsigned int i2c1_pins[] = {
2399
2400 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2401};
2402static const unsigned int i2c1_mux[] = {
2403 I2C1_SCL_MARK, I2C1_SDA_MARK,
2404};
2405static const unsigned int i2c1_b_pins[] = {
2406
2407 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2408};
2409static const unsigned int i2c1_b_mux[] = {
2410 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2411};
2412static const unsigned int i2c1_c_pins[] = {
2413
2414 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2415};
2416static const unsigned int i2c1_c_mux[] = {
2417 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2418};
2419static const unsigned int i2c1_d_pins[] = {
2420
2421 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2422};
2423static const unsigned int i2c1_d_mux[] = {
2424 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2425};
2426static const unsigned int i2c1_e_pins[] = {
2427
2428 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2429};
2430static const unsigned int i2c1_e_mux[] = {
2431 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2432};
2433
2434static const unsigned int i2c2_pins[] = {
2435
2436 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2437};
2438static const unsigned int i2c2_mux[] = {
2439 I2C2_SCL_MARK, I2C2_SDA_MARK,
2440};
2441static const unsigned int i2c2_b_pins[] = {
2442
2443 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2444};
2445static const unsigned int i2c2_b_mux[] = {
2446 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2447};
2448static const unsigned int i2c2_c_pins[] = {
2449
2450 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2451};
2452static const unsigned int i2c2_c_mux[] = {
2453 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2454};
2455static const unsigned int i2c2_d_pins[] = {
2456
2457 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2458};
2459static const unsigned int i2c2_d_mux[] = {
2460 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2461};
2462
2463static const unsigned int i2c3_pins[] = {
2464
2465 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2466};
2467static const unsigned int i2c3_mux[] = {
2468 I2C3_SCL_MARK, I2C3_SDA_MARK,
2469};
2470static const unsigned int i2c3_b_pins[] = {
2471
2472 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2473};
2474static const unsigned int i2c3_b_mux[] = {
2475 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2476};
2477static const unsigned int i2c3_c_pins[] = {
2478
2479 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2480};
2481static const unsigned int i2c3_c_mux[] = {
2482 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2483};
2484static const unsigned int i2c3_d_pins[] = {
2485
2486 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2487};
2488static const unsigned int i2c3_d_mux[] = {
2489 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2490};
2491
2492static const unsigned int i2c4_pins[] = {
2493
2494 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2495};
2496static const unsigned int i2c4_mux[] = {
2497 I2C4_SCL_MARK, I2C4_SDA_MARK,
2498};
2499static const unsigned int i2c4_b_pins[] = {
2500
2501 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2502};
2503static const unsigned int i2c4_b_mux[] = {
2504 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2505};
2506static const unsigned int i2c4_c_pins[] = {
2507
2508 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2509};
2510static const unsigned int i2c4_c_mux[] = {
2511 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2512};
2513
2514static const unsigned int i2c7_pins[] = {
2515
2516 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2517};
2518static const unsigned int i2c7_mux[] = {
2519 IIC0_SCL_MARK, IIC0_SDA_MARK,
2520};
2521static const unsigned int i2c7_b_pins[] = {
2522
2523 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2524};
2525static const unsigned int i2c7_b_mux[] = {
2526 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2527};
2528static const unsigned int i2c7_c_pins[] = {
2529
2530 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2531};
2532static const unsigned int i2c7_c_mux[] = {
2533 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2534};
2535
2536static const unsigned int i2c8_pins[] = {
2537
2538 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2539};
2540static const unsigned int i2c8_mux[] = {
2541 IIC1_SCL_MARK, IIC1_SDA_MARK,
2542};
2543static const unsigned int i2c8_b_pins[] = {
2544
2545 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2546};
2547static const unsigned int i2c8_b_mux[] = {
2548 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2549};
2550static const unsigned int i2c8_c_pins[] = {
2551
2552 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2553};
2554static const unsigned int i2c8_c_mux[] = {
2555 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2556};
2557
2558static const unsigned int intc_irq0_pins[] = {
2559
2560 RCAR_GP_PIN(7, 10),
2561};
2562static const unsigned int intc_irq0_mux[] = {
2563 IRQ0_MARK,
2564};
2565static const unsigned int intc_irq1_pins[] = {
2566
2567 RCAR_GP_PIN(7, 11),
2568};
2569static const unsigned int intc_irq1_mux[] = {
2570 IRQ1_MARK,
2571};
2572static const unsigned int intc_irq2_pins[] = {
2573
2574 RCAR_GP_PIN(7, 12),
2575};
2576static const unsigned int intc_irq2_mux[] = {
2577 IRQ2_MARK,
2578};
2579static const unsigned int intc_irq3_pins[] = {
2580
2581 RCAR_GP_PIN(7, 13),
2582};
2583static const unsigned int intc_irq3_mux[] = {
2584 IRQ3_MARK,
2585};
2586
2587#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
2588
2589static const unsigned int mlb_3pin_pins[] = {
2590 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2591};
2592static const unsigned int mlb_3pin_mux[] = {
2593 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2594};
2595#endif
2596
2597
2598static const unsigned int mmc_data_pins[] = {
2599
2600 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2601 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2602 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2603 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2604};
2605static const unsigned int mmc_data_mux[] = {
2606 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2607 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2608};
2609static const unsigned int mmc_data_b_pins[] = {
2610
2611 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2612 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2613 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2614 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2615};
2616static const unsigned int mmc_data_b_mux[] = {
2617 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2618 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2619};
2620static const unsigned int mmc_ctrl_pins[] = {
2621
2622 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2623};
2624static const unsigned int mmc_ctrl_mux[] = {
2625 MMC_CLK_MARK, MMC_CMD_MARK,
2626};
2627
2628static const unsigned int msiof0_clk_pins[] = {
2629
2630 RCAR_GP_PIN(6, 24),
2631};
2632static const unsigned int msiof0_clk_mux[] = {
2633 MSIOF0_SCK_MARK,
2634};
2635static const unsigned int msiof0_sync_pins[] = {
2636
2637 RCAR_GP_PIN(6, 25),
2638};
2639static const unsigned int msiof0_sync_mux[] = {
2640 MSIOF0_SYNC_MARK,
2641};
2642static const unsigned int msiof0_ss1_pins[] = {
2643
2644 RCAR_GP_PIN(6, 28),
2645};
2646static const unsigned int msiof0_ss1_mux[] = {
2647 MSIOF0_SS1_MARK,
2648};
2649static const unsigned int msiof0_ss2_pins[] = {
2650
2651 RCAR_GP_PIN(6, 29),
2652};
2653static const unsigned int msiof0_ss2_mux[] = {
2654 MSIOF0_SS2_MARK,
2655};
2656static const unsigned int msiof0_rx_pins[] = {
2657
2658 RCAR_GP_PIN(6, 27),
2659};
2660static const unsigned int msiof0_rx_mux[] = {
2661 MSIOF0_RXD_MARK,
2662};
2663static const unsigned int msiof0_tx_pins[] = {
2664
2665 RCAR_GP_PIN(6, 26),
2666};
2667static const unsigned int msiof0_tx_mux[] = {
2668 MSIOF0_TXD_MARK,
2669};
2670
2671static const unsigned int msiof0_clk_b_pins[] = {
2672
2673 RCAR_GP_PIN(0, 16),
2674};
2675static const unsigned int msiof0_clk_b_mux[] = {
2676 MSIOF0_SCK_B_MARK,
2677};
2678static const unsigned int msiof0_sync_b_pins[] = {
2679
2680 RCAR_GP_PIN(0, 17),
2681};
2682static const unsigned int msiof0_sync_b_mux[] = {
2683 MSIOF0_SYNC_B_MARK,
2684};
2685static const unsigned int msiof0_ss1_b_pins[] = {
2686
2687 RCAR_GP_PIN(0, 18),
2688};
2689static const unsigned int msiof0_ss1_b_mux[] = {
2690 MSIOF0_SS1_B_MARK,
2691};
2692static const unsigned int msiof0_ss2_b_pins[] = {
2693
2694 RCAR_GP_PIN(0, 19),
2695};
2696static const unsigned int msiof0_ss2_b_mux[] = {
2697 MSIOF0_SS2_B_MARK,
2698};
2699static const unsigned int msiof0_rx_b_pins[] = {
2700
2701 RCAR_GP_PIN(0, 21),
2702};
2703static const unsigned int msiof0_rx_b_mux[] = {
2704 MSIOF0_RXD_B_MARK,
2705};
2706static const unsigned int msiof0_tx_b_pins[] = {
2707
2708 RCAR_GP_PIN(0, 20),
2709};
2710static const unsigned int msiof0_tx_b_mux[] = {
2711 MSIOF0_TXD_B_MARK,
2712};
2713
2714static const unsigned int msiof0_clk_c_pins[] = {
2715
2716 RCAR_GP_PIN(5, 26),
2717};
2718static const unsigned int msiof0_clk_c_mux[] = {
2719 MSIOF0_SCK_C_MARK,
2720};
2721static const unsigned int msiof0_sync_c_pins[] = {
2722
2723 RCAR_GP_PIN(5, 25),
2724};
2725static const unsigned int msiof0_sync_c_mux[] = {
2726 MSIOF0_SYNC_C_MARK,
2727};
2728static const unsigned int msiof0_ss1_c_pins[] = {
2729
2730 RCAR_GP_PIN(5, 27),
2731};
2732static const unsigned int msiof0_ss1_c_mux[] = {
2733 MSIOF0_SS1_C_MARK,
2734};
2735static const unsigned int msiof0_ss2_c_pins[] = {
2736
2737 RCAR_GP_PIN(5, 28),
2738};
2739static const unsigned int msiof0_ss2_c_mux[] = {
2740 MSIOF0_SS2_C_MARK,
2741};
2742static const unsigned int msiof0_rx_c_pins[] = {
2743
2744 RCAR_GP_PIN(5, 29),
2745};
2746static const unsigned int msiof0_rx_c_mux[] = {
2747 MSIOF0_RXD_C_MARK,
2748};
2749static const unsigned int msiof0_tx_c_pins[] = {
2750
2751 RCAR_GP_PIN(5, 30),
2752};
2753static const unsigned int msiof0_tx_c_mux[] = {
2754 MSIOF0_TXD_C_MARK,
2755};
2756
2757static const unsigned int msiof1_clk_pins[] = {
2758
2759 RCAR_GP_PIN(0, 22),
2760};
2761static const unsigned int msiof1_clk_mux[] = {
2762 MSIOF1_SCK_MARK,
2763};
2764static const unsigned int msiof1_sync_pins[] = {
2765
2766 RCAR_GP_PIN(0, 23),
2767};
2768static const unsigned int msiof1_sync_mux[] = {
2769 MSIOF1_SYNC_MARK,
2770};
2771static const unsigned int msiof1_ss1_pins[] = {
2772
2773 RCAR_GP_PIN(0, 24),
2774};
2775static const unsigned int msiof1_ss1_mux[] = {
2776 MSIOF1_SS1_MARK,
2777};
2778static const unsigned int msiof1_ss2_pins[] = {
2779
2780 RCAR_GP_PIN(0, 25),
2781};
2782static const unsigned int msiof1_ss2_mux[] = {
2783 MSIOF1_SS2_MARK,
2784};
2785static const unsigned int msiof1_rx_pins[] = {
2786
2787 RCAR_GP_PIN(0, 27),
2788};
2789static const unsigned int msiof1_rx_mux[] = {
2790 MSIOF1_RXD_MARK,
2791};
2792static const unsigned int msiof1_tx_pins[] = {
2793
2794 RCAR_GP_PIN(0, 26),
2795};
2796static const unsigned int msiof1_tx_mux[] = {
2797 MSIOF1_TXD_MARK,
2798};
2799
2800static const unsigned int msiof1_clk_b_pins[] = {
2801
2802 RCAR_GP_PIN(2, 29),
2803};
2804static const unsigned int msiof1_clk_b_mux[] = {
2805 MSIOF1_SCK_B_MARK,
2806};
2807static const unsigned int msiof1_sync_b_pins[] = {
2808
2809 RCAR_GP_PIN(2, 30),
2810};
2811static const unsigned int msiof1_sync_b_mux[] = {
2812 MSIOF1_SYNC_B_MARK,
2813};
2814static const unsigned int msiof1_ss1_b_pins[] = {
2815
2816 RCAR_GP_PIN(2, 31),
2817};
2818static const unsigned int msiof1_ss1_b_mux[] = {
2819 MSIOF1_SS1_B_MARK,
2820};
2821static const unsigned int msiof1_ss2_b_pins[] = {
2822
2823 RCAR_GP_PIN(7, 16),
2824};
2825static const unsigned int msiof1_ss2_b_mux[] = {
2826 MSIOF1_SS2_B_MARK,
2827};
2828static const unsigned int msiof1_rx_b_pins[] = {
2829
2830 RCAR_GP_PIN(7, 18),
2831};
2832static const unsigned int msiof1_rx_b_mux[] = {
2833 MSIOF1_RXD_B_MARK,
2834};
2835static const unsigned int msiof1_tx_b_pins[] = {
2836
2837 RCAR_GP_PIN(7, 17),
2838};
2839static const unsigned int msiof1_tx_b_mux[] = {
2840 MSIOF1_TXD_B_MARK,
2841};
2842
2843static const unsigned int msiof1_clk_c_pins[] = {
2844
2845 RCAR_GP_PIN(2, 15),
2846};
2847static const unsigned int msiof1_clk_c_mux[] = {
2848 MSIOF1_SCK_C_MARK,
2849};
2850static const unsigned int msiof1_sync_c_pins[] = {
2851
2852 RCAR_GP_PIN(2, 16),
2853};
2854static const unsigned int msiof1_sync_c_mux[] = {
2855 MSIOF1_SYNC_C_MARK,
2856};
2857static const unsigned int msiof1_rx_c_pins[] = {
2858
2859 RCAR_GP_PIN(2, 18),
2860};
2861static const unsigned int msiof1_rx_c_mux[] = {
2862 MSIOF1_RXD_C_MARK,
2863};
2864static const unsigned int msiof1_tx_c_pins[] = {
2865
2866 RCAR_GP_PIN(2, 17),
2867};
2868static const unsigned int msiof1_tx_c_mux[] = {
2869 MSIOF1_TXD_C_MARK,
2870};
2871
2872static const unsigned int msiof1_clk_d_pins[] = {
2873
2874 RCAR_GP_PIN(0, 28),
2875};
2876static const unsigned int msiof1_clk_d_mux[] = {
2877 MSIOF1_SCK_D_MARK,
2878};
2879static const unsigned int msiof1_sync_d_pins[] = {
2880
2881 RCAR_GP_PIN(0, 30),
2882};
2883static const unsigned int msiof1_sync_d_mux[] = {
2884 MSIOF1_SYNC_D_MARK,
2885};
2886static const unsigned int msiof1_ss1_d_pins[] = {
2887
2888 RCAR_GP_PIN(0, 29),
2889};
2890static const unsigned int msiof1_ss1_d_mux[] = {
2891 MSIOF1_SS1_D_MARK,
2892};
2893static const unsigned int msiof1_rx_d_pins[] = {
2894
2895 RCAR_GP_PIN(0, 27),
2896};
2897static const unsigned int msiof1_rx_d_mux[] = {
2898 MSIOF1_RXD_D_MARK,
2899};
2900static const unsigned int msiof1_tx_d_pins[] = {
2901
2902 RCAR_GP_PIN(0, 26),
2903};
2904static const unsigned int msiof1_tx_d_mux[] = {
2905 MSIOF1_TXD_D_MARK,
2906};
2907
2908static const unsigned int msiof1_clk_e_pins[] = {
2909
2910 RCAR_GP_PIN(5, 18),
2911};
2912static const unsigned int msiof1_clk_e_mux[] = {
2913 MSIOF1_SCK_E_MARK,
2914};
2915static const unsigned int msiof1_sync_e_pins[] = {
2916
2917 RCAR_GP_PIN(5, 19),
2918};
2919static const unsigned int msiof1_sync_e_mux[] = {
2920 MSIOF1_SYNC_E_MARK,
2921};
2922static const unsigned int msiof1_rx_e_pins[] = {
2923
2924 RCAR_GP_PIN(5, 17),
2925};
2926static const unsigned int msiof1_rx_e_mux[] = {
2927 MSIOF1_RXD_E_MARK,
2928};
2929static const unsigned int msiof1_tx_e_pins[] = {
2930
2931 RCAR_GP_PIN(5, 20),
2932};
2933static const unsigned int msiof1_tx_e_mux[] = {
2934 MSIOF1_TXD_E_MARK,
2935};
2936
2937static const unsigned int msiof2_clk_pins[] = {
2938
2939 RCAR_GP_PIN(1, 13),
2940};
2941static const unsigned int msiof2_clk_mux[] = {
2942 MSIOF2_SCK_MARK,
2943};
2944static const unsigned int msiof2_sync_pins[] = {
2945
2946 RCAR_GP_PIN(1, 14),
2947};
2948static const unsigned int msiof2_sync_mux[] = {
2949 MSIOF2_SYNC_MARK,
2950};
2951static const unsigned int msiof2_ss1_pins[] = {
2952
2953 RCAR_GP_PIN(1, 17),
2954};
2955static const unsigned int msiof2_ss1_mux[] = {
2956 MSIOF2_SS1_MARK,
2957};
2958static const unsigned int msiof2_ss2_pins[] = {
2959
2960 RCAR_GP_PIN(1, 18),
2961};
2962static const unsigned int msiof2_ss2_mux[] = {
2963 MSIOF2_SS2_MARK,
2964};
2965static const unsigned int msiof2_rx_pins[] = {
2966
2967 RCAR_GP_PIN(1, 16),
2968};
2969static const unsigned int msiof2_rx_mux[] = {
2970 MSIOF2_RXD_MARK,
2971};
2972static const unsigned int msiof2_tx_pins[] = {
2973
2974 RCAR_GP_PIN(1, 15),
2975};
2976static const unsigned int msiof2_tx_mux[] = {
2977 MSIOF2_TXD_MARK,
2978};
2979
2980static const unsigned int msiof2_clk_b_pins[] = {
2981
2982 RCAR_GP_PIN(3, 0),
2983};
2984static const unsigned int msiof2_clk_b_mux[] = {
2985 MSIOF2_SCK_B_MARK,
2986};
2987static const unsigned int msiof2_sync_b_pins[] = {
2988
2989 RCAR_GP_PIN(3, 1),
2990};
2991static const unsigned int msiof2_sync_b_mux[] = {
2992 MSIOF2_SYNC_B_MARK,
2993};
2994static const unsigned int msiof2_ss1_b_pins[] = {
2995
2996 RCAR_GP_PIN(3, 8),
2997};
2998static const unsigned int msiof2_ss1_b_mux[] = {
2999 MSIOF2_SS1_B_MARK,
3000};
3001static const unsigned int msiof2_ss2_b_pins[] = {
3002
3003 RCAR_GP_PIN(3, 9),
3004};
3005static const unsigned int msiof2_ss2_b_mux[] = {
3006 MSIOF2_SS2_B_MARK,
3007};
3008static const unsigned int msiof2_rx_b_pins[] = {
3009
3010 RCAR_GP_PIN(3, 17),
3011};
3012static const unsigned int msiof2_rx_b_mux[] = {
3013 MSIOF2_RXD_B_MARK,
3014};
3015static const unsigned int msiof2_tx_b_pins[] = {
3016
3017 RCAR_GP_PIN(3, 16),
3018};
3019static const unsigned int msiof2_tx_b_mux[] = {
3020 MSIOF2_TXD_B_MARK,
3021};
3022
3023static const unsigned int msiof2_clk_c_pins[] = {
3024
3025 RCAR_GP_PIN(2, 2),
3026};
3027static const unsigned int msiof2_clk_c_mux[] = {
3028 MSIOF2_SCK_C_MARK,
3029};
3030static const unsigned int msiof2_sync_c_pins[] = {
3031
3032 RCAR_GP_PIN(2, 3),
3033};
3034static const unsigned int msiof2_sync_c_mux[] = {
3035 MSIOF2_SYNC_C_MARK,
3036};
3037static const unsigned int msiof2_rx_c_pins[] = {
3038
3039 RCAR_GP_PIN(2, 5),
3040};
3041static const unsigned int msiof2_rx_c_mux[] = {
3042 MSIOF2_RXD_C_MARK,
3043};
3044static const unsigned int msiof2_tx_c_pins[] = {
3045
3046 RCAR_GP_PIN(2, 4),
3047};
3048static const unsigned int msiof2_tx_c_mux[] = {
3049 MSIOF2_TXD_C_MARK,
3050};
3051
3052static const unsigned int msiof2_clk_d_pins[] = {
3053
3054 RCAR_GP_PIN(2, 14),
3055};
3056static const unsigned int msiof2_clk_d_mux[] = {
3057 MSIOF2_SCK_D_MARK,
3058};
3059static const unsigned int msiof2_sync_d_pins[] = {
3060
3061 RCAR_GP_PIN(2, 15),
3062};
3063static const unsigned int msiof2_sync_d_mux[] = {
3064 MSIOF2_SYNC_D_MARK,
3065};
3066static const unsigned int msiof2_ss1_d_pins[] = {
3067
3068 RCAR_GP_PIN(2, 17),
3069};
3070static const unsigned int msiof2_ss1_d_mux[] = {
3071 MSIOF2_SS1_D_MARK,
3072};
3073static const unsigned int msiof2_ss2_d_pins[] = {
3074
3075 RCAR_GP_PIN(2, 19),
3076};
3077static const unsigned int msiof2_ss2_d_mux[] = {
3078 MSIOF2_SS2_D_MARK,
3079};
3080static const unsigned int msiof2_rx_d_pins[] = {
3081
3082 RCAR_GP_PIN(2, 18),
3083};
3084static const unsigned int msiof2_rx_d_mux[] = {
3085 MSIOF2_RXD_D_MARK,
3086};
3087static const unsigned int msiof2_tx_d_pins[] = {
3088
3089 RCAR_GP_PIN(2, 16),
3090};
3091static const unsigned int msiof2_tx_d_mux[] = {
3092 MSIOF2_TXD_D_MARK,
3093};
3094
3095static const unsigned int msiof2_clk_e_pins[] = {
3096
3097 RCAR_GP_PIN(7, 15),
3098};
3099static const unsigned int msiof2_clk_e_mux[] = {
3100 MSIOF2_SCK_E_MARK,
3101};
3102static const unsigned int msiof2_sync_e_pins[] = {
3103
3104 RCAR_GP_PIN(7, 16),
3105};
3106static const unsigned int msiof2_sync_e_mux[] = {
3107 MSIOF2_SYNC_E_MARK,
3108};
3109static const unsigned int msiof2_rx_e_pins[] = {
3110
3111 RCAR_GP_PIN(7, 14),
3112};
3113static const unsigned int msiof2_rx_e_mux[] = {
3114 MSIOF2_RXD_E_MARK,
3115};
3116static const unsigned int msiof2_tx_e_pins[] = {
3117
3118 RCAR_GP_PIN(7, 13),
3119};
3120static const unsigned int msiof2_tx_e_mux[] = {
3121 MSIOF2_TXD_E_MARK,
3122};
3123
3124static const unsigned int pwm0_pins[] = {
3125 RCAR_GP_PIN(6, 14),
3126};
3127static const unsigned int pwm0_mux[] = {
3128 PWM0_MARK,
3129};
3130static const unsigned int pwm0_b_pins[] = {
3131 RCAR_GP_PIN(5, 30),
3132};
3133static const unsigned int pwm0_b_mux[] = {
3134 PWM0_B_MARK,
3135};
3136static const unsigned int pwm1_pins[] = {
3137 RCAR_GP_PIN(1, 17),
3138};
3139static const unsigned int pwm1_mux[] = {
3140 PWM1_MARK,
3141};
3142static const unsigned int pwm1_b_pins[] = {
3143 RCAR_GP_PIN(6, 15),
3144};
3145static const unsigned int pwm1_b_mux[] = {
3146 PWM1_B_MARK,
3147};
3148static const unsigned int pwm2_pins[] = {
3149 RCAR_GP_PIN(1, 18),
3150};
3151static const unsigned int pwm2_mux[] = {
3152 PWM2_MARK,
3153};
3154static const unsigned int pwm2_b_pins[] = {
3155 RCAR_GP_PIN(0, 16),
3156};
3157static const unsigned int pwm2_b_mux[] = {
3158 PWM2_B_MARK,
3159};
3160static const unsigned int pwm3_pins[] = {
3161 RCAR_GP_PIN(1, 24),
3162};
3163static const unsigned int pwm3_mux[] = {
3164 PWM3_MARK,
3165};
3166static const unsigned int pwm4_pins[] = {
3167 RCAR_GP_PIN(3, 26),
3168};
3169static const unsigned int pwm4_mux[] = {
3170 PWM4_MARK,
3171};
3172static const unsigned int pwm4_b_pins[] = {
3173 RCAR_GP_PIN(3, 31),
3174};
3175static const unsigned int pwm4_b_mux[] = {
3176 PWM4_B_MARK,
3177};
3178static const unsigned int pwm5_pins[] = {
3179 RCAR_GP_PIN(7, 21),
3180};
3181static const unsigned int pwm5_mux[] = {
3182 PWM5_MARK,
3183};
3184static const unsigned int pwm5_b_pins[] = {
3185 RCAR_GP_PIN(7, 20),
3186};
3187static const unsigned int pwm5_b_mux[] = {
3188 PWM5_B_MARK,
3189};
3190static const unsigned int pwm6_pins[] = {
3191 RCAR_GP_PIN(7, 22),
3192};
3193static const unsigned int pwm6_mux[] = {
3194 PWM6_MARK,
3195};
3196
3197static const unsigned int qspi_ctrl_pins[] = {
3198
3199 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3200};
3201static const unsigned int qspi_ctrl_mux[] = {
3202 SPCLK_MARK, SSL_MARK,
3203};
3204static const unsigned int qspi_data_pins[] = {
3205
3206 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3207 RCAR_GP_PIN(1, 8),
3208};
3209static const unsigned int qspi_data_mux[] = {
3210 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3211};
3212
3213static const unsigned int qspi_ctrl_b_pins[] = {
3214
3215 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3216};
3217static const unsigned int qspi_ctrl_b_mux[] = {
3218 SPCLK_B_MARK, SSL_B_MARK,
3219};
3220static const unsigned int qspi_data_b_pins[] = {
3221
3222 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3223 RCAR_GP_PIN(6, 4),
3224};
3225static const unsigned int qspi_data_b_mux[] = {
3226 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
3227};
3228
3229static const unsigned int scif0_data_pins[] = {
3230
3231 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3232};
3233static const unsigned int scif0_data_mux[] = {
3234 RX0_MARK, TX0_MARK,
3235};
3236static const unsigned int scif0_data_b_pins[] = {
3237
3238 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3239};
3240static const unsigned int scif0_data_b_mux[] = {
3241 RX0_B_MARK, TX0_B_MARK,
3242};
3243static const unsigned int scif0_data_c_pins[] = {
3244
3245 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3246};
3247static const unsigned int scif0_data_c_mux[] = {
3248 RX0_C_MARK, TX0_C_MARK,
3249};
3250static const unsigned int scif0_data_d_pins[] = {
3251
3252 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3253};
3254static const unsigned int scif0_data_d_mux[] = {
3255 RX0_D_MARK, TX0_D_MARK,
3256};
3257static const unsigned int scif0_data_e_pins[] = {
3258
3259 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3260};
3261static const unsigned int scif0_data_e_mux[] = {
3262 RX0_E_MARK, TX0_E_MARK,
3263};
3264
3265static const unsigned int scif1_data_pins[] = {
3266
3267 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3268};
3269static const unsigned int scif1_data_mux[] = {
3270 RX1_MARK, TX1_MARK,
3271};
3272static const unsigned int scif1_data_b_pins[] = {
3273
3274 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3275};
3276static const unsigned int scif1_data_b_mux[] = {
3277 RX1_B_MARK, TX1_B_MARK,
3278};
3279static const unsigned int scif1_clk_b_pins[] = {
3280
3281 RCAR_GP_PIN(3, 10),
3282};
3283static const unsigned int scif1_clk_b_mux[] = {
3284 SCIF1_SCK_B_MARK,
3285};
3286static const unsigned int scif1_data_c_pins[] = {
3287
3288 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3289};
3290static const unsigned int scif1_data_c_mux[] = {
3291 RX1_C_MARK, TX1_C_MARK,
3292};
3293static const unsigned int scif1_data_d_pins[] = {
3294
3295 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3296};
3297static const unsigned int scif1_data_d_mux[] = {
3298 RX1_D_MARK, TX1_D_MARK,
3299};
3300
3301static const unsigned int scif2_data_pins[] = {
3302
3303 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3304};
3305static const unsigned int scif2_data_mux[] = {
3306 RX2_MARK, TX2_MARK,
3307};
3308static const unsigned int scif2_data_b_pins[] = {
3309
3310 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3311};
3312static const unsigned int scif2_data_b_mux[] = {
3313 RX2_B_MARK, TX2_B_MARK,
3314};
3315static const unsigned int scif2_clk_b_pins[] = {
3316
3317 RCAR_GP_PIN(3, 18),
3318};
3319static const unsigned int scif2_clk_b_mux[] = {
3320 SCIF2_SCK_B_MARK,
3321};
3322static const unsigned int scif2_data_c_pins[] = {
3323
3324 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3325};
3326static const unsigned int scif2_data_c_mux[] = {
3327 RX2_C_MARK, TX2_C_MARK,
3328};
3329static const unsigned int scif2_data_e_pins[] = {
3330
3331 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3332};
3333static const unsigned int scif2_data_e_mux[] = {
3334 RX2_E_MARK, TX2_E_MARK,
3335};
3336
3337static const unsigned int scif3_data_pins[] = {
3338
3339 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3340};
3341static const unsigned int scif3_data_mux[] = {
3342 RX3_MARK, TX3_MARK,
3343};
3344static const unsigned int scif3_clk_pins[] = {
3345
3346 RCAR_GP_PIN(3, 23),
3347};
3348static const unsigned int scif3_clk_mux[] = {
3349 SCIF3_SCK_MARK,
3350};
3351static const unsigned int scif3_data_b_pins[] = {
3352
3353 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3354};
3355static const unsigned int scif3_data_b_mux[] = {
3356 RX3_B_MARK, TX3_B_MARK,
3357};
3358static const unsigned int scif3_clk_b_pins[] = {
3359
3360 RCAR_GP_PIN(4, 8),
3361};
3362static const unsigned int scif3_clk_b_mux[] = {
3363 SCIF3_SCK_B_MARK,
3364};
3365static const unsigned int scif3_data_c_pins[] = {
3366
3367 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3368};
3369static const unsigned int scif3_data_c_mux[] = {
3370 RX3_C_MARK, TX3_C_MARK,
3371};
3372static const unsigned int scif3_data_d_pins[] = {
3373
3374 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3375};
3376static const unsigned int scif3_data_d_mux[] = {
3377 RX3_D_MARK, TX3_D_MARK,
3378};
3379
3380static const unsigned int scif4_data_pins[] = {
3381
3382 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3383};
3384static const unsigned int scif4_data_mux[] = {
3385 RX4_MARK, TX4_MARK,
3386};
3387static const unsigned int scif4_data_b_pins[] = {
3388
3389 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3390};
3391static const unsigned int scif4_data_b_mux[] = {
3392 RX4_B_MARK, TX4_B_MARK,
3393};
3394static const unsigned int scif4_data_c_pins[] = {
3395
3396 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3397};
3398static const unsigned int scif4_data_c_mux[] = {
3399 RX4_C_MARK, TX4_C_MARK,
3400};
3401
3402static const unsigned int scif5_data_pins[] = {
3403
3404 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3405};
3406static const unsigned int scif5_data_mux[] = {
3407 RX5_MARK, TX5_MARK,
3408};
3409static const unsigned int scif5_data_b_pins[] = {
3410
3411 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3412};
3413static const unsigned int scif5_data_b_mux[] = {
3414 RX5_B_MARK, TX5_B_MARK,
3415};
3416
3417static const unsigned int scifa0_data_pins[] = {
3418
3419 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3420};
3421static const unsigned int scifa0_data_mux[] = {
3422 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3423};
3424static const unsigned int scifa0_data_b_pins[] = {
3425
3426 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3427};
3428static const unsigned int scifa0_data_b_mux[] = {
3429 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3430};
3431
3432static const unsigned int scifa1_data_pins[] = {
3433
3434 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3435};
3436static const unsigned int scifa1_data_mux[] = {
3437 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3438};
3439static const unsigned int scifa1_clk_pins[] = {
3440
3441 RCAR_GP_PIN(3, 10),
3442};
3443static const unsigned int scifa1_clk_mux[] = {
3444 SCIFA1_SCK_MARK,
3445};
3446static const unsigned int scifa1_data_b_pins[] = {
3447
3448 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3449};
3450static const unsigned int scifa1_data_b_mux[] = {
3451 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3452};
3453static const unsigned int scifa1_clk_b_pins[] = {
3454
3455 RCAR_GP_PIN(1, 0),
3456};
3457static const unsigned int scifa1_clk_b_mux[] = {
3458 SCIFA1_SCK_B_MARK,
3459};
3460static const unsigned int scifa1_data_c_pins[] = {
3461
3462 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3463};
3464static const unsigned int scifa1_data_c_mux[] = {
3465 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3466};
3467
3468static const unsigned int scifa2_data_pins[] = {
3469
3470 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3471};
3472static const unsigned int scifa2_data_mux[] = {
3473 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3474};
3475static const unsigned int scifa2_clk_pins[] = {
3476
3477 RCAR_GP_PIN(3, 18),
3478};
3479static const unsigned int scifa2_clk_mux[] = {
3480 SCIFA2_SCK_MARK,
3481};
3482static const unsigned int scifa2_data_b_pins[] = {
3483
3484 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3485};
3486static const unsigned int scifa2_data_b_mux[] = {
3487 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3488};
3489
3490static const unsigned int scifa3_data_pins[] = {
3491
3492 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3493};
3494static const unsigned int scifa3_data_mux[] = {
3495 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3496};
3497static const unsigned int scifa3_clk_pins[] = {
3498
3499 RCAR_GP_PIN(3, 23),
3500};
3501static const unsigned int scifa3_clk_mux[] = {
3502 SCIFA3_SCK_MARK,
3503};
3504static const unsigned int scifa3_data_b_pins[] = {
3505
3506 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3507};
3508static const unsigned int scifa3_data_b_mux[] = {
3509 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3510};
3511static const unsigned int scifa3_clk_b_pins[] = {
3512
3513 RCAR_GP_PIN(4, 8),
3514};
3515static const unsigned int scifa3_clk_b_mux[] = {
3516 SCIFA3_SCK_B_MARK,
3517};
3518static const unsigned int scifa3_data_c_pins[] = {
3519
3520 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3521};
3522static const unsigned int scifa3_data_c_mux[] = {
3523 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3524};
3525static const unsigned int scifa3_clk_c_pins[] = {
3526
3527 RCAR_GP_PIN(7, 22),
3528};
3529static const unsigned int scifa3_clk_c_mux[] = {
3530 SCIFA3_SCK_C_MARK,
3531};
3532
3533static const unsigned int scifa4_data_pins[] = {
3534
3535 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3536};
3537static const unsigned int scifa4_data_mux[] = {
3538 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3539};
3540static const unsigned int scifa4_data_b_pins[] = {
3541
3542 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3543};
3544static const unsigned int scifa4_data_b_mux[] = {
3545 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3546};
3547static const unsigned int scifa4_data_c_pins[] = {
3548
3549 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3550};
3551static const unsigned int scifa4_data_c_mux[] = {
3552 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3553};
3554
3555static const unsigned int scifa5_data_pins[] = {
3556
3557 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3558};
3559static const unsigned int scifa5_data_mux[] = {
3560 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3561};
3562static const unsigned int scifa5_data_b_pins[] = {
3563
3564 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3565};
3566static const unsigned int scifa5_data_b_mux[] = {
3567 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3568};
3569static const unsigned int scifa5_data_c_pins[] = {
3570
3571 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3572};
3573static const unsigned int scifa5_data_c_mux[] = {
3574 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3575};
3576
3577static const unsigned int scifb0_data_pins[] = {
3578
3579 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3580};
3581static const unsigned int scifb0_data_mux[] = {
3582 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3583};
3584static const unsigned int scifb0_clk_pins[] = {
3585
3586 RCAR_GP_PIN(7, 2),
3587};
3588static const unsigned int scifb0_clk_mux[] = {
3589 SCIFB0_SCK_MARK,
3590};
3591static const unsigned int scifb0_ctrl_pins[] = {
3592
3593 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3594};
3595static const unsigned int scifb0_ctrl_mux[] = {
3596 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3597};
3598static const unsigned int scifb0_data_b_pins[] = {
3599
3600 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3601};
3602static const unsigned int scifb0_data_b_mux[] = {
3603 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3604};
3605static const unsigned int scifb0_clk_b_pins[] = {
3606
3607 RCAR_GP_PIN(5, 31),
3608};
3609static const unsigned int scifb0_clk_b_mux[] = {
3610 SCIFB0_SCK_B_MARK,
3611};
3612static const unsigned int scifb0_ctrl_b_pins[] = {
3613
3614 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3615};
3616static const unsigned int scifb0_ctrl_b_mux[] = {
3617 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3618};
3619static const unsigned int scifb0_data_c_pins[] = {
3620
3621 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3622};
3623static const unsigned int scifb0_data_c_mux[] = {
3624 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3625};
3626static const unsigned int scifb0_clk_c_pins[] = {
3627
3628 RCAR_GP_PIN(2, 30),
3629};
3630static const unsigned int scifb0_clk_c_mux[] = {
3631 SCIFB0_SCK_C_MARK,
3632};
3633static const unsigned int scifb0_data_d_pins[] = {
3634
3635 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3636};
3637static const unsigned int scifb0_data_d_mux[] = {
3638 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3639};
3640static const unsigned int scifb0_clk_d_pins[] = {
3641
3642 RCAR_GP_PIN(4, 17),
3643};
3644static const unsigned int scifb0_clk_d_mux[] = {
3645 SCIFB0_SCK_D_MARK,
3646};
3647
3648static const unsigned int scifb1_data_pins[] = {
3649
3650 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3651};
3652static const unsigned int scifb1_data_mux[] = {
3653 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3654};
3655static const unsigned int scifb1_clk_pins[] = {
3656
3657 RCAR_GP_PIN(7, 7),
3658};
3659static const unsigned int scifb1_clk_mux[] = {
3660 SCIFB1_SCK_MARK,
3661};
3662static const unsigned int scifb1_ctrl_pins[] = {
3663
3664 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3665};
3666static const unsigned int scifb1_ctrl_mux[] = {
3667 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3668};
3669static const unsigned int scifb1_data_b_pins[] = {
3670
3671 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3672};
3673static const unsigned int scifb1_data_b_mux[] = {
3674 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3675};
3676static const unsigned int scifb1_clk_b_pins[] = {
3677
3678 RCAR_GP_PIN(1, 3),
3679};
3680static const unsigned int scifb1_clk_b_mux[] = {
3681 SCIFB1_SCK_B_MARK,
3682};
3683static const unsigned int scifb1_data_c_pins[] = {
3684
3685 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3686};
3687static const unsigned int scifb1_data_c_mux[] = {
3688 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3689};
3690static const unsigned int scifb1_clk_c_pins[] = {
3691
3692 RCAR_GP_PIN(7, 11),
3693};
3694static const unsigned int scifb1_clk_c_mux[] = {
3695 SCIFB1_SCK_C_MARK,
3696};
3697static const unsigned int scifb1_data_d_pins[] = {
3698
3699 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3700};
3701static const unsigned int scifb1_data_d_mux[] = {
3702 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3703};
3704
3705static const unsigned int scifb2_data_pins[] = {
3706
3707 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3708};
3709static const unsigned int scifb2_data_mux[] = {
3710 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3711};
3712static const unsigned int scifb2_clk_pins[] = {
3713
3714 RCAR_GP_PIN(4, 15),
3715};
3716static const unsigned int scifb2_clk_mux[] = {
3717 SCIFB2_SCK_MARK,
3718};
3719static const unsigned int scifb2_ctrl_pins[] = {
3720
3721 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3722};
3723static const unsigned int scifb2_ctrl_mux[] = {
3724 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3725};
3726static const unsigned int scifb2_data_b_pins[] = {
3727
3728 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3729};
3730static const unsigned int scifb2_data_b_mux[] = {
3731 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3732};
3733static const unsigned int scifb2_clk_b_pins[] = {
3734
3735 RCAR_GP_PIN(5, 31),
3736};
3737static const unsigned int scifb2_clk_b_mux[] = {
3738 SCIFB2_SCK_B_MARK,
3739};
3740static const unsigned int scifb2_ctrl_b_pins[] = {
3741
3742 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3743};
3744static const unsigned int scifb2_ctrl_b_mux[] = {
3745 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3746};
3747static const unsigned int scifb2_data_c_pins[] = {
3748
3749 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3750};
3751static const unsigned int scifb2_data_c_mux[] = {
3752 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3753};
3754static const unsigned int scifb2_clk_c_pins[] = {
3755
3756 RCAR_GP_PIN(5, 27),
3757};
3758static const unsigned int scifb2_clk_c_mux[] = {
3759 SCIFB2_SCK_C_MARK,
3760};
3761static const unsigned int scifb2_data_d_pins[] = {
3762
3763 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3764};
3765static const unsigned int scifb2_data_d_mux[] = {
3766 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3767};
3768
3769
3770static const unsigned int scif_clk_pins[] = {
3771
3772 RCAR_GP_PIN(2, 29),
3773};
3774static const unsigned int scif_clk_mux[] = {
3775 SCIF_CLK_MARK,
3776};
3777static const unsigned int scif_clk_b_pins[] = {
3778
3779 RCAR_GP_PIN(7, 19),
3780};
3781static const unsigned int scif_clk_b_mux[] = {
3782 SCIF_CLK_B_MARK,
3783};
3784
3785
3786static const unsigned int sdhi0_data_pins[] = {
3787
3788 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3789 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3790};
3791static const unsigned int sdhi0_data_mux[] = {
3792 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3793};
3794static const unsigned int sdhi0_ctrl_pins[] = {
3795
3796 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3797};
3798static const unsigned int sdhi0_ctrl_mux[] = {
3799 SD0_CLK_MARK, SD0_CMD_MARK,
3800};
3801static const unsigned int sdhi0_cd_pins[] = {
3802
3803 RCAR_GP_PIN(6, 6),
3804};
3805static const unsigned int sdhi0_cd_mux[] = {
3806 SD0_CD_MARK,
3807};
3808static const unsigned int sdhi0_wp_pins[] = {
3809
3810 RCAR_GP_PIN(6, 7),
3811};
3812static const unsigned int sdhi0_wp_mux[] = {
3813 SD0_WP_MARK,
3814};
3815
3816static const unsigned int sdhi1_data_pins[] = {
3817
3818 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3819 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3820};
3821static const unsigned int sdhi1_data_mux[] = {
3822 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3823};
3824static const unsigned int sdhi1_ctrl_pins[] = {
3825
3826 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3827};
3828static const unsigned int sdhi1_ctrl_mux[] = {
3829 SD1_CLK_MARK, SD1_CMD_MARK,
3830};
3831static const unsigned int sdhi1_cd_pins[] = {
3832
3833 RCAR_GP_PIN(6, 14),
3834};
3835static const unsigned int sdhi1_cd_mux[] = {
3836 SD1_CD_MARK,
3837};
3838static const unsigned int sdhi1_wp_pins[] = {
3839
3840 RCAR_GP_PIN(6, 15),
3841};
3842static const unsigned int sdhi1_wp_mux[] = {
3843 SD1_WP_MARK,
3844};
3845
3846static const unsigned int sdhi2_data_pins[] = {
3847
3848 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3849 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3850};
3851static const unsigned int sdhi2_data_mux[] = {
3852 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3853};
3854static const unsigned int sdhi2_ctrl_pins[] = {
3855
3856 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3857};
3858static const unsigned int sdhi2_ctrl_mux[] = {
3859 SD2_CLK_MARK, SD2_CMD_MARK,
3860};
3861static const unsigned int sdhi2_cd_pins[] = {
3862
3863 RCAR_GP_PIN(6, 22),
3864};
3865static const unsigned int sdhi2_cd_mux[] = {
3866 SD2_CD_MARK,
3867};
3868static const unsigned int sdhi2_wp_pins[] = {
3869
3870 RCAR_GP_PIN(6, 23),
3871};
3872static const unsigned int sdhi2_wp_mux[] = {
3873 SD2_WP_MARK,
3874};
3875
3876
3877static const unsigned int ssi0_data_pins[] = {
3878
3879 RCAR_GP_PIN(2, 2),
3880};
3881
3882static const unsigned int ssi0_data_mux[] = {
3883 SSI_SDATA0_MARK,
3884};
3885
3886static const unsigned int ssi0_data_b_pins[] = {
3887
3888 RCAR_GP_PIN(3, 4),
3889};
3890
3891static const unsigned int ssi0_data_b_mux[] = {
3892 SSI_SDATA0_B_MARK,
3893};
3894
3895static const unsigned int ssi0129_ctrl_pins[] = {
3896
3897 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3898};
3899
3900static const unsigned int ssi0129_ctrl_mux[] = {
3901 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3902};
3903
3904static const unsigned int ssi0129_ctrl_b_pins[] = {
3905
3906 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3907};
3908
3909static const unsigned int ssi0129_ctrl_b_mux[] = {
3910 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3911};
3912
3913static const unsigned int ssi1_data_pins[] = {
3914
3915 RCAR_GP_PIN(2, 5),
3916};
3917
3918static const unsigned int ssi1_data_mux[] = {
3919 SSI_SDATA1_MARK,
3920};
3921
3922static const unsigned int ssi1_data_b_pins[] = {
3923
3924 RCAR_GP_PIN(3, 7),
3925};
3926
3927static const unsigned int ssi1_data_b_mux[] = {
3928 SSI_SDATA1_B_MARK,
3929};
3930
3931static const unsigned int ssi1_ctrl_pins[] = {
3932
3933 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3934};
3935
3936static const unsigned int ssi1_ctrl_mux[] = {
3937 SSI_SCK1_MARK, SSI_WS1_MARK,
3938};
3939
3940static const unsigned int ssi1_ctrl_b_pins[] = {
3941
3942 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3943};
3944
3945static const unsigned int ssi1_ctrl_b_mux[] = {
3946 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3947};
3948
3949static const unsigned int ssi2_data_pins[] = {
3950
3951 RCAR_GP_PIN(2, 8),
3952};
3953
3954static const unsigned int ssi2_data_mux[] = {
3955 SSI_SDATA2_MARK,
3956};
3957
3958static const unsigned int ssi2_ctrl_pins[] = {
3959
3960 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3961};
3962
3963static const unsigned int ssi2_ctrl_mux[] = {
3964 SSI_SCK2_MARK, SSI_WS2_MARK,
3965};
3966
3967static const unsigned int ssi3_data_pins[] = {
3968
3969 RCAR_GP_PIN(2, 11),
3970};
3971
3972static const unsigned int ssi3_data_mux[] = {
3973 SSI_SDATA3_MARK,
3974};
3975
3976static const unsigned int ssi34_ctrl_pins[] = {
3977
3978 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3979};
3980
3981static const unsigned int ssi34_ctrl_mux[] = {
3982 SSI_SCK34_MARK, SSI_WS34_MARK,
3983};
3984
3985static const unsigned int ssi4_data_pins[] = {
3986
3987 RCAR_GP_PIN(2, 14),
3988};
3989
3990static const unsigned int ssi4_data_mux[] = {
3991 SSI_SDATA4_MARK,
3992};
3993
3994static const unsigned int ssi4_ctrl_pins[] = {
3995
3996 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3997};
3998
3999static const unsigned int ssi4_ctrl_mux[] = {
4000 SSI_SCK4_MARK, SSI_WS4_MARK,
4001};
4002
4003static const unsigned int ssi5_data_pins[] = {
4004
4005 RCAR_GP_PIN(2, 17),
4006};
4007
4008static const unsigned int ssi5_data_mux[] = {
4009 SSI_SDATA5_MARK,
4010};
4011
4012static const unsigned int ssi5_ctrl_pins[] = {
4013
4014 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4015};
4016
4017static const unsigned int ssi5_ctrl_mux[] = {
4018 SSI_SCK5_MARK, SSI_WS5_MARK,
4019};
4020
4021static const unsigned int ssi6_data_pins[] = {
4022
4023 RCAR_GP_PIN(2, 20),
4024};
4025
4026static const unsigned int ssi6_data_mux[] = {
4027 SSI_SDATA6_MARK,
4028};
4029
4030static const unsigned int ssi6_ctrl_pins[] = {
4031
4032 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4033};
4034
4035static const unsigned int ssi6_ctrl_mux[] = {
4036 SSI_SCK6_MARK, SSI_WS6_MARK,
4037};
4038
4039static const unsigned int ssi7_data_pins[] = {
4040
4041 RCAR_GP_PIN(2, 23),
4042};
4043
4044static const unsigned int ssi7_data_mux[] = {
4045 SSI_SDATA7_MARK,
4046};
4047
4048static const unsigned int ssi7_data_b_pins[] = {
4049
4050 RCAR_GP_PIN(3, 12),
4051};
4052
4053static const unsigned int ssi7_data_b_mux[] = {
4054 SSI_SDATA7_B_MARK,
4055};
4056
4057static const unsigned int ssi78_ctrl_pins[] = {
4058
4059 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4060};
4061
4062static const unsigned int ssi78_ctrl_mux[] = {
4063 SSI_SCK78_MARK, SSI_WS78_MARK,
4064};
4065
4066static const unsigned int ssi78_ctrl_b_pins[] = {
4067
4068 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4069};
4070
4071static const unsigned int ssi78_ctrl_b_mux[] = {
4072 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4073};
4074
4075static const unsigned int ssi8_data_pins[] = {
4076
4077 RCAR_GP_PIN(2, 24),
4078};
4079
4080static const unsigned int ssi8_data_mux[] = {
4081 SSI_SDATA8_MARK,
4082};
4083
4084static const unsigned int ssi8_data_b_pins[] = {
4085
4086 RCAR_GP_PIN(3, 13),
4087};
4088
4089static const unsigned int ssi8_data_b_mux[] = {
4090 SSI_SDATA8_B_MARK,
4091};
4092
4093static const unsigned int ssi9_data_pins[] = {
4094
4095 RCAR_GP_PIN(2, 27),
4096};
4097
4098static const unsigned int ssi9_data_mux[] = {
4099 SSI_SDATA9_MARK,
4100};
4101
4102static const unsigned int ssi9_data_b_pins[] = {
4103
4104 RCAR_GP_PIN(3, 18),
4105};
4106
4107static const unsigned int ssi9_data_b_mux[] = {
4108 SSI_SDATA9_B_MARK,
4109};
4110
4111static const unsigned int ssi9_ctrl_pins[] = {
4112
4113 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4114};
4115
4116static const unsigned int ssi9_ctrl_mux[] = {
4117 SSI_SCK9_MARK, SSI_WS9_MARK,
4118};
4119
4120static const unsigned int ssi9_ctrl_b_pins[] = {
4121
4122 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4123};
4124
4125static const unsigned int ssi9_ctrl_b_mux[] = {
4126 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4127};
4128
4129
4130static const unsigned int tpu_to0_pins[] = {
4131 RCAR_GP_PIN(6, 14),
4132};
4133static const unsigned int tpu_to0_mux[] = {
4134 TPU_TO0_MARK,
4135};
4136static const unsigned int tpu_to1_pins[] = {
4137 RCAR_GP_PIN(1, 17),
4138};
4139static const unsigned int tpu_to1_mux[] = {
4140 TPU_TO1_MARK,
4141};
4142static const unsigned int tpu_to2_pins[] = {
4143 RCAR_GP_PIN(1, 18),
4144};
4145static const unsigned int tpu_to2_mux[] = {
4146 TPU_TO2_MARK,
4147};
4148static const unsigned int tpu_to3_pins[] = {
4149 RCAR_GP_PIN(1, 24),
4150};
4151static const unsigned int tpu_to3_mux[] = {
4152 TPU_TO3_MARK,
4153};
4154
4155
4156static const unsigned int usb0_pins[] = {
4157 RCAR_GP_PIN(7, 23),
4158 RCAR_GP_PIN(7, 24),
4159};
4160static const unsigned int usb0_mux[] = {
4161 USB0_PWEN_MARK,
4162 USB0_OVC_MARK,
4163};
4164
4165static const unsigned int usb1_pins[] = {
4166 RCAR_GP_PIN(7, 25),
4167 RCAR_GP_PIN(6, 30),
4168};
4169static const unsigned int usb1_mux[] = {
4170 USB1_PWEN_MARK,
4171 USB1_OVC_MARK,
4172};
4173
4174static const unsigned int vin0_data_pins[] = {
4175
4176 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4177 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4178 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4179 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4180
4181 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4182 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4183 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4184 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4185
4186 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4187 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4188 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4189 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4190};
4191static const unsigned int vin0_data_mux[] = {
4192
4193 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4194 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4195 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4196 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4197
4198 VI0_G0_MARK, VI0_G1_MARK,
4199 VI0_G2_MARK, VI0_G3_MARK,
4200 VI0_G4_MARK, VI0_G5_MARK,
4201 VI0_G6_MARK, VI0_G7_MARK,
4202
4203 VI0_R0_MARK, VI0_R1_MARK,
4204 VI0_R2_MARK, VI0_R3_MARK,
4205 VI0_R4_MARK, VI0_R5_MARK,
4206 VI0_R6_MARK, VI0_R7_MARK,
4207};
4208static const unsigned int vin0_data18_pins[] = {
4209
4210 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4211 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4212 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4213
4214 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4215 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4216 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4217
4218 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4219 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4220 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4221};
4222static const unsigned int vin0_data18_mux[] = {
4223
4224 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4225 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4226 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4227
4228 VI0_G2_MARK, VI0_G3_MARK,
4229 VI0_G4_MARK, VI0_G5_MARK,
4230 VI0_G6_MARK, VI0_G7_MARK,
4231
4232 VI0_R2_MARK, VI0_R3_MARK,
4233 VI0_R4_MARK, VI0_R5_MARK,
4234 VI0_R6_MARK, VI0_R7_MARK,
4235};
4236static const unsigned int vin0_sync_pins[] = {
4237 RCAR_GP_PIN(4, 3),
4238 RCAR_GP_PIN(4, 4),
4239};
4240static const unsigned int vin0_sync_mux[] = {
4241 VI0_HSYNC_N_MARK,
4242 VI0_VSYNC_N_MARK,
4243};
4244static const unsigned int vin0_field_pins[] = {
4245 RCAR_GP_PIN(4, 2),
4246};
4247static const unsigned int vin0_field_mux[] = {
4248 VI0_FIELD_MARK,
4249};
4250static const unsigned int vin0_clkenb_pins[] = {
4251 RCAR_GP_PIN(4, 1),
4252};
4253static const unsigned int vin0_clkenb_mux[] = {
4254 VI0_CLKENB_MARK,
4255};
4256static const unsigned int vin0_clk_pins[] = {
4257 RCAR_GP_PIN(4, 0),
4258};
4259static const unsigned int vin0_clk_mux[] = {
4260 VI0_CLK_MARK,
4261};
4262
4263static const unsigned int vin1_data8_pins[] = {
4264 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4265 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4266 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4267 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4268};
4269static const unsigned int vin1_data8_mux[] = {
4270 VI1_DATA0_MARK, VI1_DATA1_MARK,
4271 VI1_DATA2_MARK, VI1_DATA3_MARK,
4272 VI1_DATA4_MARK, VI1_DATA5_MARK,
4273 VI1_DATA6_MARK, VI1_DATA7_MARK,
4274};
4275static const unsigned int vin1_sync_pins[] = {
4276 RCAR_GP_PIN(5, 0),
4277 RCAR_GP_PIN(5, 1),
4278};
4279static const unsigned int vin1_sync_mux[] = {
4280 VI1_HSYNC_N_MARK,
4281 VI1_VSYNC_N_MARK,
4282};
4283static const unsigned int vin1_field_pins[] = {
4284 RCAR_GP_PIN(5, 3),
4285};
4286static const unsigned int vin1_field_mux[] = {
4287 VI1_FIELD_MARK,
4288};
4289static const unsigned int vin1_clkenb_pins[] = {
4290 RCAR_GP_PIN(5, 2),
4291};
4292static const unsigned int vin1_clkenb_mux[] = {
4293 VI1_CLKENB_MARK,
4294};
4295static const unsigned int vin1_clk_pins[] = {
4296 RCAR_GP_PIN(5, 4),
4297};
4298static const unsigned int vin1_clk_mux[] = {
4299 VI1_CLK_MARK,
4300};
4301static const unsigned int vin1_data_b_pins[] = {
4302
4303 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4304 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4305 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4306 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4307
4308 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4309 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4310 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4311 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4312
4313 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4314 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4315 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4316 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4317};
4318static const unsigned int vin1_data_b_mux[] = {
4319
4320 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4321 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4322 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4323 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4324
4325 VI1_G0_B_MARK, VI1_G1_B_MARK,
4326 VI1_G2_B_MARK, VI1_G3_B_MARK,
4327 VI1_G4_B_MARK, VI1_G5_B_MARK,
4328 VI1_G6_B_MARK, VI1_G7_B_MARK,
4329
4330 VI1_R0_B_MARK, VI1_R1_B_MARK,
4331 VI1_R2_B_MARK, VI1_R3_B_MARK,
4332 VI1_R4_B_MARK, VI1_R5_B_MARK,
4333 VI1_R6_B_MARK, VI1_R7_B_MARK,
4334};
4335static const unsigned int vin1_data18_b_pins[] = {
4336
4337 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4338 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4339 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4340
4341 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4342 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4343 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4344
4345 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4346 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4347 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4348};
4349static const unsigned int vin1_data18_b_mux[] = {
4350
4351 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4352 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4353 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4354
4355 VI1_G2_B_MARK, VI1_G3_B_MARK,
4356 VI1_G4_B_MARK, VI1_G5_B_MARK,
4357 VI1_G6_B_MARK, VI1_G7_B_MARK,
4358
4359 VI1_R2_B_MARK, VI1_R3_B_MARK,
4360 VI1_R4_B_MARK, VI1_R5_B_MARK,
4361 VI1_R6_B_MARK, VI1_R7_B_MARK,
4362};
4363static const unsigned int vin1_sync_b_pins[] = {
4364 RCAR_GP_PIN(3, 17),
4365 RCAR_GP_PIN(3, 18),
4366};
4367static const unsigned int vin1_sync_b_mux[] = {
4368 VI1_HSYNC_N_B_MARK,
4369 VI1_VSYNC_N_B_MARK,
4370};
4371static const unsigned int vin1_field_b_pins[] = {
4372 RCAR_GP_PIN(3, 20),
4373};
4374static const unsigned int vin1_field_b_mux[] = {
4375 VI1_FIELD_B_MARK,
4376};
4377static const unsigned int vin1_clkenb_b_pins[] = {
4378 RCAR_GP_PIN(3, 19),
4379};
4380static const unsigned int vin1_clkenb_b_mux[] = {
4381 VI1_CLKENB_B_MARK,
4382};
4383static const unsigned int vin1_clk_b_pins[] = {
4384 RCAR_GP_PIN(3, 16),
4385};
4386static const unsigned int vin1_clk_b_mux[] = {
4387 VI1_CLK_B_MARK,
4388};
4389
4390static const unsigned int vin2_data8_pins[] = {
4391 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4392 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4393 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4394 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4395};
4396static const unsigned int vin2_data8_mux[] = {
4397 VI2_DATA0_MARK, VI2_DATA1_MARK,
4398 VI2_DATA2_MARK, VI2_DATA3_MARK,
4399 VI2_DATA4_MARK, VI2_DATA5_MARK,
4400 VI2_DATA6_MARK, VI2_DATA7_MARK,
4401};
4402static const unsigned int vin2_sync_pins[] = {
4403 RCAR_GP_PIN(4, 15),
4404 RCAR_GP_PIN(4, 16),
4405};
4406static const unsigned int vin2_sync_mux[] = {
4407 VI2_HSYNC_N_MARK,
4408 VI2_VSYNC_N_MARK,
4409};
4410static const unsigned int vin2_field_pins[] = {
4411 RCAR_GP_PIN(4, 18),
4412};
4413static const unsigned int vin2_field_mux[] = {
4414 VI2_FIELD_MARK,
4415};
4416static const unsigned int vin2_clkenb_pins[] = {
4417 RCAR_GP_PIN(4, 17),
4418};
4419static const unsigned int vin2_clkenb_mux[] = {
4420 VI2_CLKENB_MARK,
4421};
4422static const unsigned int vin2_clk_pins[] = {
4423 RCAR_GP_PIN(4, 19),
4424};
4425static const unsigned int vin2_clk_mux[] = {
4426 VI2_CLK_MARK,
4427};
4428
4429static const struct {
4430 struct sh_pfc_pin_group common[346];
4431#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4432 struct sh_pfc_pin_group automotive[9];
4433#endif
4434} pinmux_groups = {
4435 .common = {
4436 SH_PFC_PIN_GROUP(audio_clk_a),
4437 SH_PFC_PIN_GROUP(audio_clk_b),
4438 SH_PFC_PIN_GROUP(audio_clk_b_b),
4439 SH_PFC_PIN_GROUP(audio_clk_c),
4440 SH_PFC_PIN_GROUP(audio_clkout),
4441 SH_PFC_PIN_GROUP(avb_link),
4442 SH_PFC_PIN_GROUP(avb_magic),
4443 SH_PFC_PIN_GROUP(avb_phy_int),
4444 SH_PFC_PIN_GROUP(avb_mdio),
4445 SH_PFC_PIN_GROUP(avb_mii),
4446 SH_PFC_PIN_GROUP(avb_gmii),
4447 SH_PFC_PIN_GROUP(can0_data),
4448 SH_PFC_PIN_GROUP(can0_data_b),
4449 SH_PFC_PIN_GROUP(can0_data_c),
4450 SH_PFC_PIN_GROUP(can0_data_d),
4451 SH_PFC_PIN_GROUP(can0_data_e),
4452 SH_PFC_PIN_GROUP(can0_data_f),
4453 SH_PFC_PIN_GROUP(can1_data),
4454 SH_PFC_PIN_GROUP(can1_data_b),
4455 SH_PFC_PIN_GROUP(can1_data_c),
4456 SH_PFC_PIN_GROUP(can1_data_d),
4457 SH_PFC_PIN_GROUP(can_clk),
4458 SH_PFC_PIN_GROUP(can_clk_b),
4459 SH_PFC_PIN_GROUP(can_clk_c),
4460 SH_PFC_PIN_GROUP(can_clk_d),
4461 SH_PFC_PIN_GROUP(du_rgb666),
4462 SH_PFC_PIN_GROUP(du_rgb888),
4463 SH_PFC_PIN_GROUP(du_clk_out_0),
4464 SH_PFC_PIN_GROUP(du_clk_out_1),
4465 SH_PFC_PIN_GROUP(du_sync),
4466 SH_PFC_PIN_GROUP(du_oddf),
4467 SH_PFC_PIN_GROUP(du_cde),
4468 SH_PFC_PIN_GROUP(du_disp),
4469 SH_PFC_PIN_GROUP(du0_clk_in),
4470 SH_PFC_PIN_GROUP(du1_clk_in),
4471 SH_PFC_PIN_GROUP(du1_clk_in_b),
4472 SH_PFC_PIN_GROUP(du1_clk_in_c),
4473 SH_PFC_PIN_GROUP(eth_link),
4474 SH_PFC_PIN_GROUP(eth_magic),
4475 SH_PFC_PIN_GROUP(eth_mdio),
4476 SH_PFC_PIN_GROUP(eth_rmii),
4477 SH_PFC_PIN_GROUP(hscif0_data),
4478 SH_PFC_PIN_GROUP(hscif0_clk),
4479 SH_PFC_PIN_GROUP(hscif0_ctrl),
4480 SH_PFC_PIN_GROUP(hscif0_data_b),
4481 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4482 SH_PFC_PIN_GROUP(hscif0_data_c),
4483 SH_PFC_PIN_GROUP(hscif0_clk_c),
4484 SH_PFC_PIN_GROUP(hscif1_data),
4485 SH_PFC_PIN_GROUP(hscif1_clk),
4486 SH_PFC_PIN_GROUP(hscif1_ctrl),
4487 SH_PFC_PIN_GROUP(hscif1_data_b),
4488 SH_PFC_PIN_GROUP(hscif1_data_c),
4489 SH_PFC_PIN_GROUP(hscif1_clk_c),
4490 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4491 SH_PFC_PIN_GROUP(hscif1_data_d),
4492 SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c),
4493 SH_PFC_PIN_GROUP(hscif1_clk_e),
4494 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4495 SH_PFC_PIN_GROUP(hscif2_data),
4496 SH_PFC_PIN_GROUP(hscif2_clk),
4497 SH_PFC_PIN_GROUP(hscif2_ctrl),
4498 SH_PFC_PIN_GROUP(hscif2_data_b),
4499 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4500 SH_PFC_PIN_GROUP(hscif2_data_c),
4501 SH_PFC_PIN_GROUP(hscif2_clk_c),
4502 SH_PFC_PIN_GROUP(hscif2_data_d),
4503 SH_PFC_PIN_GROUP(i2c0),
4504 SH_PFC_PIN_GROUP(i2c0_b),
4505 SH_PFC_PIN_GROUP(i2c0_c),
4506 SH_PFC_PIN_GROUP(i2c1),
4507 SH_PFC_PIN_GROUP(i2c1_b),
4508 SH_PFC_PIN_GROUP(i2c1_c),
4509 SH_PFC_PIN_GROUP(i2c1_d),
4510 SH_PFC_PIN_GROUP(i2c1_e),
4511 SH_PFC_PIN_GROUP(i2c2),
4512 SH_PFC_PIN_GROUP(i2c2_b),
4513 SH_PFC_PIN_GROUP(i2c2_c),
4514 SH_PFC_PIN_GROUP(i2c2_d),
4515 SH_PFC_PIN_GROUP(i2c3),
4516 SH_PFC_PIN_GROUP(i2c3_b),
4517 SH_PFC_PIN_GROUP(i2c3_c),
4518 SH_PFC_PIN_GROUP(i2c3_d),
4519 SH_PFC_PIN_GROUP(i2c4),
4520 SH_PFC_PIN_GROUP(i2c4_b),
4521 SH_PFC_PIN_GROUP(i2c4_c),
4522 SH_PFC_PIN_GROUP(i2c7),
4523 SH_PFC_PIN_GROUP(i2c7_b),
4524 SH_PFC_PIN_GROUP(i2c7_c),
4525 SH_PFC_PIN_GROUP(i2c8),
4526 SH_PFC_PIN_GROUP(i2c8_b),
4527 SH_PFC_PIN_GROUP(i2c8_c),
4528 SH_PFC_PIN_GROUP(intc_irq0),
4529 SH_PFC_PIN_GROUP(intc_irq1),
4530 SH_PFC_PIN_GROUP(intc_irq2),
4531 SH_PFC_PIN_GROUP(intc_irq3),
4532 BUS_DATA_PIN_GROUP(mmc_data, 1),
4533 BUS_DATA_PIN_GROUP(mmc_data, 4),
4534 BUS_DATA_PIN_GROUP(mmc_data, 8),
4535 BUS_DATA_PIN_GROUP(mmc_data, 8, _b),
4536 SH_PFC_PIN_GROUP(mmc_ctrl),
4537 SH_PFC_PIN_GROUP(msiof0_clk),
4538 SH_PFC_PIN_GROUP(msiof0_sync),
4539 SH_PFC_PIN_GROUP(msiof0_ss1),
4540 SH_PFC_PIN_GROUP(msiof0_ss2),
4541 SH_PFC_PIN_GROUP(msiof0_rx),
4542 SH_PFC_PIN_GROUP(msiof0_tx),
4543 SH_PFC_PIN_GROUP(msiof0_clk_b),
4544 SH_PFC_PIN_GROUP(msiof0_sync_b),
4545 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4546 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4547 SH_PFC_PIN_GROUP(msiof0_rx_b),
4548 SH_PFC_PIN_GROUP(msiof0_tx_b),
4549 SH_PFC_PIN_GROUP(msiof0_clk_c),
4550 SH_PFC_PIN_GROUP(msiof0_sync_c),
4551 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4552 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4553 SH_PFC_PIN_GROUP(msiof0_rx_c),
4554 SH_PFC_PIN_GROUP(msiof0_tx_c),
4555 SH_PFC_PIN_GROUP(msiof1_clk),
4556 SH_PFC_PIN_GROUP(msiof1_sync),
4557 SH_PFC_PIN_GROUP(msiof1_ss1),
4558 SH_PFC_PIN_GROUP(msiof1_ss2),
4559 SH_PFC_PIN_GROUP(msiof1_rx),
4560 SH_PFC_PIN_GROUP(msiof1_tx),
4561 SH_PFC_PIN_GROUP(msiof1_clk_b),
4562 SH_PFC_PIN_GROUP(msiof1_sync_b),
4563 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4564 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4565 SH_PFC_PIN_GROUP(msiof1_rx_b),
4566 SH_PFC_PIN_GROUP(msiof1_tx_b),
4567 SH_PFC_PIN_GROUP(msiof1_clk_c),
4568 SH_PFC_PIN_GROUP(msiof1_sync_c),
4569 SH_PFC_PIN_GROUP(msiof1_rx_c),
4570 SH_PFC_PIN_GROUP(msiof1_tx_c),
4571 SH_PFC_PIN_GROUP(msiof1_clk_d),
4572 SH_PFC_PIN_GROUP(msiof1_sync_d),
4573 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4574 SH_PFC_PIN_GROUP(msiof1_rx_d),
4575 SH_PFC_PIN_GROUP(msiof1_tx_d),
4576 SH_PFC_PIN_GROUP(msiof1_clk_e),
4577 SH_PFC_PIN_GROUP(msiof1_sync_e),
4578 SH_PFC_PIN_GROUP(msiof1_rx_e),
4579 SH_PFC_PIN_GROUP(msiof1_tx_e),
4580 SH_PFC_PIN_GROUP(msiof2_clk),
4581 SH_PFC_PIN_GROUP(msiof2_sync),
4582 SH_PFC_PIN_GROUP(msiof2_ss1),
4583 SH_PFC_PIN_GROUP(msiof2_ss2),
4584 SH_PFC_PIN_GROUP(msiof2_rx),
4585 SH_PFC_PIN_GROUP(msiof2_tx),
4586 SH_PFC_PIN_GROUP(msiof2_clk_b),
4587 SH_PFC_PIN_GROUP(msiof2_sync_b),
4588 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4589 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4590 SH_PFC_PIN_GROUP(msiof2_rx_b),
4591 SH_PFC_PIN_GROUP(msiof2_tx_b),
4592 SH_PFC_PIN_GROUP(msiof2_clk_c),
4593 SH_PFC_PIN_GROUP(msiof2_sync_c),
4594 SH_PFC_PIN_GROUP(msiof2_rx_c),
4595 SH_PFC_PIN_GROUP(msiof2_tx_c),
4596 SH_PFC_PIN_GROUP(msiof2_clk_d),
4597 SH_PFC_PIN_GROUP(msiof2_sync_d),
4598 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4599 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4600 SH_PFC_PIN_GROUP(msiof2_rx_d),
4601 SH_PFC_PIN_GROUP(msiof2_tx_d),
4602 SH_PFC_PIN_GROUP(msiof2_clk_e),
4603 SH_PFC_PIN_GROUP(msiof2_sync_e),
4604 SH_PFC_PIN_GROUP(msiof2_rx_e),
4605 SH_PFC_PIN_GROUP(msiof2_tx_e),
4606 SH_PFC_PIN_GROUP(pwm0),
4607 SH_PFC_PIN_GROUP(pwm0_b),
4608 SH_PFC_PIN_GROUP(pwm1),
4609 SH_PFC_PIN_GROUP(pwm1_b),
4610 SH_PFC_PIN_GROUP(pwm2),
4611 SH_PFC_PIN_GROUP(pwm2_b),
4612 SH_PFC_PIN_GROUP(pwm3),
4613 SH_PFC_PIN_GROUP(pwm4),
4614 SH_PFC_PIN_GROUP(pwm4_b),
4615 SH_PFC_PIN_GROUP(pwm5),
4616 SH_PFC_PIN_GROUP(pwm5_b),
4617 SH_PFC_PIN_GROUP(pwm6),
4618 SH_PFC_PIN_GROUP(qspi_ctrl),
4619 BUS_DATA_PIN_GROUP(qspi_data, 2),
4620 BUS_DATA_PIN_GROUP(qspi_data, 4),
4621 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4622 BUS_DATA_PIN_GROUP(qspi_data, 2, _b),
4623 BUS_DATA_PIN_GROUP(qspi_data, 4, _b),
4624 SH_PFC_PIN_GROUP(scif0_data),
4625 SH_PFC_PIN_GROUP(scif0_data_b),
4626 SH_PFC_PIN_GROUP(scif0_data_c),
4627 SH_PFC_PIN_GROUP(scif0_data_d),
4628 SH_PFC_PIN_GROUP(scif0_data_e),
4629 SH_PFC_PIN_GROUP(scif1_data),
4630 SH_PFC_PIN_GROUP(scif1_data_b),
4631 SH_PFC_PIN_GROUP(scif1_clk_b),
4632 SH_PFC_PIN_GROUP(scif1_data_c),
4633 SH_PFC_PIN_GROUP(scif1_data_d),
4634 SH_PFC_PIN_GROUP(scif2_data),
4635 SH_PFC_PIN_GROUP(scif2_data_b),
4636 SH_PFC_PIN_GROUP(scif2_clk_b),
4637 SH_PFC_PIN_GROUP(scif2_data_c),
4638 SH_PFC_PIN_GROUP(scif2_data_e),
4639 SH_PFC_PIN_GROUP(scif3_data),
4640 SH_PFC_PIN_GROUP(scif3_clk),
4641 SH_PFC_PIN_GROUP(scif3_data_b),
4642 SH_PFC_PIN_GROUP(scif3_clk_b),
4643 SH_PFC_PIN_GROUP(scif3_data_c),
4644 SH_PFC_PIN_GROUP(scif3_data_d),
4645 SH_PFC_PIN_GROUP(scif4_data),
4646 SH_PFC_PIN_GROUP(scif4_data_b),
4647 SH_PFC_PIN_GROUP(scif4_data_c),
4648 SH_PFC_PIN_GROUP(scif5_data),
4649 SH_PFC_PIN_GROUP(scif5_data_b),
4650 SH_PFC_PIN_GROUP(scifa0_data),
4651 SH_PFC_PIN_GROUP(scifa0_data_b),
4652 SH_PFC_PIN_GROUP(scifa1_data),
4653 SH_PFC_PIN_GROUP(scifa1_clk),
4654 SH_PFC_PIN_GROUP(scifa1_data_b),
4655 SH_PFC_PIN_GROUP(scifa1_clk_b),
4656 SH_PFC_PIN_GROUP(scifa1_data_c),
4657 SH_PFC_PIN_GROUP(scifa2_data),
4658 SH_PFC_PIN_GROUP(scifa2_clk),
4659 SH_PFC_PIN_GROUP(scifa2_data_b),
4660 SH_PFC_PIN_GROUP(scifa3_data),
4661 SH_PFC_PIN_GROUP(scifa3_clk),
4662 SH_PFC_PIN_GROUP(scifa3_data_b),
4663 SH_PFC_PIN_GROUP(scifa3_clk_b),
4664 SH_PFC_PIN_GROUP(scifa3_data_c),
4665 SH_PFC_PIN_GROUP(scifa3_clk_c),
4666 SH_PFC_PIN_GROUP(scifa4_data),
4667 SH_PFC_PIN_GROUP(scifa4_data_b),
4668 SH_PFC_PIN_GROUP(scifa4_data_c),
4669 SH_PFC_PIN_GROUP(scifa5_data),
4670 SH_PFC_PIN_GROUP(scifa5_data_b),
4671 SH_PFC_PIN_GROUP(scifa5_data_c),
4672 SH_PFC_PIN_GROUP(scifb0_data),
4673 SH_PFC_PIN_GROUP(scifb0_clk),
4674 SH_PFC_PIN_GROUP(scifb0_ctrl),
4675 SH_PFC_PIN_GROUP(scifb0_data_b),
4676 SH_PFC_PIN_GROUP(scifb0_clk_b),
4677 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4678 SH_PFC_PIN_GROUP(scifb0_data_c),
4679 SH_PFC_PIN_GROUP(scifb0_clk_c),
4680 SH_PFC_PIN_GROUP(scifb0_data_d),
4681 SH_PFC_PIN_GROUP(scifb0_clk_d),
4682 SH_PFC_PIN_GROUP(scifb1_data),
4683 SH_PFC_PIN_GROUP(scifb1_clk),
4684 SH_PFC_PIN_GROUP(scifb1_ctrl),
4685 SH_PFC_PIN_GROUP(scifb1_data_b),
4686 SH_PFC_PIN_GROUP(scifb1_clk_b),
4687 SH_PFC_PIN_GROUP(scifb1_data_c),
4688 SH_PFC_PIN_GROUP(scifb1_clk_c),
4689 SH_PFC_PIN_GROUP(scifb1_data_d),
4690 SH_PFC_PIN_GROUP(scifb2_data),
4691 SH_PFC_PIN_GROUP(scifb2_clk),
4692 SH_PFC_PIN_GROUP(scifb2_ctrl),
4693 SH_PFC_PIN_GROUP(scifb2_data_b),
4694 SH_PFC_PIN_GROUP(scifb2_clk_b),
4695 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4696 SH_PFC_PIN_GROUP(scifb2_data_c),
4697 SH_PFC_PIN_GROUP(scifb2_clk_c),
4698 SH_PFC_PIN_GROUP(scifb2_data_d),
4699 SH_PFC_PIN_GROUP(scif_clk),
4700 SH_PFC_PIN_GROUP(scif_clk_b),
4701 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4702 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4703 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4704 SH_PFC_PIN_GROUP(sdhi0_cd),
4705 SH_PFC_PIN_GROUP(sdhi0_wp),
4706 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4707 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4708 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4709 SH_PFC_PIN_GROUP(sdhi1_cd),
4710 SH_PFC_PIN_GROUP(sdhi1_wp),
4711 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4712 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4713 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4714 SH_PFC_PIN_GROUP(sdhi2_cd),
4715 SH_PFC_PIN_GROUP(sdhi2_wp),
4716 SH_PFC_PIN_GROUP(ssi0_data),
4717 SH_PFC_PIN_GROUP(ssi0_data_b),
4718 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4719 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4720 SH_PFC_PIN_GROUP(ssi1_data),
4721 SH_PFC_PIN_GROUP(ssi1_data_b),
4722 SH_PFC_PIN_GROUP(ssi1_ctrl),
4723 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4724 SH_PFC_PIN_GROUP(ssi2_data),
4725 SH_PFC_PIN_GROUP(ssi2_ctrl),
4726 SH_PFC_PIN_GROUP(ssi3_data),
4727 SH_PFC_PIN_GROUP(ssi34_ctrl),
4728 SH_PFC_PIN_GROUP(ssi4_data),
4729 SH_PFC_PIN_GROUP(ssi4_ctrl),
4730 SH_PFC_PIN_GROUP(ssi5_data),
4731 SH_PFC_PIN_GROUP(ssi5_ctrl),
4732 SH_PFC_PIN_GROUP(ssi6_data),
4733 SH_PFC_PIN_GROUP(ssi6_ctrl),
4734 SH_PFC_PIN_GROUP(ssi7_data),
4735 SH_PFC_PIN_GROUP(ssi7_data_b),
4736 SH_PFC_PIN_GROUP(ssi78_ctrl),
4737 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4738 SH_PFC_PIN_GROUP(ssi8_data),
4739 SH_PFC_PIN_GROUP(ssi8_data_b),
4740 SH_PFC_PIN_GROUP(ssi9_data),
4741 SH_PFC_PIN_GROUP(ssi9_data_b),
4742 SH_PFC_PIN_GROUP(ssi9_ctrl),
4743 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4744 SH_PFC_PIN_GROUP(tpu_to0),
4745 SH_PFC_PIN_GROUP(tpu_to1),
4746 SH_PFC_PIN_GROUP(tpu_to2),
4747 SH_PFC_PIN_GROUP(tpu_to3),
4748 SH_PFC_PIN_GROUP(usb0),
4749 SH_PFC_PIN_GROUP(usb1),
4750 BUS_DATA_PIN_GROUP(vin0_data, 24),
4751 BUS_DATA_PIN_GROUP(vin0_data, 20),
4752 SH_PFC_PIN_GROUP(vin0_data18),
4753 BUS_DATA_PIN_GROUP(vin0_data, 16),
4754 BUS_DATA_PIN_GROUP(vin0_data, 12),
4755 BUS_DATA_PIN_GROUP(vin0_data, 10),
4756 BUS_DATA_PIN_GROUP(vin0_data, 8),
4757 SH_PFC_PIN_GROUP(vin0_sync),
4758 SH_PFC_PIN_GROUP(vin0_field),
4759 SH_PFC_PIN_GROUP(vin0_clkenb),
4760 SH_PFC_PIN_GROUP(vin0_clk),
4761 SH_PFC_PIN_GROUP(vin1_data8),
4762 SH_PFC_PIN_GROUP(vin1_sync),
4763 SH_PFC_PIN_GROUP(vin1_field),
4764 SH_PFC_PIN_GROUP(vin1_clkenb),
4765 SH_PFC_PIN_GROUP(vin1_clk),
4766 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4767 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
4768 SH_PFC_PIN_GROUP(vin1_data18_b),
4769 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4770 BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4771 BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4772 BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
4773 SH_PFC_PIN_GROUP(vin1_sync_b),
4774 SH_PFC_PIN_GROUP(vin1_field_b),
4775 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4776 SH_PFC_PIN_GROUP(vin1_clk_b),
4777 SH_PFC_PIN_GROUP(vin2_data8),
4778 SH_PFC_PIN_GROUP(vin2_sync),
4779 SH_PFC_PIN_GROUP(vin2_field),
4780 SH_PFC_PIN_GROUP(vin2_clkenb),
4781 SH_PFC_PIN_GROUP(vin2_clk),
4782 },
4783#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4784 .automotive = {
4785 SH_PFC_PIN_GROUP(adi_common),
4786 SH_PFC_PIN_GROUP(adi_chsel0),
4787 SH_PFC_PIN_GROUP(adi_chsel1),
4788 SH_PFC_PIN_GROUP(adi_chsel2),
4789 SH_PFC_PIN_GROUP(adi_common_b),
4790 SH_PFC_PIN_GROUP(adi_chsel0_b),
4791 SH_PFC_PIN_GROUP(adi_chsel1_b),
4792 SH_PFC_PIN_GROUP(adi_chsel2_b),
4793 SH_PFC_PIN_GROUP(mlb_3pin),
4794 }
4795#endif
4796};
4797
4798#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4799static const char * const adi_groups[] = {
4800 "adi_common",
4801 "adi_chsel0",
4802 "adi_chsel1",
4803 "adi_chsel2",
4804 "adi_common_b",
4805 "adi_chsel0_b",
4806 "adi_chsel1_b",
4807 "adi_chsel2_b",
4808};
4809#endif
4810
4811static const char * const audio_clk_groups[] = {
4812 "audio_clk_a",
4813 "audio_clk_b",
4814 "audio_clk_b_b",
4815 "audio_clk_c",
4816 "audio_clkout",
4817};
4818
4819static const char * const avb_groups[] = {
4820 "avb_link",
4821 "avb_magic",
4822 "avb_phy_int",
4823 "avb_mdio",
4824 "avb_mii",
4825 "avb_gmii",
4826};
4827
4828static const char * const can0_groups[] = {
4829 "can0_data",
4830 "can0_data_b",
4831 "can0_data_c",
4832 "can0_data_d",
4833 "can0_data_e",
4834 "can0_data_f",
4835
4836
4837
4838
4839 "can_clk",
4840 "can_clk_b",
4841 "can_clk_c",
4842 "can_clk_d",
4843};
4844
4845static const char * const can1_groups[] = {
4846 "can1_data",
4847 "can1_data_b",
4848 "can1_data_c",
4849 "can1_data_d",
4850
4851
4852
4853
4854 "can_clk",
4855 "can_clk_b",
4856 "can_clk_c",
4857 "can_clk_d",
4858};
4859
4860
4861
4862
4863
4864static const char * const can_clk_groups[] = {
4865 "can_clk",
4866 "can_clk_b",
4867 "can_clk_c",
4868 "can_clk_d",
4869};
4870
4871static const char * const du_groups[] = {
4872 "du_rgb666",
4873 "du_rgb888",
4874 "du_clk_out_0",
4875 "du_clk_out_1",
4876 "du_sync",
4877 "du_oddf",
4878 "du_cde",
4879 "du_disp",
4880};
4881
4882static const char * const du0_groups[] = {
4883 "du0_clk_in",
4884};
4885
4886static const char * const du1_groups[] = {
4887 "du1_clk_in",
4888 "du1_clk_in_b",
4889 "du1_clk_in_c",
4890};
4891
4892static const char * const eth_groups[] = {
4893 "eth_link",
4894 "eth_magic",
4895 "eth_mdio",
4896 "eth_rmii",
4897};
4898
4899static const char * const hscif0_groups[] = {
4900 "hscif0_data",
4901 "hscif0_clk",
4902 "hscif0_ctrl",
4903 "hscif0_data_b",
4904 "hscif0_ctrl_b",
4905 "hscif0_data_c",
4906 "hscif0_clk_c",
4907};
4908
4909static const char * const hscif1_groups[] = {
4910 "hscif1_data",
4911 "hscif1_clk",
4912 "hscif1_ctrl",
4913 "hscif1_data_b",
4914 "hscif1_data_c",
4915 "hscif1_clk_c",
4916 "hscif1_ctrl_c",
4917 "hscif1_data_d",
4918 "hscif1_data_e",
4919 "hscif1_clk_e",
4920 "hscif1_ctrl_e",
4921};
4922
4923static const char * const hscif2_groups[] = {
4924 "hscif2_data",
4925 "hscif2_clk",
4926 "hscif2_ctrl",
4927 "hscif2_data_b",
4928 "hscif2_ctrl_b",
4929 "hscif2_data_c",
4930 "hscif2_clk_c",
4931 "hscif2_data_d",
4932};
4933
4934static const char * const i2c0_groups[] = {
4935 "i2c0",
4936 "i2c0_b",
4937 "i2c0_c",
4938};
4939
4940static const char * const i2c1_groups[] = {
4941 "i2c1",
4942 "i2c1_b",
4943 "i2c1_c",
4944 "i2c1_d",
4945 "i2c1_e",
4946};
4947
4948static const char * const i2c2_groups[] = {
4949 "i2c2",
4950 "i2c2_b",
4951 "i2c2_c",
4952 "i2c2_d",
4953};
4954
4955static const char * const i2c3_groups[] = {
4956 "i2c3",
4957 "i2c3_b",
4958 "i2c3_c",
4959 "i2c3_d",
4960};
4961
4962static const char * const i2c4_groups[] = {
4963 "i2c4",
4964 "i2c4_b",
4965 "i2c4_c",
4966};
4967
4968static const char * const i2c7_groups[] = {
4969 "i2c7",
4970 "i2c7_b",
4971 "i2c7_c",
4972};
4973
4974static const char * const i2c8_groups[] = {
4975 "i2c8",
4976 "i2c8_b",
4977 "i2c8_c",
4978};
4979
4980static const char * const intc_groups[] = {
4981 "intc_irq0",
4982 "intc_irq1",
4983 "intc_irq2",
4984 "intc_irq3",
4985};
4986
4987#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4988static const char * const mlb_groups[] = {
4989 "mlb_3pin",
4990};
4991#endif
4992
4993static const char * const mmc_groups[] = {
4994 "mmc_data1",
4995 "mmc_data4",
4996 "mmc_data8",
4997 "mmc_data8_b",
4998 "mmc_ctrl",
4999};
5000
5001static const char * const msiof0_groups[] = {
5002 "msiof0_clk",
5003 "msiof0_sync",
5004 "msiof0_ss1",
5005 "msiof0_ss2",
5006 "msiof0_rx",
5007 "msiof0_tx",
5008 "msiof0_clk_b",
5009 "msiof0_sync_b",
5010 "msiof0_ss1_b",
5011 "msiof0_ss2_b",
5012 "msiof0_rx_b",
5013 "msiof0_tx_b",
5014 "msiof0_clk_c",
5015 "msiof0_sync_c",
5016 "msiof0_ss1_c",
5017 "msiof0_ss2_c",
5018 "msiof0_rx_c",
5019 "msiof0_tx_c",
5020};
5021
5022static const char * const msiof1_groups[] = {
5023 "msiof1_clk",
5024 "msiof1_sync",
5025 "msiof1_ss1",
5026 "msiof1_ss2",
5027 "msiof1_rx",
5028 "msiof1_tx",
5029 "msiof1_clk_b",
5030 "msiof1_sync_b",
5031 "msiof1_ss1_b",
5032 "msiof1_ss2_b",
5033 "msiof1_rx_b",
5034 "msiof1_tx_b",
5035 "msiof1_clk_c",
5036 "msiof1_sync_c",
5037 "msiof1_rx_c",
5038 "msiof1_tx_c",
5039 "msiof1_clk_d",
5040 "msiof1_sync_d",
5041 "msiof1_ss1_d",
5042 "msiof1_rx_d",
5043 "msiof1_tx_d",
5044 "msiof1_clk_e",
5045 "msiof1_sync_e",
5046 "msiof1_rx_e",
5047 "msiof1_tx_e",
5048};
5049
5050static const char * const msiof2_groups[] = {
5051 "msiof2_clk",
5052 "msiof2_sync",
5053 "msiof2_ss1",
5054 "msiof2_ss2",
5055 "msiof2_rx",
5056 "msiof2_tx",
5057 "msiof2_clk_b",
5058 "msiof2_sync_b",
5059 "msiof2_ss1_b",
5060 "msiof2_ss2_b",
5061 "msiof2_rx_b",
5062 "msiof2_tx_b",
5063 "msiof2_clk_c",
5064 "msiof2_sync_c",
5065 "msiof2_rx_c",
5066 "msiof2_tx_c",
5067 "msiof2_clk_d",
5068 "msiof2_sync_d",
5069 "msiof2_ss1_d",
5070 "msiof2_ss2_d",
5071 "msiof2_rx_d",
5072 "msiof2_tx_d",
5073 "msiof2_clk_e",
5074 "msiof2_sync_e",
5075 "msiof2_rx_e",
5076 "msiof2_tx_e",
5077};
5078
5079static const char * const pwm0_groups[] = {
5080 "pwm0",
5081 "pwm0_b",
5082};
5083
5084static const char * const pwm1_groups[] = {
5085 "pwm1",
5086 "pwm1_b",
5087};
5088
5089static const char * const pwm2_groups[] = {
5090 "pwm2",
5091 "pwm2_b",
5092};
5093
5094static const char * const pwm3_groups[] = {
5095 "pwm3",
5096};
5097
5098static const char * const pwm4_groups[] = {
5099 "pwm4",
5100 "pwm4_b",
5101};
5102
5103static const char * const pwm5_groups[] = {
5104 "pwm5",
5105 "pwm5_b",
5106};
5107
5108static const char * const pwm6_groups[] = {
5109 "pwm6",
5110};
5111
5112static const char * const qspi_groups[] = {
5113 "qspi_ctrl",
5114 "qspi_data2",
5115 "qspi_data4",
5116 "qspi_ctrl_b",
5117 "qspi_data2_b",
5118 "qspi_data4_b",
5119};
5120
5121static const char * const scif0_groups[] = {
5122 "scif0_data",
5123 "scif0_data_b",
5124 "scif0_data_c",
5125 "scif0_data_d",
5126 "scif0_data_e",
5127};
5128
5129static const char * const scif1_groups[] = {
5130 "scif1_data",
5131 "scif1_data_b",
5132 "scif1_clk_b",
5133 "scif1_data_c",
5134 "scif1_data_d",
5135};
5136
5137static const char * const scif2_groups[] = {
5138 "scif2_data",
5139 "scif2_data_b",
5140 "scif2_clk_b",
5141 "scif2_data_c",
5142 "scif2_data_e",
5143};
5144static const char * const scif3_groups[] = {
5145 "scif3_data",
5146 "scif3_clk",
5147 "scif3_data_b",
5148 "scif3_clk_b",
5149 "scif3_data_c",
5150 "scif3_data_d",
5151};
5152static const char * const scif4_groups[] = {
5153 "scif4_data",
5154 "scif4_data_b",
5155 "scif4_data_c",
5156};
5157static const char * const scif5_groups[] = {
5158 "scif5_data",
5159 "scif5_data_b",
5160};
5161static const char * const scifa0_groups[] = {
5162 "scifa0_data",
5163 "scifa0_data_b",
5164};
5165static const char * const scifa1_groups[] = {
5166 "scifa1_data",
5167 "scifa1_clk",
5168 "scifa1_data_b",
5169 "scifa1_clk_b",
5170 "scifa1_data_c",
5171};
5172static const char * const scifa2_groups[] = {
5173 "scifa2_data",
5174 "scifa2_clk",
5175 "scifa2_data_b",
5176};
5177static const char * const scifa3_groups[] = {
5178 "scifa3_data",
5179 "scifa3_clk",
5180 "scifa3_data_b",
5181 "scifa3_clk_b",
5182 "scifa3_data_c",
5183 "scifa3_clk_c",
5184};
5185static const char * const scifa4_groups[] = {
5186 "scifa4_data",
5187 "scifa4_data_b",
5188 "scifa4_data_c",
5189};
5190static const char * const scifa5_groups[] = {
5191 "scifa5_data",
5192 "scifa5_data_b",
5193 "scifa5_data_c",
5194};
5195static const char * const scifb0_groups[] = {
5196 "scifb0_data",
5197 "scifb0_clk",
5198 "scifb0_ctrl",
5199 "scifb0_data_b",
5200 "scifb0_clk_b",
5201 "scifb0_ctrl_b",
5202 "scifb0_data_c",
5203 "scifb0_clk_c",
5204 "scifb0_data_d",
5205 "scifb0_clk_d",
5206};
5207static const char * const scifb1_groups[] = {
5208 "scifb1_data",
5209 "scifb1_clk",
5210 "scifb1_ctrl",
5211 "scifb1_data_b",
5212 "scifb1_clk_b",
5213 "scifb1_data_c",
5214 "scifb1_clk_c",
5215 "scifb1_data_d",
5216};
5217static const char * const scifb2_groups[] = {
5218 "scifb2_data",
5219 "scifb2_clk",
5220 "scifb2_ctrl",
5221 "scifb2_data_b",
5222 "scifb2_clk_b",
5223 "scifb2_ctrl_b",
5224 "scifb2_data_c",
5225 "scifb2_clk_c",
5226 "scifb2_data_d",
5227};
5228
5229static const char * const scif_clk_groups[] = {
5230 "scif_clk",
5231 "scif_clk_b",
5232};
5233
5234static const char * const sdhi0_groups[] = {
5235 "sdhi0_data1",
5236 "sdhi0_data4",
5237 "sdhi0_ctrl",
5238 "sdhi0_cd",
5239 "sdhi0_wp",
5240};
5241
5242static const char * const sdhi1_groups[] = {
5243 "sdhi1_data1",
5244 "sdhi1_data4",
5245 "sdhi1_ctrl",
5246 "sdhi1_cd",
5247 "sdhi1_wp",
5248};
5249
5250static const char * const sdhi2_groups[] = {
5251 "sdhi2_data1",
5252 "sdhi2_data4",
5253 "sdhi2_ctrl",
5254 "sdhi2_cd",
5255 "sdhi2_wp",
5256};
5257
5258static const char * const ssi_groups[] = {
5259 "ssi0_data",
5260 "ssi0_data_b",
5261 "ssi0129_ctrl",
5262 "ssi0129_ctrl_b",
5263 "ssi1_data",
5264 "ssi1_data_b",
5265 "ssi1_ctrl",
5266 "ssi1_ctrl_b",
5267 "ssi2_data",
5268 "ssi2_ctrl",
5269 "ssi3_data",
5270 "ssi34_ctrl",
5271 "ssi4_data",
5272 "ssi4_ctrl",
5273 "ssi5_data",
5274 "ssi5_ctrl",
5275 "ssi6_data",
5276 "ssi6_ctrl",
5277 "ssi7_data",
5278 "ssi7_data_b",
5279 "ssi78_ctrl",
5280 "ssi78_ctrl_b",
5281 "ssi8_data",
5282 "ssi8_data_b",
5283 "ssi9_data",
5284 "ssi9_data_b",
5285 "ssi9_ctrl",
5286 "ssi9_ctrl_b",
5287};
5288
5289static const char * const tpu_groups[] = {
5290 "tpu_to0",
5291 "tpu_to1",
5292 "tpu_to2",
5293 "tpu_to3",
5294};
5295
5296static const char * const usb0_groups[] = {
5297 "usb0",
5298};
5299static const char * const usb1_groups[] = {
5300 "usb1",
5301};
5302
5303static const char * const vin0_groups[] = {
5304 "vin0_data24",
5305 "vin0_data20",
5306 "vin0_data18",
5307 "vin0_data16",
5308 "vin0_data12",
5309 "vin0_data10",
5310 "vin0_data8",
5311 "vin0_sync",
5312 "vin0_field",
5313 "vin0_clkenb",
5314 "vin0_clk",
5315};
5316
5317static const char * const vin1_groups[] = {
5318 "vin1_data8",
5319 "vin1_sync",
5320 "vin1_field",
5321 "vin1_clkenb",
5322 "vin1_clk",
5323 "vin1_data24_b",
5324 "vin1_data20_b",
5325 "vin1_data18_b",
5326 "vin1_data16_b",
5327 "vin1_data12_b",
5328 "vin1_data10_b",
5329 "vin1_data8_b",
5330 "vin1_sync_b",
5331 "vin1_field_b",
5332 "vin1_clkenb_b",
5333 "vin1_clk_b",
5334};
5335
5336static const char * const vin2_groups[] = {
5337 "vin2_data8",
5338 "vin2_sync",
5339 "vin2_field",
5340 "vin2_clkenb",
5341 "vin2_clk",
5342};
5343
5344static const struct {
5345 struct sh_pfc_function common[58];
5346#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5347 struct sh_pfc_function automotive[2];
5348#endif
5349} pinmux_functions = {
5350 .common = {
5351 SH_PFC_FUNCTION(audio_clk),
5352 SH_PFC_FUNCTION(avb),
5353 SH_PFC_FUNCTION(can0),
5354 SH_PFC_FUNCTION(can1),
5355 SH_PFC_FUNCTION(can_clk),
5356 SH_PFC_FUNCTION(du),
5357 SH_PFC_FUNCTION(du0),
5358 SH_PFC_FUNCTION(du1),
5359 SH_PFC_FUNCTION(eth),
5360 SH_PFC_FUNCTION(hscif0),
5361 SH_PFC_FUNCTION(hscif1),
5362 SH_PFC_FUNCTION(hscif2),
5363 SH_PFC_FUNCTION(i2c0),
5364 SH_PFC_FUNCTION(i2c1),
5365 SH_PFC_FUNCTION(i2c2),
5366 SH_PFC_FUNCTION(i2c3),
5367 SH_PFC_FUNCTION(i2c4),
5368 SH_PFC_FUNCTION(i2c7),
5369 SH_PFC_FUNCTION(i2c8),
5370 SH_PFC_FUNCTION(intc),
5371 SH_PFC_FUNCTION(mmc),
5372 SH_PFC_FUNCTION(msiof0),
5373 SH_PFC_FUNCTION(msiof1),
5374 SH_PFC_FUNCTION(msiof2),
5375 SH_PFC_FUNCTION(pwm0),
5376 SH_PFC_FUNCTION(pwm1),
5377 SH_PFC_FUNCTION(pwm2),
5378 SH_PFC_FUNCTION(pwm3),
5379 SH_PFC_FUNCTION(pwm4),
5380 SH_PFC_FUNCTION(pwm5),
5381 SH_PFC_FUNCTION(pwm6),
5382 SH_PFC_FUNCTION(qspi),
5383 SH_PFC_FUNCTION(scif0),
5384 SH_PFC_FUNCTION(scif1),
5385 SH_PFC_FUNCTION(scif2),
5386 SH_PFC_FUNCTION(scif3),
5387 SH_PFC_FUNCTION(scif4),
5388 SH_PFC_FUNCTION(scif5),
5389 SH_PFC_FUNCTION(scifa0),
5390 SH_PFC_FUNCTION(scifa1),
5391 SH_PFC_FUNCTION(scifa2),
5392 SH_PFC_FUNCTION(scifa3),
5393 SH_PFC_FUNCTION(scifa4),
5394 SH_PFC_FUNCTION(scifa5),
5395 SH_PFC_FUNCTION(scifb0),
5396 SH_PFC_FUNCTION(scifb1),
5397 SH_PFC_FUNCTION(scifb2),
5398 SH_PFC_FUNCTION(scif_clk),
5399 SH_PFC_FUNCTION(sdhi0),
5400 SH_PFC_FUNCTION(sdhi1),
5401 SH_PFC_FUNCTION(sdhi2),
5402 SH_PFC_FUNCTION(ssi),
5403 SH_PFC_FUNCTION(tpu),
5404 SH_PFC_FUNCTION(usb0),
5405 SH_PFC_FUNCTION(usb1),
5406 SH_PFC_FUNCTION(vin0),
5407 SH_PFC_FUNCTION(vin1),
5408 SH_PFC_FUNCTION(vin2),
5409 },
5410#if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5411 .automotive = {
5412 SH_PFC_FUNCTION(adi),
5413 SH_PFC_FUNCTION(mlb),
5414 }
5415#endif
5416};
5417
5418static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5419 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5420 GP_0_31_FN, FN_IP1_22_20,
5421 GP_0_30_FN, FN_IP1_19_17,
5422 GP_0_29_FN, FN_IP1_16_14,
5423 GP_0_28_FN, FN_IP1_13_11,
5424 GP_0_27_FN, FN_IP1_10_8,
5425 GP_0_26_FN, FN_IP1_7_6,
5426 GP_0_25_FN, FN_IP1_5_4,
5427 GP_0_24_FN, FN_IP1_3_2,
5428 GP_0_23_FN, FN_IP1_1_0,
5429 GP_0_22_FN, FN_IP0_30_29,
5430 GP_0_21_FN, FN_IP0_28_27,
5431 GP_0_20_FN, FN_IP0_26_25,
5432 GP_0_19_FN, FN_IP0_24_23,
5433 GP_0_18_FN, FN_IP0_22_21,
5434 GP_0_17_FN, FN_IP0_20_19,
5435 GP_0_16_FN, FN_IP0_18_16,
5436 GP_0_15_FN, FN_IP0_15,
5437 GP_0_14_FN, FN_IP0_14,
5438 GP_0_13_FN, FN_IP0_13,
5439 GP_0_12_FN, FN_IP0_12,
5440 GP_0_11_FN, FN_IP0_11,
5441 GP_0_10_FN, FN_IP0_10,
5442 GP_0_9_FN, FN_IP0_9,
5443 GP_0_8_FN, FN_IP0_8,
5444 GP_0_7_FN, FN_IP0_7,
5445 GP_0_6_FN, FN_IP0_6,
5446 GP_0_5_FN, FN_IP0_5,
5447 GP_0_4_FN, FN_IP0_4,
5448 GP_0_3_FN, FN_IP0_3,
5449 GP_0_2_FN, FN_IP0_2,
5450 GP_0_1_FN, FN_IP0_1,
5451 GP_0_0_FN, FN_IP0_0, ))
5452 },
5453 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5454 0, 0,
5455 0, 0,
5456 0, 0,
5457 0, 0,
5458 0, 0,
5459 0, 0,
5460 GP_1_25_FN, FN_IP3_21_20,
5461 GP_1_24_FN, FN_IP3_19_18,
5462 GP_1_23_FN, FN_IP3_17_16,
5463 GP_1_22_FN, FN_IP3_15_14,
5464 GP_1_21_FN, FN_IP3_13_12,
5465 GP_1_20_FN, FN_IP3_11_9,
5466 GP_1_19_FN, FN_RD_N,
5467 GP_1_18_FN, FN_IP3_8_6,
5468 GP_1_17_FN, FN_IP3_5_3,
5469 GP_1_16_FN, FN_IP3_2_0,
5470 GP_1_15_FN, FN_IP2_29_27,
5471 GP_1_14_FN, FN_IP2_26_25,
5472 GP_1_13_FN, FN_IP2_24_23,
5473 GP_1_12_FN, FN_EX_CS0_N,
5474 GP_1_11_FN, FN_IP2_22_21,
5475 GP_1_10_FN, FN_IP2_20_19,
5476 GP_1_9_FN, FN_IP2_18_16,
5477 GP_1_8_FN, FN_IP2_15_13,
5478 GP_1_7_FN, FN_IP2_12_10,
5479 GP_1_6_FN, FN_IP2_9_7,
5480 GP_1_5_FN, FN_IP2_6_5,
5481 GP_1_4_FN, FN_IP2_4_3,
5482 GP_1_3_FN, FN_IP2_2_0,
5483 GP_1_2_FN, FN_IP1_31_29,
5484 GP_1_1_FN, FN_IP1_28_26,
5485 GP_1_0_FN, FN_IP1_25_23, ))
5486 },
5487 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5488 GP_2_31_FN, FN_IP6_7_6,
5489 GP_2_30_FN, FN_IP6_5_3,
5490 GP_2_29_FN, FN_IP6_2_0,
5491 GP_2_28_FN, FN_AUDIO_CLKA,
5492 GP_2_27_FN, FN_IP5_31_29,
5493 GP_2_26_FN, FN_IP5_28_26,
5494 GP_2_25_FN, FN_IP5_25_24,
5495 GP_2_24_FN, FN_IP5_23_22,
5496 GP_2_23_FN, FN_IP5_21_20,
5497 GP_2_22_FN, FN_IP5_19_17,
5498 GP_2_21_FN, FN_IP5_16_15,
5499 GP_2_20_FN, FN_IP5_14_12,
5500 GP_2_19_FN, FN_IP5_11_9,
5501 GP_2_18_FN, FN_IP5_8_6,
5502 GP_2_17_FN, FN_IP5_5_3,
5503 GP_2_16_FN, FN_IP5_2_0,
5504 GP_2_15_FN, FN_IP4_30_28,
5505 GP_2_14_FN, FN_IP4_27_26,
5506 GP_2_13_FN, FN_IP4_25_24,
5507 GP_2_12_FN, FN_IP4_23_22,
5508 GP_2_11_FN, FN_IP4_21,
5509 GP_2_10_FN, FN_IP4_20,
5510 GP_2_9_FN, FN_IP4_19,
5511 GP_2_8_FN, FN_IP4_18_16,
5512 GP_2_7_FN, FN_IP4_15_13,
5513 GP_2_6_FN, FN_IP4_12_10,
5514 GP_2_5_FN, FN_IP4_9_8,
5515 GP_2_4_FN, FN_IP4_7_5,
5516 GP_2_3_FN, FN_IP4_4_2,
5517 GP_2_2_FN, FN_IP4_1_0,
5518 GP_2_1_FN, FN_IP3_30_28,
5519 GP_2_0_FN, FN_IP3_27_25 ))
5520 },
5521 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5522 GP_3_31_FN, FN_IP9_18_17,
5523 GP_3_30_FN, FN_IP9_16,
5524 GP_3_29_FN, FN_IP9_15_13,
5525 GP_3_28_FN, FN_IP9_12,
5526 GP_3_27_FN, FN_IP9_11,
5527 GP_3_26_FN, FN_IP9_10_8,
5528 GP_3_25_FN, FN_IP9_7,
5529 GP_3_24_FN, FN_IP9_6,
5530 GP_3_23_FN, FN_IP9_5_3,
5531 GP_3_22_FN, FN_IP9_2_0,
5532 GP_3_21_FN, FN_IP8_30_28,
5533 GP_3_20_FN, FN_IP8_27_26,
5534 GP_3_19_FN, FN_IP8_25_24,
5535 GP_3_18_FN, FN_IP8_23_21,
5536 GP_3_17_FN, FN_IP8_20_18,
5537 GP_3_16_FN, FN_IP8_17_15,
5538 GP_3_15_FN, FN_IP8_14_12,
5539 GP_3_14_FN, FN_IP8_11_9,
5540 GP_3_13_FN, FN_IP8_8_6,
5541 GP_3_12_FN, FN_IP8_5_3,
5542 GP_3_11_FN, FN_IP8_2_0,
5543 GP_3_10_FN, FN_IP7_29_27,
5544 GP_3_9_FN, FN_IP7_26_24,
5545 GP_3_8_FN, FN_IP7_23_21,
5546 GP_3_7_FN, FN_IP7_20_19,
5547 GP_3_6_FN, FN_IP7_18_17,
5548 GP_3_5_FN, FN_IP7_16_15,
5549 GP_3_4_FN, FN_IP7_14_13,
5550 GP_3_3_FN, FN_IP7_12_11,
5551 GP_3_2_FN, FN_IP7_10_9,
5552 GP_3_1_FN, FN_IP7_8_6,
5553 GP_3_0_FN, FN_IP7_5_3 ))
5554 },
5555 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5556 GP_4_31_FN, FN_IP15_5_4,
5557 GP_4_30_FN, FN_IP15_3_2,
5558 GP_4_29_FN, FN_IP15_1_0,
5559 GP_4_28_FN, FN_IP11_8_6,
5560 GP_4_27_FN, FN_IP11_5_3,
5561 GP_4_26_FN, FN_IP11_2_0,
5562 GP_4_25_FN, FN_IP10_31_29,
5563 GP_4_24_FN, FN_IP10_28_27,
5564 GP_4_23_FN, FN_IP10_26_25,
5565 GP_4_22_FN, FN_IP10_24_22,
5566 GP_4_21_FN, FN_IP10_21_19,
5567 GP_4_20_FN, FN_IP10_18_17,
5568 GP_4_19_FN, FN_IP10_16_15,
5569 GP_4_18_FN, FN_IP10_14_12,
5570 GP_4_17_FN, FN_IP10_11_9,
5571 GP_4_16_FN, FN_IP10_8_6,
5572 GP_4_15_FN, FN_IP10_5_3,
5573 GP_4_14_FN, FN_IP10_2_0,
5574 GP_4_13_FN, FN_IP9_31_29,
5575 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5576 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5577 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5578 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5579 GP_4_8_FN, FN_IP9_28_27,
5580 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5581 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5582 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5583 GP_4_4_FN, FN_IP9_26_25,
5584 GP_4_3_FN, FN_IP9_24_23,
5585 GP_4_2_FN, FN_IP9_22_21,
5586 GP_4_1_FN, FN_IP9_20_19,
5587 GP_4_0_FN, FN_VI0_CLK ))
5588 },
5589 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5590 GP_5_31_FN, FN_IP3_24_22,
5591 GP_5_30_FN, FN_IP13_9_7,
5592 GP_5_29_FN, FN_IP13_6_5,
5593 GP_5_28_FN, FN_IP13_4_3,
5594 GP_5_27_FN, FN_IP13_2_0,
5595 GP_5_26_FN, FN_IP12_29_27,
5596 GP_5_25_FN, FN_IP12_26_24,
5597 GP_5_24_FN, FN_IP12_23_22,
5598 GP_5_23_FN, FN_IP12_21_20,
5599 GP_5_22_FN, FN_IP12_19_18,
5600 GP_5_21_FN, FN_IP12_17_16,
5601 GP_5_20_FN, FN_IP12_15_13,
5602 GP_5_19_FN, FN_IP12_12_10,
5603 GP_5_18_FN, FN_IP12_9_7,
5604 GP_5_17_FN, FN_IP12_6_4,
5605 GP_5_16_FN, FN_IP12_3_2,
5606 GP_5_15_FN, FN_IP12_1_0,
5607 GP_5_14_FN, FN_IP11_31_30,
5608 GP_5_13_FN, FN_IP11_29_28,
5609 GP_5_12_FN, FN_IP11_27,
5610 GP_5_11_FN, FN_IP11_26,
5611 GP_5_10_FN, FN_IP11_25,
5612 GP_5_9_FN, FN_IP11_24,
5613 GP_5_8_FN, FN_IP11_23,
5614 GP_5_7_FN, FN_IP11_22,
5615 GP_5_6_FN, FN_IP11_21,
5616 GP_5_5_FN, FN_IP11_20,
5617 GP_5_4_FN, FN_IP11_19,
5618 GP_5_3_FN, FN_IP11_18_17,
5619 GP_5_2_FN, FN_IP11_16_15,
5620 GP_5_1_FN, FN_IP11_14_12,
5621 GP_5_0_FN, FN_IP11_11_9 ))
5622 },
5623 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5624 GP_6_31_FN, FN_DU0_DOTCLKIN,
5625 GP_6_30_FN, FN_USB1_OVC,
5626 GP_6_29_FN, FN_IP14_31_29,
5627 GP_6_28_FN, FN_IP14_28_26,
5628 GP_6_27_FN, FN_IP14_25_23,
5629 GP_6_26_FN, FN_IP14_22_20,
5630 GP_6_25_FN, FN_IP14_19_17,
5631 GP_6_24_FN, FN_IP14_16_14,
5632 GP_6_23_FN, FN_IP14_13_11,
5633 GP_6_22_FN, FN_IP14_10_8,
5634 GP_6_21_FN, FN_IP14_7,
5635 GP_6_20_FN, FN_IP14_6,
5636 GP_6_19_FN, FN_IP14_5,
5637 GP_6_18_FN, FN_IP14_4,
5638 GP_6_17_FN, FN_IP14_3,
5639 GP_6_16_FN, FN_IP14_2,
5640 GP_6_15_FN, FN_IP14_1_0,
5641 GP_6_14_FN, FN_IP13_30_28,
5642 GP_6_13_FN, FN_IP13_27,
5643 GP_6_12_FN, FN_IP13_26,
5644 GP_6_11_FN, FN_IP13_25,
5645 GP_6_10_FN, FN_IP13_24_23,
5646 GP_6_9_FN, FN_IP13_22,
5647 GP_6_8_FN, FN_SD1_CLK,
5648 GP_6_7_FN, FN_IP13_21_19,
5649 GP_6_6_FN, FN_IP13_18_16,
5650 GP_6_5_FN, FN_IP13_15,
5651 GP_6_4_FN, FN_IP13_14,
5652 GP_6_3_FN, FN_IP13_13,
5653 GP_6_2_FN, FN_IP13_12,
5654 GP_6_1_FN, FN_IP13_11,
5655 GP_6_0_FN, FN_IP13_10 ))
5656 },
5657 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5658 0, 0,
5659 0, 0,
5660 0, 0,
5661 0, 0,
5662 0, 0,
5663 0, 0,
5664 GP_7_25_FN, FN_USB1_PWEN,
5665 GP_7_24_FN, FN_USB0_OVC,
5666 GP_7_23_FN, FN_USB0_PWEN,
5667 GP_7_22_FN, FN_IP15_14_12,
5668 GP_7_21_FN, FN_IP15_11_9,
5669 GP_7_20_FN, FN_IP15_8_6,
5670 GP_7_19_FN, FN_IP7_2_0,
5671 GP_7_18_FN, FN_IP6_29_27,
5672 GP_7_17_FN, FN_IP6_26_24,
5673 GP_7_16_FN, FN_IP6_23_21,
5674 GP_7_15_FN, FN_IP6_20_19,
5675 GP_7_14_FN, FN_IP6_18_16,
5676 GP_7_13_FN, FN_IP6_15_14,
5677 GP_7_12_FN, FN_IP6_13_12,
5678 GP_7_11_FN, FN_IP6_11_10,
5679 GP_7_10_FN, FN_IP6_9_8,
5680 GP_7_9_FN, FN_IP16_11_10,
5681 GP_7_8_FN, FN_IP16_9_8,
5682 GP_7_7_FN, FN_IP16_7_6,
5683 GP_7_6_FN, FN_IP16_5_3,
5684 GP_7_5_FN, FN_IP16_2_0,
5685 GP_7_4_FN, FN_IP15_29_27,
5686 GP_7_3_FN, FN_IP15_26_24,
5687 GP_7_2_FN, FN_IP15_23_21,
5688 GP_7_1_FN, FN_IP15_20_18,
5689 GP_7_0_FN, FN_IP15_17_15 ))
5690 },
5691 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5692 GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
5693 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5694 GROUP(
5695
5696
5697 FN_A6, FN_MSIOF1_SCK,
5698 0, 0,
5699
5700 FN_A5, FN_MSIOF0_RXD_B,
5701 0, 0,
5702
5703 FN_A4, FN_MSIOF0_TXD_B,
5704 0, 0,
5705
5706 FN_A3, FN_MSIOF0_SS2_B,
5707 0, 0,
5708
5709 FN_A2, FN_MSIOF0_SS1_B,
5710 0, 0,
5711
5712 FN_A1, FN_MSIOF0_SYNC_B,
5713 0, 0,
5714
5715 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5716 0, 0, 0,
5717
5718 FN_D15, 0,
5719
5720 FN_D14, 0,
5721
5722 FN_D13, 0,
5723
5724 FN_D12, 0,
5725
5726 FN_D11, 0,
5727
5728 FN_D10, 0,
5729
5730 FN_D9, 0,
5731
5732 FN_D8, 0,
5733
5734 FN_D7, 0,
5735
5736 FN_D6, 0,
5737
5738 FN_D5, 0,
5739
5740 FN_D4, 0,
5741
5742 FN_D3, 0,
5743
5744 FN_D2, 0,
5745
5746 FN_D1, 0,
5747
5748 FN_D0, 0, ))
5749 },
5750 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5751 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5752 GROUP(
5753
5754 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5755 0, 0, 0,
5756
5757 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5758 0, 0, 0, 0,
5759
5760 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5761 0, 0, 0,
5762
5763 FN_A15, FN_BPFCLK_C,
5764 0, 0, 0, 0, 0, 0,
5765
5766 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5767 0, 0, 0,
5768
5769 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5770 0, 0, 0, 0,
5771
5772 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5773 0, 0, 0, 0,
5774
5775 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5776 0, 0, 0, 0,
5777
5778 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5779
5780 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5781
5782 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5783
5784 FN_A7, FN_MSIOF1_SYNC,
5785 0, 0, ))
5786 },
5787 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5788 GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
5789 GROUP(
5790
5791
5792 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5793 FN_ATAG0_N, 0, FN_EX_WAIT1,
5794 0, 0,
5795
5796 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5797
5798 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5799
5800 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5801
5802 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5803
5804 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5805 0, 0,
5806
5807 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5808 0, 0, 0,
5809
5810 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5811 0, 0, 0,
5812
5813 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5814 0, 0, 0,
5815
5816 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5817
5818 FN_A20, FN_SPCLK, 0, 0,
5819
5820 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5821 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5822 },
5823 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5824 GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
5825 GROUP(
5826
5827
5828 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5829 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5830 0, 0, 0,
5831
5832 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5833 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5834 0, 0, 0,
5835
5836 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5837 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5838
5839 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5840
5841 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5842
5843 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5844
5845 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5846
5847 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5848
5849 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5850 0, 0, 0,
5851
5852 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5853 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5854
5855 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5856 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5857
5858 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5859 0, 0, 0, ))
5860 },
5861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5862 GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
5863 3, 3, 2),
5864 GROUP(
5865
5866
5867 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5868 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5869 0, 0,
5870
5871 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5872
5873 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5874
5875 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5876
5877 FN_SSI_SDATA3, 0,
5878
5879 FN_SSI_WS34, 0,
5880
5881 FN_SSI_SCK34, 0,
5882
5883 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5884 0, 0, 0, 0,
5885
5886 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5887 FN_GLO_Q1_D, FN_HCTS1_N_E,
5888 0, 0,
5889
5890 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5891 0, 0, 0,
5892
5893 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5894
5895 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5896 FN_GLO_I1_D, 0, 0, 0,
5897
5898 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5899 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5900 0, 0, 0,
5901
5902 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
5903 ))
5904 },
5905 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5906 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
5907 GROUP(
5908
5909 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5910 0, 0, 0, 0, 0,
5911
5912 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5913 0, 0, 0, 0,
5914
5915 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5916
5917 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5918
5919 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5920
5921 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5922 0, 0, 0, 0,
5923
5924 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5925
5926 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5927 0, 0, 0, 0,
5928
5929 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5930 0, 0, 0, 0,
5931
5932 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5933 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5934 0, 0,
5935
5936 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5937 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5938 0, 0,
5939
5940 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5941 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5942 0, 0, ))
5943 },
5944 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5945 GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
5946 GROUP(
5947
5948
5949 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5950 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5951 0, 0, 0,
5952
5953 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5954 FN_GPS_CLK_C, FN_GPS_CLK_D,
5955 0, 0, 0,
5956
5957 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5958 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5959 0, 0, 0,
5960
5961 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5962
5963 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5964 0, 0, 0, 0,
5965
5966 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0,
5967
5968 FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0,
5969
5970 FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0,
5971
5972 FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0,
5973
5974 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5975
5976 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5977 FN_SCIFA2_RXD, FN_FMIN_E,
5978 0, 0,
5979
5980 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5981 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5982 0, 0, ))
5983 },
5984 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5985 GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
5986 GROUP(
5987
5988
5989 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
5990 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
5991 0, 0,
5992
5993 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
5994 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
5995 0, 0,
5996
5997 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
5998 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
5999 0, 0,
6000
6001 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6002
6003 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6004
6005 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6006
6007 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6008
6009 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6010
6011 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6012
6013 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
6014 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
6015 0, 0,
6016
6017 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
6018 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
6019 0, 0,
6020
6021 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6022 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6023 0, 0, ))
6024 },
6025 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6026 GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
6027 GROUP(
6028
6029
6030 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
6031 0, 0, 0,
6032
6033 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
6034
6035 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6036
6037 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
6038 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
6039 0, 0,
6040
6041 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6042 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6043 0, 0,
6044
6045 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6046 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6047 0, 0,
6048
6049 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6050 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6051 0, 0, 0,
6052
6053 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6054 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6055 0, 0, 0,
6056
6057 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6058 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6059 0, 0,
6060
6061 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6062 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6063 0, 0,
6064
6065 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6066 0, 0, 0, ))
6067 },
6068 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6069 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
6070 1, 1, 3, 3),
6071 GROUP(
6072
6073 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6074 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6075
6076 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6077
6078 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6079
6080 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6081
6082 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6083
6084 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6085
6086 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6087
6088 FN_DU1_DISP, FN_QPOLA,
6089
6090 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6091 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6092 0, 0, 0,
6093
6094 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6095
6096 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6097
6098 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6099 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6100 0, 0,
6101
6102 FN_DU1_DOTCLKOUT0, FN_QCLK,
6103
6104 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6105
6106 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6107 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6108 0, 0, 0,
6109
6110 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6111 0, 0, 0, ))
6112 },
6113 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6114 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
6115 GROUP(
6116
6117 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6118 0, 0, 0,
6119
6120 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6121
6122 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6123
6124 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6125 0, 0, 0,
6126
6127 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6128 FN_TS_SDATA0_C, FN_ATACS11_N,
6129 0, 0, 0,
6130
6131 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6132
6133 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6134
6135 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6136 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6137
6138 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6139 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6140 0, 0,
6141
6142 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6143 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6144
6145 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6146 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6147
6148 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6149 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6150 },
6151 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6152 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
6153 2, 3, 3, 3, 3, 3),
6154 GROUP(
6155
6156 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6157
6158 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6159
6160 FN_VI1_DATA7, FN_AVB_MDC,
6161
6162 FN_VI1_DATA6, FN_AVB_MAGIC,
6163
6164 FN_VI1_DATA5, FN_AVB_RX_DV,
6165
6166 FN_VI1_DATA4, FN_AVB_MDIO,
6167
6168 FN_VI1_DATA3, FN_AVB_RX_ER,
6169
6170 FN_VI1_DATA2, FN_AVB_RXD7,
6171
6172 FN_VI1_DATA1, FN_AVB_RXD6,
6173
6174 FN_VI1_DATA0, FN_AVB_RXD5,
6175
6176 FN_VI1_CLK, FN_AVB_RXD4,
6177
6178 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6179
6180 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6181
6182 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6183 FN_RX4_B, FN_SCIFA4_RXD_B,
6184 0, 0, 0,
6185
6186 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6187 FN_TX4_B, FN_SCIFA4_TXD_B,
6188 0, 0, 0,
6189
6190 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6191 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6192
6193 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6194 0, 0, 0,
6195
6196 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6197 FN_I2C1_SDA_D, 0, 0, 0, ))
6198 },
6199 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6200 GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
6201 GROUP(
6202
6203
6204 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6205 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6206 0, 0, 0,
6207
6208 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6209 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6210 0, 0, 0,
6211
6212 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6213
6214 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6215
6216 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6217
6218 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6219
6220 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6221 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6222 0, 0, 0,
6223
6224 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6225 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6226 0, 0, 0,
6227
6228 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6229 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6230 0, 0, 0,
6231
6232 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6233 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6234 0, 0, 0,
6235
6236 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6237
6238 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
6239 },
6240 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6241 GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
6242 1, 1, 1, 3, 2, 2, 3),
6243 GROUP(
6244
6245
6246 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6247 0, 0, 0, 0,
6248
6249 FN_SD1_DATA3, FN_IERX_B,
6250
6251 FN_SD1_DATA2, FN_IECLK_B,
6252
6253 FN_SD1_DATA1, FN_IETX_B,
6254
6255 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6256
6257 FN_SD1_CMD, FN_REMOCON_B,
6258
6259 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6260 FN_SCIFA5_RXD_B, FN_RX3_C,
6261 0, 0,
6262
6263 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6264 FN_SCIFA5_TXD_B, FN_TX3_C,
6265 0, 0,
6266
6267 FN_SD0_DATA3, FN_SSL_B,
6268
6269 FN_SD0_DATA2, FN_IO3_B,
6270
6271 FN_SD0_DATA1, FN_IO2_B,
6272
6273 FN_SD0_DATA0, FN_MISO_IO1_B,
6274
6275 FN_SD0_CMD, FN_MOSI_IO0_B,
6276
6277 FN_SD0_CLK, FN_SPCLK_B,
6278
6279 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6280 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6281 0, 0, 0,
6282
6283 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6284
6285 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6286
6287 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6288 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6289 0, 0, 0, ))
6290 },
6291 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6292 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
6293 1, 1, 2),
6294 GROUP(
6295
6296 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6297 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6298
6299 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6300 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6301
6302 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6303 0, 0, 0,
6304
6305 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6306 0, 0, 0,
6307
6308 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6309 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6310 0, 0,
6311
6312 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6313 FN_VI1_CLK_C, FN_VI1_G0_B,
6314 0, 0,
6315
6316 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6317 0, 0, 0,
6318
6319 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6320 0, 0, 0,
6321
6322 FN_SD2_DATA3, FN_MMC_D3,
6323
6324 FN_SD2_DATA2, FN_MMC_D2,
6325
6326 FN_SD2_DATA1, FN_MMC_D1,
6327
6328 FN_SD2_DATA0, FN_MMC_D0,
6329
6330 FN_SD2_CMD, FN_MMC_CMD,
6331
6332 FN_SD2_CLK, FN_MMC_CLK,
6333
6334 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6335 },
6336 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6337 GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
6338 GROUP(
6339
6340
6341 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6342 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6343 0, 0,
6344
6345 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6346 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6347 0, 0,
6348
6349 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6350 FN_TCLK2, FN_VI1_DATA3_C, 0,
6351
6352 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6353 0, 0, 0,
6354
6355 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6356 FN_TCLK1, FN_VI1_DATA1_C,
6357 0, 0,
6358
6359 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6360 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6361 0, 0,
6362
6363 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6364 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6365 0, 0,
6366
6367 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6368 FN_PWM5_B, FN_SCIFA3_TXD_C,
6369 0, 0, 0,
6370
6371 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6372
6373 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6374
6375 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6376 },
6377 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6378 GROUP(-20, 2, 2, 2, 3, 3),
6379 GROUP(
6380
6381
6382 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6383
6384 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6385
6386 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6387
6388 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6389 FN_GLO_SS_C, FN_VI1_DATA7_C,
6390 0, 0, 0,
6391
6392 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6393 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6394 0, 0, 0, ))
6395 },
6396 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6397 GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2,
6398 2, -2, 1, 2, 2, 2),
6399 GROUP(
6400
6401
6402 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6403
6404 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6405
6406 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6407 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6408
6409 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6410 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6411 0, 0, 0, 0,
6412
6413 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6414
6415 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6416
6417 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6418
6419 FN_SEL_QSP_0, FN_SEL_QSP_1,
6420
6421 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6422
6423 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6424 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6425 0, 0, 0,
6426
6427
6428 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6429
6430
6431 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6432
6433 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6434
6435 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6436
6437 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6438 },
6439 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6440 GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2,
6441 -1, 2, 2, 2, 1, -1, 1),
6442 GROUP(
6443
6444 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6445 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6446 0, 0, 0,
6447
6448
6449 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6450
6451 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6452 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6453 0, 0,
6454
6455 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6456
6457
6458 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6459
6460 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6461
6462
6463 FN_SEL_ADG_0, FN_SEL_ADG_1,
6464
6465 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6466 FN_SEL_FM_3, FN_SEL_FM_4,
6467 0, 0, 0,
6468
6469 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6470
6471
6472 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6473
6474 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6475
6476 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6477
6478 FN_SEL_SIM_0, FN_SEL_SIM_1,
6479
6480
6481 FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
6482 },
6483 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6484 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2,
6485 3, 2, -5),
6486 GROUP(
6487
6488 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6489 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6490
6491 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6492 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6493
6494 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6495
6496 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6497
6498 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6499
6500 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6501
6502 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6503
6504 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6505
6506 FN_SEL_MMC_0, FN_SEL_MMC_1,
6507
6508 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6509
6510
6511 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6512
6513 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6514 FN_SEL_I2C1_4,
6515 0, 0, 0,
6516
6517 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6518 ))
6519 },
6520 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6521 GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1,
6522 1, 1, 2, -6),
6523 GROUP(
6524
6525 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6526 FN_SEL_SOF1_4,
6527 0, 0, 0,
6528
6529 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6530
6531 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6532
6533
6534 FN_SEL_RAD_0, FN_SEL_RAD_1,
6535
6536 FN_SEL_RCN_0, FN_SEL_RCN_1,
6537
6538 FN_SEL_RSP_0, FN_SEL_RSP_1,
6539
6540 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6541 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6542 0, 0, 0,
6543
6544
6545
6546 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6547 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6548 0, 0, 0,
6549
6550
6551 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6552
6553 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6554
6555 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6556 ))
6557 },
6558 { },
6559};
6560
6561static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
6562{
6563 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6564 return -EINVAL;
6565
6566 *pocctrl = 0xe606008c;
6567
6568 return 31 - (pin & 0x1f);
6569}
6570
6571static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6572 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
6573 [ 0] = RCAR_GP_PIN(1, 4),
6574 [ 1] = RCAR_GP_PIN(1, 5),
6575 [ 2] = RCAR_GP_PIN(1, 6),
6576 [ 3] = RCAR_GP_PIN(1, 7),
6577 [ 4] = RCAR_GP_PIN(1, 8),
6578 [ 5] = RCAR_GP_PIN(6, 31),
6579 [ 6] = RCAR_GP_PIN(0, 0),
6580 [ 7] = RCAR_GP_PIN(0, 1),
6581 [ 8] = RCAR_GP_PIN(0, 2),
6582 [ 9] = RCAR_GP_PIN(0, 3),
6583 [10] = RCAR_GP_PIN(0, 4),
6584 [11] = RCAR_GP_PIN(0, 5),
6585 [12] = RCAR_GP_PIN(0, 6),
6586 [13] = RCAR_GP_PIN(0, 7),
6587 [14] = RCAR_GP_PIN(0, 8),
6588 [15] = RCAR_GP_PIN(0, 9),
6589 [16] = RCAR_GP_PIN(0, 10),
6590 [17] = RCAR_GP_PIN(0, 11),
6591 [18] = RCAR_GP_PIN(0, 12),
6592 [19] = RCAR_GP_PIN(0, 13),
6593 [20] = RCAR_GP_PIN(0, 14),
6594 [21] = RCAR_GP_PIN(0, 15),
6595 [22] = RCAR_GP_PIN(0, 16),
6596 [23] = RCAR_GP_PIN(0, 17),
6597 [24] = RCAR_GP_PIN(0, 18),
6598 [25] = RCAR_GP_PIN(0, 19),
6599 [26] = RCAR_GP_PIN(0, 20),
6600 [27] = RCAR_GP_PIN(0, 21),
6601 [28] = RCAR_GP_PIN(0, 22),
6602 [29] = RCAR_GP_PIN(0, 23),
6603 [30] = RCAR_GP_PIN(0, 24),
6604 [31] = RCAR_GP_PIN(0, 25),
6605 } },
6606 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
6607 [ 0] = RCAR_GP_PIN(0, 26),
6608 [ 1] = RCAR_GP_PIN(0, 27),
6609 [ 2] = RCAR_GP_PIN(0, 28),
6610 [ 3] = RCAR_GP_PIN(0, 29),
6611 [ 4] = RCAR_GP_PIN(0, 30),
6612 [ 5] = RCAR_GP_PIN(0, 31),
6613 [ 6] = RCAR_GP_PIN(1, 0),
6614 [ 7] = RCAR_GP_PIN(1, 1),
6615 [ 8] = RCAR_GP_PIN(1, 2),
6616 [ 9] = RCAR_GP_PIN(1, 3),
6617 [10] = PIN_TRST_N,
6618 [11] = PIN_TCK,
6619 [12] = PIN_TMS,
6620 [13] = PIN_TDI,
6621 [14] = RCAR_GP_PIN(1, 11),
6622 [15] = RCAR_GP_PIN(1, 12),
6623 [16] = RCAR_GP_PIN(1, 13),
6624 [17] = RCAR_GP_PIN(1, 14),
6625 [18] = RCAR_GP_PIN(1, 15),
6626 [19] = RCAR_GP_PIN(1, 16),
6627 [20] = RCAR_GP_PIN(1, 17),
6628 [21] = RCAR_GP_PIN(1, 18),
6629 [22] = RCAR_GP_PIN(1, 19),
6630 [23] = RCAR_GP_PIN(1, 20),
6631 [24] = RCAR_GP_PIN(1, 21),
6632 [25] = RCAR_GP_PIN(1, 22),
6633 [26] = RCAR_GP_PIN(1, 23),
6634 [27] = RCAR_GP_PIN(1, 24),
6635 [28] = RCAR_GP_PIN(1, 25),
6636 [29] = RCAR_GP_PIN(5, 31),
6637 [30] = RCAR_GP_PIN(2, 0),
6638 [31] = RCAR_GP_PIN(2, 1),
6639 } },
6640 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
6641 [ 0] = RCAR_GP_PIN(2, 2),
6642 [ 1] = RCAR_GP_PIN(2, 3),
6643 [ 2] = RCAR_GP_PIN(2, 4),
6644 [ 3] = RCAR_GP_PIN(2, 5),
6645 [ 4] = RCAR_GP_PIN(2, 6),
6646 [ 5] = RCAR_GP_PIN(2, 7),
6647 [ 6] = RCAR_GP_PIN(2, 8),
6648 [ 7] = RCAR_GP_PIN(2, 9),
6649 [ 8] = RCAR_GP_PIN(2, 10),
6650 [ 9] = RCAR_GP_PIN(2, 11),
6651 [10] = RCAR_GP_PIN(2, 12),
6652 [11] = RCAR_GP_PIN(2, 13),
6653 [12] = RCAR_GP_PIN(2, 14),
6654 [13] = RCAR_GP_PIN(2, 15),
6655 [14] = RCAR_GP_PIN(2, 16),
6656 [15] = RCAR_GP_PIN(2, 17),
6657 [16] = RCAR_GP_PIN(2, 18),
6658 [17] = RCAR_GP_PIN(2, 19),
6659 [18] = RCAR_GP_PIN(2, 20),
6660 [19] = RCAR_GP_PIN(2, 21),
6661 [20] = RCAR_GP_PIN(2, 22),
6662 [21] = RCAR_GP_PIN(2, 23),
6663 [22] = RCAR_GP_PIN(2, 24),
6664 [23] = RCAR_GP_PIN(2, 25),
6665 [24] = RCAR_GP_PIN(2, 26),
6666 [25] = RCAR_GP_PIN(2, 27),
6667 [26] = RCAR_GP_PIN(2, 28),
6668 [27] = RCAR_GP_PIN(2, 29),
6669 [28] = RCAR_GP_PIN(2, 30),
6670 [29] = RCAR_GP_PIN(2, 31),
6671 [30] = RCAR_GP_PIN(7, 10),
6672 [31] = RCAR_GP_PIN(7, 11),
6673 } },
6674 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
6675 [ 0] = RCAR_GP_PIN(7, 12),
6676 [ 1] = RCAR_GP_PIN(7, 13),
6677 [ 2] = RCAR_GP_PIN(7, 14),
6678 [ 3] = RCAR_GP_PIN(7, 15),
6679 [ 4] = RCAR_GP_PIN(7, 16),
6680 [ 5] = RCAR_GP_PIN(7, 17),
6681 [ 6] = RCAR_GP_PIN(7, 18),
6682 [ 7] = RCAR_GP_PIN(7, 19),
6683 [ 8] = RCAR_GP_PIN(3, 0),
6684 [ 9] = RCAR_GP_PIN(3, 1),
6685 [10] = RCAR_GP_PIN(3, 2),
6686 [11] = RCAR_GP_PIN(3, 3),
6687 [12] = RCAR_GP_PIN(3, 4),
6688 [13] = RCAR_GP_PIN(3, 5),
6689 [14] = RCAR_GP_PIN(3, 6),
6690 [15] = RCAR_GP_PIN(3, 7),
6691 [16] = RCAR_GP_PIN(3, 8),
6692 [17] = RCAR_GP_PIN(3, 9),
6693 [18] = RCAR_GP_PIN(3, 10),
6694 [19] = RCAR_GP_PIN(3, 11),
6695 [20] = RCAR_GP_PIN(3, 12),
6696 [21] = RCAR_GP_PIN(3, 13),
6697 [22] = RCAR_GP_PIN(3, 14),
6698 [23] = RCAR_GP_PIN(3, 15),
6699 [24] = RCAR_GP_PIN(3, 16),
6700 [25] = RCAR_GP_PIN(3, 17),
6701 [26] = RCAR_GP_PIN(3, 18),
6702 [27] = RCAR_GP_PIN(3, 19),
6703 [28] = RCAR_GP_PIN(3, 20),
6704 [29] = RCAR_GP_PIN(3, 21),
6705 [30] = RCAR_GP_PIN(3, 22),
6706 [31] = RCAR_GP_PIN(3, 23),
6707 } },
6708 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6709 [ 0] = RCAR_GP_PIN(3, 24),
6710 [ 1] = RCAR_GP_PIN(3, 25),
6711 [ 2] = RCAR_GP_PIN(3, 26),
6712 [ 3] = RCAR_GP_PIN(3, 27),
6713 [ 4] = RCAR_GP_PIN(3, 28),
6714 [ 5] = RCAR_GP_PIN(3, 29),
6715 [ 6] = RCAR_GP_PIN(3, 30),
6716 [ 7] = RCAR_GP_PIN(3, 31),
6717 [ 8] = RCAR_GP_PIN(4, 0),
6718 [ 9] = RCAR_GP_PIN(4, 1),
6719 [10] = RCAR_GP_PIN(4, 2),
6720 [11] = RCAR_GP_PIN(4, 3),
6721 [12] = RCAR_GP_PIN(4, 4),
6722 [13] = RCAR_GP_PIN(4, 5),
6723 [14] = RCAR_GP_PIN(4, 6),
6724 [15] = RCAR_GP_PIN(4, 7),
6725 [16] = RCAR_GP_PIN(4, 8),
6726 [17] = RCAR_GP_PIN(4, 9),
6727 [18] = RCAR_GP_PIN(4, 10),
6728 [19] = RCAR_GP_PIN(4, 11),
6729 [20] = RCAR_GP_PIN(4, 12),
6730 [21] = RCAR_GP_PIN(4, 13),
6731 [22] = RCAR_GP_PIN(4, 14),
6732 [23] = RCAR_GP_PIN(4, 15),
6733 [24] = RCAR_GP_PIN(4, 16),
6734 [25] = RCAR_GP_PIN(4, 17),
6735 [26] = RCAR_GP_PIN(4, 18),
6736 [27] = RCAR_GP_PIN(4, 19),
6737 [28] = RCAR_GP_PIN(4, 20),
6738 [29] = RCAR_GP_PIN(4, 21),
6739 [30] = RCAR_GP_PIN(4, 22),
6740 [31] = RCAR_GP_PIN(4, 23),
6741 } },
6742 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6743 [ 0] = RCAR_GP_PIN(4, 24),
6744 [ 1] = RCAR_GP_PIN(4, 25),
6745 [ 2] = RCAR_GP_PIN(4, 26),
6746 [ 3] = RCAR_GP_PIN(4, 27),
6747 [ 4] = RCAR_GP_PIN(4, 28),
6748 [ 5] = RCAR_GP_PIN(5, 0),
6749 [ 6] = RCAR_GP_PIN(5, 1),
6750 [ 7] = RCAR_GP_PIN(5, 2),
6751 [ 8] = RCAR_GP_PIN(5, 3),
6752 [ 9] = RCAR_GP_PIN(5, 4),
6753 [10] = RCAR_GP_PIN(5, 5),
6754 [11] = RCAR_GP_PIN(5, 6),
6755 [12] = RCAR_GP_PIN(5, 7),
6756 [13] = RCAR_GP_PIN(5, 8),
6757 [14] = RCAR_GP_PIN(5, 9),
6758 [15] = RCAR_GP_PIN(5, 10),
6759 [16] = RCAR_GP_PIN(5, 11),
6760 [17] = RCAR_GP_PIN(5, 12),
6761 [18] = RCAR_GP_PIN(5, 13),
6762 [19] = RCAR_GP_PIN(5, 14),
6763 [20] = RCAR_GP_PIN(5, 15),
6764 [21] = RCAR_GP_PIN(5, 16),
6765 [22] = RCAR_GP_PIN(5, 17),
6766 [23] = RCAR_GP_PIN(5, 18),
6767 [24] = RCAR_GP_PIN(5, 19),
6768 [25] = RCAR_GP_PIN(5, 20),
6769 [26] = RCAR_GP_PIN(5, 21),
6770 [27] = RCAR_GP_PIN(5, 22),
6771 [28] = RCAR_GP_PIN(5, 23),
6772 [29] = RCAR_GP_PIN(5, 24),
6773 [30] = RCAR_GP_PIN(5, 25),
6774 [31] = RCAR_GP_PIN(5, 26),
6775 } },
6776 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6777 [ 0] = RCAR_GP_PIN(5, 27),
6778 [ 1] = RCAR_GP_PIN(5, 28),
6779 [ 2] = RCAR_GP_PIN(5, 29),
6780 [ 3] = RCAR_GP_PIN(5, 30),
6781 [ 4] = RCAR_GP_PIN(6, 0),
6782 [ 5] = RCAR_GP_PIN(6, 1),
6783 [ 6] = RCAR_GP_PIN(6, 2),
6784 [ 7] = RCAR_GP_PIN(6, 3),
6785 [ 8] = RCAR_GP_PIN(6, 4),
6786 [ 9] = RCAR_GP_PIN(6, 5),
6787 [10] = RCAR_GP_PIN(6, 6),
6788 [11] = RCAR_GP_PIN(6, 7),
6789 [12] = RCAR_GP_PIN(6, 8),
6790 [13] = RCAR_GP_PIN(6, 9),
6791 [14] = RCAR_GP_PIN(6, 10),
6792 [15] = RCAR_GP_PIN(6, 11),
6793 [16] = RCAR_GP_PIN(6, 12),
6794 [17] = RCAR_GP_PIN(6, 13),
6795 [18] = RCAR_GP_PIN(6, 14),
6796 [19] = RCAR_GP_PIN(6, 15),
6797 [20] = RCAR_GP_PIN(6, 16),
6798 [21] = RCAR_GP_PIN(6, 17),
6799 [22] = RCAR_GP_PIN(6, 18),
6800 [23] = RCAR_GP_PIN(6, 19),
6801 [24] = RCAR_GP_PIN(6, 20),
6802 [25] = RCAR_GP_PIN(6, 21),
6803 [26] = RCAR_GP_PIN(6, 22),
6804 [27] = RCAR_GP_PIN(6, 23),
6805 [28] = RCAR_GP_PIN(6, 24),
6806 [29] = RCAR_GP_PIN(6, 25),
6807 [30] = RCAR_GP_PIN(6, 26),
6808 [31] = RCAR_GP_PIN(6, 27),
6809 } },
6810 { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) {
6811
6812 [ 0] = RCAR_GP_PIN(6, 28),
6813 [ 1] = RCAR_GP_PIN(6, 29),
6814 [ 2] = RCAR_GP_PIN(4, 29),
6815 [ 3] = RCAR_GP_PIN(4, 30),
6816 [ 4] = RCAR_GP_PIN(4, 31),
6817 [ 5] = RCAR_GP_PIN(7, 20),
6818 [ 6] = RCAR_GP_PIN(7, 21),
6819 [ 7] = RCAR_GP_PIN(7, 22),
6820 [ 8] = RCAR_GP_PIN(7, 0),
6821 [ 9] = RCAR_GP_PIN(7, 1),
6822 [10] = RCAR_GP_PIN(7, 2),
6823 [11] = RCAR_GP_PIN(7, 3),
6824 [12] = RCAR_GP_PIN(7, 4),
6825 [13] = RCAR_GP_PIN(7, 5),
6826 [14] = RCAR_GP_PIN(7, 6),
6827 [15] = SH_PFC_PIN_NONE,
6828 [16] = SH_PFC_PIN_NONE,
6829 [17] = SH_PFC_PIN_NONE,
6830 [18] = RCAR_GP_PIN(1, 9),
6831 [19] = SH_PFC_PIN_NONE,
6832 [20] = RCAR_GP_PIN(1, 10),
6833 [21] = RCAR_GP_PIN(7, 23),
6834 [22] = RCAR_GP_PIN(7, 24),
6835 [23] = RCAR_GP_PIN(7, 25),
6836 [24] = RCAR_GP_PIN(6, 30),
6837 [25] = PIN_AVS1,
6838 [26] = PIN_AVS2,
6839 [27] = SH_PFC_PIN_NONE,
6840 [28] = SH_PFC_PIN_NONE,
6841 [29] = SH_PFC_PIN_NONE,
6842 [30] = SH_PFC_PIN_NONE,
6843 [31] = SH_PFC_PIN_NONE,
6844 } },
6845 { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) {
6846
6847 [ 0] = SH_PFC_PIN_NONE,
6848 [ 1] = SH_PFC_PIN_NONE,
6849 [ 2] = SH_PFC_PIN_NONE,
6850 [ 3] = SH_PFC_PIN_NONE,
6851 [ 4] = SH_PFC_PIN_NONE,
6852 [ 5] = SH_PFC_PIN_NONE,
6853 [ 6] = SH_PFC_PIN_NONE,
6854 [ 7] = SH_PFC_PIN_NONE,
6855 [ 8] = SH_PFC_PIN_NONE,
6856 [ 9] = SH_PFC_PIN_NONE,
6857 [10] = SH_PFC_PIN_NONE,
6858 [11] = SH_PFC_PIN_NONE,
6859 [12] = SH_PFC_PIN_NONE,
6860 [13] = SH_PFC_PIN_NONE,
6861 [14] = SH_PFC_PIN_NONE,
6862 [15] = SH_PFC_PIN_NONE,
6863 [16] = SH_PFC_PIN_NONE,
6864 [17] = SH_PFC_PIN_NONE,
6865 [18] = SH_PFC_PIN_NONE,
6866 [19] = PIN_ASEBRK_N_ACK,
6867 [20] = SH_PFC_PIN_NONE,
6868 [21] = SH_PFC_PIN_NONE,
6869 [22] = SH_PFC_PIN_NONE,
6870 [23] = SH_PFC_PIN_NONE,
6871 [24] = SH_PFC_PIN_NONE,
6872 [25] = SH_PFC_PIN_NONE,
6873 [26] = SH_PFC_PIN_NONE,
6874 [27] = SH_PFC_PIN_NONE,
6875 [28] = SH_PFC_PIN_NONE,
6876 [29] = SH_PFC_PIN_NONE,
6877 [30] = SH_PFC_PIN_NONE,
6878 [31] = SH_PFC_PIN_NONE,
6879 } },
6880 { },
6881};
6882
6883static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
6884 .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6885 .get_bias = rcar_pinmux_get_bias,
6886 .set_bias = rcar_pinmux_set_bias,
6887};
6888
6889#ifdef CONFIG_PINCTRL_PFC_R8A7743
6890const struct sh_pfc_soc_info r8a7743_pinmux_info = {
6891 .name = "r8a77430_pfc",
6892 .ops = &r8a7791_pfc_ops,
6893 .unlock_reg = 0xe6060000,
6894
6895 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6896
6897 .pins = pinmux_pins,
6898 .nr_pins = ARRAY_SIZE(pinmux_pins),
6899 .groups = pinmux_groups.common,
6900 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6901 .functions = pinmux_functions.common,
6902 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6903
6904 .cfg_regs = pinmux_config_regs,
6905 .bias_regs = pinmux_bias_regs,
6906
6907 .pinmux_data = pinmux_data,
6908 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6909};
6910#endif
6911
6912#ifdef CONFIG_PINCTRL_PFC_R8A7744
6913const struct sh_pfc_soc_info r8a7744_pinmux_info = {
6914 .name = "r8a77440_pfc",
6915 .ops = &r8a7791_pfc_ops,
6916 .unlock_reg = 0xe6060000,
6917
6918 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6919
6920 .pins = pinmux_pins,
6921 .nr_pins = ARRAY_SIZE(pinmux_pins),
6922 .groups = pinmux_groups.common,
6923 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6924 .functions = pinmux_functions.common,
6925 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6926
6927 .cfg_regs = pinmux_config_regs,
6928 .bias_regs = pinmux_bias_regs,
6929
6930 .pinmux_data = pinmux_data,
6931 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6932};
6933#endif
6934
6935#ifdef CONFIG_PINCTRL_PFC_R8A7791
6936const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6937 .name = "r8a77910_pfc",
6938 .ops = &r8a7791_pfc_ops,
6939 .unlock_reg = 0xe6060000,
6940
6941 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6942
6943 .pins = pinmux_pins,
6944 .nr_pins = ARRAY_SIZE(pinmux_pins),
6945 .groups = pinmux_groups.common,
6946 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6947 ARRAY_SIZE(pinmux_groups.automotive),
6948 .functions = pinmux_functions.common,
6949 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6950 ARRAY_SIZE(pinmux_functions.automotive),
6951
6952 .cfg_regs = pinmux_config_regs,
6953 .bias_regs = pinmux_bias_regs,
6954
6955 .pinmux_data = pinmux_data,
6956 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6957};
6958#endif
6959
6960#ifdef CONFIG_PINCTRL_PFC_R8A7793
6961const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6962 .name = "r8a77930_pfc",
6963 .ops = &r8a7791_pfc_ops,
6964 .unlock_reg = 0xe6060000,
6965
6966 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6967
6968 .pins = pinmux_pins,
6969 .nr_pins = ARRAY_SIZE(pinmux_pins),
6970 .groups = pinmux_groups.common,
6971 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6972 ARRAY_SIZE(pinmux_groups.automotive),
6973 .functions = pinmux_functions.common,
6974 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6975 ARRAY_SIZE(pinmux_functions.automotive),
6976
6977 .cfg_regs = pinmux_config_regs,
6978 .bias_regs = pinmux_bias_regs,
6979
6980 .pinmux_data = pinmux_data,
6981 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6982};
6983#endif
6984
