LXR uboot/drivers/ram/stm32mp1/stm32mp1

   1/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2/*
   3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4 */
   5
   6#ifndef _RAM_STM32MP1_DDR_H
   7#define _RAM_STM32MP1_DDR_H
   8
   9enum stm32mp1_ddr_interact_step {
  10        STEP_DDR_RESET,
  11        STEP_CTL_INIT,
  12        STEP_PHY_INIT,
  13        STEP_DDR_READY,
  14        STEP_RUN,
  15};
  16
  17/* DDR CTL and DDR PHY REGISTERS */
  18struct stm32mp1_ddrctl;
  19struct stm32mp1_ddrphy;
  20
  21/**
  22 * struct ddr_info
  23 *
  24 * @dev: pointer for the device
  25 * @info: UCLASS RAM information
  26 * @ctl: DDR controleur base address
  27 * @clk: DDR clock
  28 * @phy: DDR PHY base address
  29 * @rcc: rcc base address
  30 */
  31struct ddr_info {
  32        struct udevice *dev;
  33        struct ram_info info;
  34        struct clk clk;
  35        struct stm32mp1_ddrctl *ctl;
  36        struct stm32mp1_ddrphy *phy;
  37        u32 rcc;
  38};
  39
  40struct stm32mp1_ddrctrl_reg {
  41        u32 mstr;
  42        u32 mrctrl0;
  43        u32 mrctrl1;
  44        u32 derateen;
  45        u32 derateint;
  46        u32 pwrctl;
  47        u32 pwrtmg;
  48        u32 hwlpctl;
  49        u32 rfshctl0;
  50        u32 rfshctl3;
  51        u32 crcparctl0;
  52        u32 zqctl0;
  53        u32 dfitmg0;
  54        u32 dfitmg1;
  55        u32 dfilpcfg0;
  56        u32 dfiupd0;
  57        u32 dfiupd1;
  58        u32 dfiupd2;
  59        u32 dfiphymstr;
  60        u32 odtmap;
  61        u32 dbg0;
  62        u32 dbg1;
  63        u32 dbgcmd;
  64        u32 poisoncfg;
  65        u32 pccfg;
  66
  67};
  68
  69struct stm32mp1_ddrctrl_timing {
  70        u32 rfshtmg;
  71        u32 dramtmg0;
  72        u32 dramtmg1;
  73        u32 dramtmg2;
  74        u32 dramtmg3;
  75        u32 dramtmg4;
  76        u32 dramtmg5;
  77        u32 dramtmg6;
  78        u32 dramtmg7;
  79        u32 dramtmg8;
  80        u32 dramtmg14;
  81        u32 odtcfg;
  82};
  83
  84struct stm32mp1_ddrctrl_map {
  85        u32 addrmap1;
  86        u32 addrmap2;
  87        u32 addrmap3;
  88        u32 addrmap4;
  89        u32 addrmap5;
  90        u32 addrmap6;
  91        u32 addrmap9;
  92        u32 addrmap10;
  93        u32 addrmap11;
  94};
  95
  96struct stm32mp1_ddrctrl_perf {
  97        u32 sched;
  98        u32 sched1;
  99        u32 perfhpr1;
 100        u32 perflpr1;
 101        u32 perfwr1;
 102        u32 pcfgr_0;
 103        u32 pcfgw_0;
 104        u32 pcfgqos0_0;
 105        u32 pcfgqos1_0;
 106        u32 pcfgwqos0_0;
 107        u32 pcfgwqos1_0;
 108        u32 pcfgr_1;
 109        u32 pcfgw_1;
 110        u32 pcfgqos0_1;
 111        u32 pcfgqos1_1;
 112        u32 pcfgwqos0_1;
 113        u32 pcfgwqos1_1;
 114};
 115
 116struct stm32mp1_ddrphy_reg {
 117        u32 pgcr;
 118        u32 aciocr;
 119        u32 dxccr;
 120        u32 dsgcr;
 121        u32 dcr;
 122        u32 odtcr;
 123        u32 zq0cr1;
 124        u32 dx0gcr;
 125        u32 dx1gcr;
 126        u32 dx2gcr;
 127        u32 dx3gcr;
 128};
 129
 130struct stm32mp1_ddrphy_timing {
 131        u32 ptr0;
 132        u32 ptr1;
 133        u32 ptr2;
 134        u32 dtpr0;
 135        u32 dtpr1;
 136        u32 dtpr2;
 137        u32 mr0;
 138        u32 mr1;
 139        u32 mr2;
 140        u32 mr3;
 141};
 142
 143struct stm32mp1_ddr_info {
 144        const char *name;
 145        u32 speed; /* in kHZ */
 146        u32 size;  /* memory size in byte = col * row * width */
 147};
 148
 149struct stm32mp1_ddr_config {
 150        struct stm32mp1_ddr_info info;
 151        struct stm32mp1_ddrctrl_reg c_reg;
 152        struct stm32mp1_ddrctrl_timing c_timing;
 153        struct stm32mp1_ddrctrl_map c_map;
 154        struct stm32mp1_ddrctrl_perf c_perf;
 155        struct stm32mp1_ddrphy_reg p_reg;
 156        struct stm32mp1_ddrphy_timing p_timing;
 157};
 158
 159int stm32mp1_ddr_clk_enable(struct ddr_info *priv, u32 mem_speed);
 160
 161void stm32mp1_ddr_init(
 162        struct ddr_info *priv,
 163        const struct stm32mp1_ddr_config *config);
 164
 165int stm32mp1_dump_reg(const struct ddr_info *priv,
 166                      const char *name);
 167
 168void stm32mp1_edit_reg(const struct ddr_info *priv,
 169                       char *name,
 170                       char *string);
 171
 172int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
 173                        const char *name);
 174
 175void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
 176                         char *name,
 177                         char *string);
 178
 179bool stm32mp1_ddr_interactive(
 180        void *priv,
 181        enum stm32mp1_ddr_interact_step step,
 182        const struct stm32mp1_ddr_config *config);
 183
 184#endif
 185