LXR uboot/drivers/reset/sti-reset.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
   5 */
   6
   7#include <common.h>
   8#include <errno.h>
   9#include <log.h>
  10#include <malloc.h>
  11#include <wait_bit.h>
  12#include <dm.h>
  13#include <reset-uclass.h>
  14#include <regmap.h>
  15#include <syscon.h>
  16#include <asm/global_data.h>
  17#include <dt-bindings/reset/stih407-resets.h>
  18#include <linux/bitops.h>
  19
  20DECLARE_GLOBAL_DATA_PTR;
  21
  22struct sti_reset {
  23        const struct syscfg_reset_controller_data *data;
  24};
  25
  26/**
  27 * Reset channel description for a system configuration register based
  28 * reset controller.
  29 *
  30 * @compatible: Compatible string of the syscon containing this
  31 *              channel's control and ack (status) bits.
  32 * @reset_offset: Reset register offset in sysconf bank.
  33 * @reset_bit: Bit number in reset register.
  34 * @ack_offset: Ack reset register offset in syscon bank.
  35 * @ack_bit: Bit number in Ack reset register.
  36 * @deassert_cnt: incremented when reset is deasserted, reset can only be
  37 *                asserted when equal to 0
  38 */
  39
  40struct syscfg_reset_channel_data {
  41        const char *compatible;
  42        int reset_offset;
  43        int reset_bit;
  44        int ack_offset;
  45        int ack_bit;
  46        int deassert_cnt;
  47};
  48
  49/**
  50 * Description of a system configuration register based reset controller.
  51 *
  52 * @wait_for_ack: The controller will wait for reset assert and de-assert to
  53 *                be "ack'd" in a channel's ack field.
  54 * @active_low: Are the resets in this controller active low, i.e. clearing
  55 *              the reset bit puts the hardware into reset.
  56 * @nr_channels: The number of reset channels in this controller.
  57 * @channels: An array of reset channel descriptions.
  58 */
  59struct syscfg_reset_controller_data {
  60        bool wait_for_ack;
  61        bool active_low;
  62        int nr_channels;
  63        struct syscfg_reset_channel_data *channels;
  64};
  65
  66/* STiH407 Peripheral powerdown definitions. */
  67static const char stih407_core[] = "st,stih407-core-syscfg";
  68static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
  69static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
  70
  71#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab)          \
  72        { .compatible   = _c,                           \
  73          .reset_offset = _rr,                          \
  74          .reset_bit    = _rb,                          \
  75          .ack_offset   = _ar,                          \
  76          .ack_bit      = _ab,                          }
  77
  78#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb)             \
  79        { .compatible   = _c,                           \
  80          .reset_offset = _rr,                          \
  81          .reset_bit    = _rb,                          }
  82
  83#define STIH407_SRST_CORE(_reg, _bit) \
  84        _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
  85
  86#define STIH407_SRST_SBC(_reg, _bit) \
  87        _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
  88
  89#define STIH407_SRST_LPM(_reg, _bit) \
  90        _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
  91
  92#define STIH407_PDN_0(_bit) \
  93        _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
  94#define STIH407_PDN_1(_bit) \
  95        _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
  96#define STIH407_PDN_ETH(_bit, _stat) \
  97        _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
  98
  99/* Powerdown requests control 0 */
 100#define SYSCFG_5000     0x0
 101#define SYSSTAT_5500    0x7d0
 102/* Powerdown requests control 1 (High Speed Links) */
 103#define SYSCFG_5001     0x4
 104#define SYSSTAT_5501    0x7d4
 105
 106/* Ethernet powerdown/status/reset */
 107#define SYSCFG_4032     0x80
 108#define SYSSTAT_4520    0x820
 109#define SYSCFG_4002     0x8
 110
 111static struct syscfg_reset_channel_data stih407_powerdowns[] = {
 112        [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
 113        [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
 114        [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
 115        [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
 116        [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
 117        [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
 118        [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
 119        [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
 120        [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
 121        [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
 122};
 123
 124/* Reset Generator control 0/1 */
 125#define SYSCFG_5128     0x200
 126#define SYSCFG_5131     0x20c
 127#define SYSCFG_5132     0x210
 128
 129#define LPM_SYSCFG_1    0x4     /* Softreset IRB & SBC UART */
 130
 131static struct syscfg_reset_channel_data stih407_softresets[] = {
 132        [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
 133        [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
 134        [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
 135        [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
 136        [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
 137        [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
 138        [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
 139        [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
 140        [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
 141        [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
 142        [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
 143        [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
 144        [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
 145        [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
 146        [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
 147        [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
 148        [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
 149        [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
 150        [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
 151        [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
 152        [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
 153        [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
 154        [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
 155        [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
 156        [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
 157        [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
 158        [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
 159        [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
 160        [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
 161        [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
 162        [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
 163        [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
 164        [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
 165};
 166
 167/* PicoPHY reset/control */
 168#define SYSCFG_5061     0x0f4
 169
 170static struct syscfg_reset_channel_data stih407_picophyresets[] = {
 171        [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
 172        [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
 173        [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
 174};
 175
 176static const struct
 177syscfg_reset_controller_data stih407_powerdown_controller = {
 178        .wait_for_ack = true,
 179        .nr_channels = ARRAY_SIZE(stih407_powerdowns),
 180        .channels = stih407_powerdowns,
 181};
 182
 183static const struct
 184syscfg_reset_controller_data stih407_softreset_controller = {
 185        .wait_for_ack = false,
 186        .active_low = true,
 187        .nr_channels = ARRAY_SIZE(stih407_softresets),
 188        .channels = stih407_softresets,
 189};
 190
 191static const struct
 192syscfg_reset_controller_data stih407_picophyreset_controller = {
 193        .wait_for_ack = false,
 194        .nr_channels = ARRAY_SIZE(stih407_picophyresets),
 195        .channels = stih407_picophyresets,
 196};
 197
 198phys_addr_t sti_reset_get_regmap(const char *compatible)
 199{
 200        struct udevice *syscon;
 201        struct regmap *regmap;
 202        int node, ret;
 203
 204        node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 205                                             compatible);
 206        if (node < 0) {
 207                pr_err("unable to find %s node\n", compatible);
 208                return node;
 209        }
 210
 211        ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
 212        if (ret) {
 213                pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
 214                      __func__, ret);
 215                return ret;
 216        }
 217
 218        regmap = syscon_get_regmap(syscon);
 219        if (!regmap) {
 220                pr_err("unable to get regmap for %s\n", syscon->name);
 221                return -ENODEV;
 222        }
 223
 224        return regmap->ranges[0].start;
 225}
 226
 227static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
 228{
 229        struct udevice *dev = reset_ctl->dev;
 230        struct syscfg_reset_controller_data *reset_desc =
 231                (struct syscfg_reset_controller_data *)(dev->driver_data);
 232        struct syscfg_reset_channel_data *ch;
 233        phys_addr_t base;
 234        u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
 235        void __iomem *reg;
 236
 237        /* check if reset id is inside available range */
 238        if (reset_ctl->id >= reset_desc->nr_channels)
 239                return -EINVAL;
 240
 241        /* get reset sysconf register base address */
 242        base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
 243
 244        ch = &reset_desc->channels[reset_ctl->id];
 245
 246        /* check the deassert counter to assert reset when it reaches 0 */
 247        if (!assert) {
 248                ch->deassert_cnt++;
 249                if (ch->deassert_cnt > 1)
 250                        return 0;
 251        } else {
 252                if (ch->deassert_cnt > 0) {
 253                        ch->deassert_cnt--;
 254                        if (ch->deassert_cnt > 0)
 255                                return 0;
 256                } else
 257                        pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
 258                              reset_ctl, reset_ctl->dev, reset_ctl->id);
 259        }
 260
 261        reg = (void __iomem *)base + ch->reset_offset;
 262
 263        if (ctrl_val)
 264                generic_set_bit(ch->reset_bit, reg);
 265        else
 266                generic_clear_bit(ch->reset_bit, reg);
 267
 268        if (!reset_desc->wait_for_ack)
 269                return 0;
 270
 271        reg = (void __iomem *)base + ch->ack_offset;
 272        if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
 273                              1000, false)) {
 274                pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
 275                      reset_ctl, reset_ctl->dev, reset_ctl->id);
 276
 277                return -ETIMEDOUT;
 278        }
 279
 280        return 0;
 281}
 282
 283static int sti_reset_assert(struct reset_ctl *reset_ctl)
 284{
 285        return sti_reset_program_hw(reset_ctl, true);
 286}
 287
 288static int sti_reset_deassert(struct reset_ctl *reset_ctl)
 289{
 290        return sti_reset_program_hw(reset_ctl, false);
 291}
 292
 293struct reset_ops sti_reset_ops = {
 294        .rst_assert = sti_reset_assert,
 295        .rst_deassert = sti_reset_deassert,
 296};
 297
 298static int sti_reset_probe(struct udevice *dev)
 299{
 300        struct sti_reset *priv = dev_get_priv(dev);
 301
 302        priv->data = (void *)dev_get_driver_data(dev);
 303
 304        return 0;
 305}
 306
 307static const struct udevice_id sti_reset_ids[] = {
 308        {
 309                .compatible = "st,stih407-picophyreset",
 310                .data = (ulong)&stih407_picophyreset_controller,
 311        },
 312        {
 313                .compatible = "st,stih407-powerdown",
 314                .data = (ulong)&stih407_powerdown_controller,
 315        },
 316        {
 317                .compatible = "st,stih407-softreset",
 318                .data = (ulong)&stih407_softreset_controller,
 319        },
 320        { }
 321};
 322
 323U_BOOT_DRIVER(sti_reset) = {
 324        .name = "sti_reset",
 325        .id = UCLASS_RESET,
 326        .of_match = sti_reset_ids,
 327        .probe = sti_reset_probe,
 328        .priv_auto      = sizeof(struct sti_reset),
 329        .ops = &sti_reset_ops,
 330};
 331