1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2012 Samsung Electronics 4 */ 5 6#ifndef __WM8994_REGISTERS_H__ 7#define __WM8994_REGISTERS_H__ 8 9/* 10 * Register values. 11 */ 12#define WM8994_SOFTWARE_RESET 0x00 13#define WM8994_POWER_MANAGEMENT_1 0x01 14#define WM8994_POWER_MANAGEMENT_2 0x02 15#define WM8994_POWER_MANAGEMENT_4 0x04 16#define WM8994_POWER_MANAGEMENT_5 0x05 17#define WM8994_LEFT_OUTPUT_VOLUME 0x1C 18#define WM8994_RIGHT_OUTPUT_VOLUME 0x1D 19#define WM8994_OUTPUT_MIXER_1 0x2D 20#define WM8994_OUTPUT_MIXER_2 0x2E 21#define WM8994_CHARGE_PUMP_1 0x4C 22#define WM8994_DC_SERVO_1 0x54 23#define WM8994_ANALOGUE_HP_1 0x60 24#define WM8994_CHIP_REVISION 0x100 25#define WM8994_AIF1_CLOCKING_1 0x200 26#define WM8994_AIF1_CLOCKING_2 0x201 27#define WM8994_AIF2_CLOCKING_1 0x204 28#define WM8994_CLOCKING_1 0x208 29#define WM8994_CLOCKING_2 0x209 30#define WM8994_AIF1_RATE 0x210 31#define WM8994_AIF2_RATE 0x211 32#define WM8994_RATE_STATUS 0x212 33#define WM8994_AIF1_CONTROL_1 0x300 34#define WM8994_AIF1_CONTROL_2 0x301 35#define WM8994_AIF1_MASTER_SLAVE 0x302 36#define WM8994_AIF1_BCLK 0x303 37#define WM8994_AIF2_CONTROL_1 0x310 38#define WM8994_AIF2_CONTROL_2 0x311 39#define WM8994_AIF2_MASTER_SLAVE 0x312 40#define WM8994_AIF2_BCLK 0x313 41#define WM8994_AIF1_DAC_FILTERS_1 0x420 42#define WM8994_AIF2_DAC_LEFT_VOLUME 0x502 43#define WM8994_AIF2_DAC_RIGHT_VOLUME 0x503 44#define WM8994_AIF2_DAC_FILTERS_1 0x520 45#define WM8994_DAC1_LEFT_MIXER_ROUTING 0x601 46#define WM8994_DAC1_RIGHT_MIXER_ROUTING 0x602 47#define WM8994_DAC1_LEFT_VOLUME 0x610 48#define WM8994_DAC1_RIGHT_VOLUME 0x611 49#define WM8994_GPIO_1 0x700 50#define WM8994_GPIO_3 0x702 51#define WM8994_GPIO_4 0x703 52#define WM8994_GPIO_5 0x704 53 54/* 55 * Field Definitions. 56 */ 57 58/* 59 * R0 (0x00) - Software Reset 60 */ 61/* SW_RESET */ 62#define WM8994_SW_RESET 1 63/* 64 * R1 (0x01) - Power Management (1) 65 */ 66/* HPOUT1L_ENA */ 67#define WM8994_HPOUT1L_ENA 0x0200 68/* HPOUT1L_ENA */ 69#define WM8994_HPOUT1L_ENA_MASK 0x0200 70/* HPOUT1R_ENA */ 71#define WM8994_HPOUT1R_ENA 0x0100 72/* HPOUT1R_ENA */ 73#define WM8994_HPOUT1R_ENA_MASK 0x0100 74/* VMID_SEL - [2:1] */ 75#define WM8994_VMID_SEL_MASK 0x0006 76/* BIAS_ENA */ 77#define WM8994_BIAS_ENA 0x0001 78/* BIAS_ENA */ 79#define WM8994_BIAS_ENA_MASK 0x0001 80 81/* 82 * R2 (0x02) - Power Management (2) 83 */ 84/* OPCLK_ENA */ 85#define WM8994_OPCLK_ENA 0x0800 86 87#define WM8994_TSHUT_ENA 0x4000 88#define WM8994_MIXINL_ENA 0x0200 89#define WM8994_MIXINR_ENA 0x0100 90#define WM8994_IN2L_ENA 0x0080 91#define WM8994_IN2R_ENA 0x0020 92 93/* 94 * R5 (0x04) - Power Management (4) 95 */ 96#define WM8994_ADCL_ENA 0x0001 97#define WM8994_ADCR_ENA 0x0002 98#define WM8994_AIF1ADC1R_ENA 0x0100 99#define WM8994_AIF1ADC1L_ENA 0x0200 100 101/* 102 * R5 (0x05) - Power Management (5) 103 */ 104/* AIF2DACL_ENA */ 105#define WM8994_AIF2DACL_ENA 0x2000 106#define WM8994_AIF2DACL_ENA_MASK 0x2000 107/* AIF2DACR_ENA */ 108#define WM8994_AIF2DACR_ENA 0x1000 109#define WM8994_AIF2DACR_ENA_MASK 0x1000 110/* AIF1DACL_ENA */ 111#define WM8994_AIF1DACL_ENA 0x0200 112#define WM8994_AIF1DACL_ENA_MASK 0x0200 113/* AIF1DACR_ENA */ 114#define WM8994_AIF1DACR_ENA 0x0100 115#define WM8994_AIF1DACR_ENA_MASK 0x0100 116/* DAC1L_ENA */ 117#define WM8994_DAC1L_ENA 0x0002 118#define WM8994_DAC1L_ENA_MASK 0x0002 119/* DAC1R_ENA */ 120#define WM8994_DAC1R_ENA 0x0001 121#define WM8994_DAC1R_ENA_MASK 0x0001 122 123/* 124 * R45 (0x2D) - Output Mixer (1) 125 */ 126/* DAC1L_TO_HPOUT1L */ 127#define WM8994_DAC1L_TO_HPOUT1L 0x0100 128#define WM8994_DAC1L_TO_HPOUT1L_MASK 0x0100 129 130/* 131 * R46 (0x2E) - Output Mixer (2) 132 */ 133/* DAC1R_TO_HPOUT1R */ 134#define WM8994_DAC1R_TO_HPOUT1R 0x0100 135#define WM8994_DAC1R_TO_HPOUT1R_MASK 0x0100 136 137/* 138 * R76 (0x4C) - Charge Pump (1) 139 */ 140/* CP_ENA */ 141#define WM8994_CP_ENA 0x8000 142#define WM8994_CP_ENA_MASK 0x8000 143/* 144 * R84 (0x54) - DC Servo (1) 145 */ 146/* DCS_ENA_CHAN_1 */ 147#define WM8994_DCS_ENA_CHAN_1 0x0002 148#define WM8994_DCS_ENA_CHAN_1_MASK 0x0002 149/* DCS_ENA_CHAN_0 */ 150#define WM8994_DCS_ENA_CHAN_0 0x0001 151#define WM8994_DCS_ENA_CHAN_0_MASK 0x0001 152 153/* 154 * R96 (0x60) - Analogue HP (1) 155 */ 156/* HPOUT1L_RMV_SHORT */ 157#define WM8994_HPOUT1L_RMV_SHORT 0x0080 158#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 159/* HPOUT1L_OUTP */ 160#define WM8994_HPOUT1L_OUTP 0x0040 161#define WM8994_HPOUT1L_OUTP_MASK 0x0040 162/* HPOUT1L_DLY */ 163#define WM8994_HPOUT1L_DLY 0x0020 164#define WM8994_HPOUT1L_DLY_MASK 0x0020 165/* HPOUT1R_RMV_SHORT */ 166#define WM8994_HPOUT1R_RMV_SHORT 0x0008 167#define WM8994_HPOUT1R_RMV_SHORT_MASK 0x0008 168/* HPOUT1R_OUTP */ 169#define WM8994_HPOUT1R_OUTP 0x0004 170#define WM8994_HPOUT1R_OUTP_MASK 0x0004 171/* HPOUT1R_DLY */ 172#define WM8994_HPOUT1R_DLY 0x0002 173#define WM8994_HPOUT1R_DLY_MASK 0x0002 174 175/* 176 * R512 (0x200) - AIF1 Clocking (1) 177 */ 178/* AIF1CLK_SRC - [4:3] */ 179#define WM8994_AIF1CLK_SRC_MASK 0x0018 180/* AIF1CLK_DIV */ 181#define WM8994_AIF1CLK_DIV 0x0002 182/* AIF1CLK_ENA */ 183#define WM8994_AIF1CLK_ENA 0x0001 184#define WM8994_AIF1CLK_ENA_MASK 0x0001 185 186/* 187 * R517 (0x205) - AIF2 Clocking (2) 188 */ 189/* AIF2DAC_DIV - [5:3] */ 190#define WM8994_AIF2DAC_DIV_MASK 0x0038 191 192/* 193 * R520 (0x208) - Clocking (1) 194 */ 195/* AIF1DSPCLK_ENA */ 196#define WM8994_AIF1DSPCLK_ENA 0x0008 197#define WM8994_AIF1DSPCLK_ENA_MASK 0x0008 198/* AIF2DSPCLK_ENA */ 199#define WM8994_AIF2DSPCLK_ENA 0x0004 200#define WM8994_AIF2DSPCLK_ENA_MASK 0x0004 201/* SYSDSPCLK_ENA */ 202#define WM8994_SYSDSPCLK_ENA 0x0002 203#define WM8994_SYSDSPCLK_ENA_MASK 0x0002 204/* SYSCLK_SRC */ 205#define WM8994_SYSCLK_SRC 0x0001 206 207/* 208 * R521 (0x209) - Clocking (2) 209 */ 210/* OPCLK_DIV - [2:0] */ 211#define WM8994_OPCLK_DIV_MASK 0x0007 212 213/* 214 * R528 (0x210) - AIF1 Rate 215 */ 216/* AIF1_SR - [7:4] */ 217#define WM8994_AIF1_SR_MASK 0x00F0 218#define WM8994_AIF1_SR_SHIFT 4 219/* AIF1CLK_RATE - [3:0] */ 220#define WM8994_AIF1CLK_RATE_MASK 0x000F 221 222/* 223 * R768 (0x300) - AIF1 Control (1) 224 */ 225/* AIF1_BCLK_INV */ 226#define WM8994_AIF1_BCLK_INV 0x0100 227/* AIF1_LRCLK_INV */ 228#define WM8994_AIF1_LRCLK_INV 0x0080 229#define WM8994_AIF1_LRCLK_INV_MASK 0x0080 230/* AIF1_WL - [6:5] */ 231#define WM8994_AIF1_WL_MASK 0x0060 232/* AIF1_FMT - [4:3] */ 233#define WM8994_AIF1_FMT_MASK 0x0018 234 235/* 236 * R769 (0x301) - AIF1 Control (2) 237 */ 238/* AIF1_MONO */ 239#define WM8994_AIF1_MONO 0x0100 240 241/* 242 * R770 (0x302) - AIF1 Master/Slave 243 */ 244/* AIF1_MSTR */ 245#define WM8994_AIF1_MSTR 0x4000 246#define WM8994_AIF1_MSTR_MASK 0x4000 247 248/* 249 * R771 (0x303) - AIF1 BCLK 250 */ 251/* AIF1_BCLK_DIV - [8:4] */ 252#define WM8994_AIF1_BCLK_DIV_MASK 0x01F0 253#define WM8994_AIF1_BCLK_DIV_SHIFT 4 254 255/* 256 * R1282 (0x502) - AIF2 DAC Left Volume 257 */ 258/* AIF2DAC_VU */ 259#define WM8994_AIF2DAC_VU 0x0100 260#define WM8994_AIF2DAC_VU_MASK 0x0100 261/* AIF2DACL_VOL - [7:0] */ 262#define WM8994_AIF2DACL_VOL_MASK 0x00FF 263 264/* 265 * R1283 (0x503) - AIF2 DAC Right Volume 266 */ 267/* AIF2DACR_VOL - [7:0] */ 268#define WM8994_AIF2DACR_VOL_MASK 0x00FF 269 270/* 271 * R1312 (0x520) - AIF2 DAC Filters (1) 272 */ 273/* AIF2DAC_MUTE */ 274#define WM8994_AIF2DAC_MUTE_MASK 0x0200 275 276/* 277 * R1537 (0x601) - DAC1 Left Mixer Routing 278 */ 279/* AIF2DACL_TO_DAC1L */ 280#define WM8994_AIF2DACL_TO_DAC1L 0x0004 281#define WM8994_AIF2DACL_TO_DAC1L_MASK 0x0004 282/* AIF1DAC1L_TO_DAC1L */ 283#define WM8994_AIF1DAC1L_TO_DAC1L 0x0001 284 285/* 286 * R1538 (0x602) - DAC1 Right Mixer Routing 287 */ 288/* AIF2DACR_TO_DAC1R */ 289#define WM8994_AIF2DACR_TO_DAC1R 0x0004 290#define WM8994_AIF2DACR_TO_DAC1R_MASK 0x0004 291/* AIF1DAC1R_TO_DAC1R */ 292#define WM8994_AIF1DAC1R_TO_DAC1R 0x0001 293 294/* 295 * R1552 (0x610) - DAC1 Left Volume 296 */ 297/* DAC1L_MUTE */ 298#define WM8994_DAC1L_MUTE_MASK 0x0200 299/* DAC1_VU */ 300#define WM8994_DAC1_VU 0x0100 301#define WM8994_DAC1_VU_MASK 0x0100 302/* DAC1L_VOL - [7:0] */ 303#define WM8994_DAC1L_VOL_MASK 0x00FF 304 305/* 306 * R1553 (0x611) - DAC1 Right Volume 307 */ 308/* DAC1R_MUTE */ 309#define WM8994_DAC1R_MUTE_MASK 0x0200 310/* DAC1R_VOL - [7:0] */ 311#define WM8994_DAC1R_VOL_MASK 0x00FF 312 313/* 314 * GPIO 315 */ 316/* OUTPUT PIN */ 317#define WM8994_GPIO_DIR_OUTPUT 0x8000 318/* GPIO PIN MASK */ 319#define WM8994_GPIO_DIR_MASK 0xFFE0 320/* I2S CLK */ 321#define WM8994_GPIO_FUNCTION_I2S_CLK 0x0001 322#define WM8994_GPIO_INPUT_DEBOUNCE 0x0100 323/* GPn FN */ 324#define WM8994_GPIO_FUNCTION_MASK 0x001F 325#endif 326