LXR uboot/drivers/spi/stm32

   1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   4 *
   5 * Driver for STMicroelectronics Serial peripheral interface (SPI)
   6 */
   7
   8#define LOG_CATEGORY UCLASS_SPI
   9
  10#include <common.h>
  11#include <clk.h>
  12#include <dm.h>
  13#include <errno.h>
  14#include <log.h>
  15#include <malloc.h>
  16#include <reset.h>
  17#include <spi.h>
  18#include <dm/device_compat.h>
  19#include <linux/bitops.h>
  20#include <linux/delay.h>
  21
  22#include <asm/io.h>
  23#include <asm/gpio.h>
  24#include <linux/bitfield.h>
  25#include <linux/iopoll.h>
  26
  27/* STM32 SPI registers */
  28#define STM32_SPI_CR1           0x00
  29#define STM32_SPI_CR2           0x04
  30#define STM32_SPI_CFG1          0x08
  31#define STM32_SPI_CFG2          0x0C
  32#define STM32_SPI_SR            0x14
  33#define STM32_SPI_IFCR          0x18
  34#define STM32_SPI_TXDR          0x20
  35#define STM32_SPI_RXDR          0x30
  36#define STM32_SPI_I2SCFGR       0x50
  37
  38/* STM32_SPI_CR1 bit fields */
  39#define SPI_CR1_SPE             BIT(0)
  40#define SPI_CR1_MASRX           BIT(8)
  41#define SPI_CR1_CSTART          BIT(9)
  42#define SPI_CR1_CSUSP           BIT(10)
  43#define SPI_CR1_HDDIR           BIT(11)
  44#define SPI_CR1_SSI             BIT(12)
  45
  46/* STM32_SPI_CR2 bit fields */
  47#define SPI_CR2_TSIZE           GENMASK(15, 0)
  48
  49/* STM32_SPI_CFG1 bit fields */
  50#define SPI_CFG1_DSIZE          GENMASK(4, 0)
  51#define SPI_CFG1_DSIZE_MIN      3
  52#define SPI_CFG1_FTHLV_SHIFT    5
  53#define SPI_CFG1_FTHLV          GENMASK(8, 5)
  54#define SPI_CFG1_MBR_SHIFT      28
  55#define SPI_CFG1_MBR            GENMASK(30, 28)
  56#define SPI_CFG1_MBR_MIN        0
  57#define SPI_CFG1_MBR_MAX        FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
  58
  59/* STM32_SPI_CFG2 bit fields */
  60#define SPI_CFG2_COMM_SHIFT     17
  61#define SPI_CFG2_COMM           GENMASK(18, 17)
  62#define SPI_CFG2_MASTER         BIT(22)
  63#define SPI_CFG2_LSBFRST        BIT(23)
  64#define SPI_CFG2_CPHA           BIT(24)
  65#define SPI_CFG2_CPOL           BIT(25)
  66#define SPI_CFG2_SSM            BIT(26)
  67#define SPI_CFG2_AFCNTR         BIT(31)
  68
  69/* STM32_SPI_SR bit fields */
  70#define SPI_SR_RXP              BIT(0)
  71#define SPI_SR_TXP              BIT(1)
  72#define SPI_SR_EOT              BIT(3)
  73#define SPI_SR_TXTF             BIT(4)
  74#define SPI_SR_OVR              BIT(6)
  75#define SPI_SR_SUSP             BIT(11)
  76#define SPI_SR_RXPLVL_SHIFT     13
  77#define SPI_SR_RXPLVL           GENMASK(14, 13)
  78#define SPI_SR_RXWNE            BIT(15)
  79
  80/* STM32_SPI_IFCR bit fields */
  81#define SPI_IFCR_ALL            GENMASK(11, 3)
  82
  83/* STM32_SPI_I2SCFGR bit fields */
  84#define SPI_I2SCFGR_I2SMOD      BIT(0)
  85
  86#define MAX_CS_COUNT    4
  87
  88/* SPI Master Baud Rate min/max divisor */
  89#define STM32_MBR_DIV_MIN       (2 << SPI_CFG1_MBR_MIN)
  90#define STM32_MBR_DIV_MAX       (2 << SPI_CFG1_MBR_MAX)
  91
  92#define STM32_SPI_TIMEOUT_US    100000
  93
  94/* SPI Communication mode */
  95#define SPI_FULL_DUPLEX         0
  96#define SPI_SIMPLEX_TX          1
  97#define SPI_SIMPLEX_RX          2
  98#define SPI_HALF_DUPLEX         3
  99
 100struct stm32_spi_plat {
 101        void __iomem *base;
 102        struct clk clk;
 103        struct reset_ctl rst_ctl;
 104        struct gpio_desc cs_gpios[MAX_CS_COUNT];
 105};
 106
 107struct stm32_spi_priv {
 108        ulong bus_clk_rate;
 109        unsigned int fifo_size;
 110        unsigned int cur_bpw;
 111        unsigned int cur_hz;
 112        unsigned int cur_xferlen; /* current transfer length in bytes */
 113        unsigned int tx_len;      /* number of data to be written in bytes */
 114        unsigned int rx_len;      /* number of data to be read in bytes */
 115        const void *tx_buf;       /* data to be written, or NULL */
 116        void *rx_buf;             /* data to be read, or NULL */
 117        u32 cur_mode;
 118        bool cs_high;
 119};
 120
 121static void stm32_spi_write_txfifo(struct udevice *bus)
 122{
 123        struct stm32_spi_priv *priv = dev_get_priv(bus);
 124        struct stm32_spi_plat *plat = dev_get_plat(bus);
 125        void __iomem *base = plat->base;
 126
 127        while ((priv->tx_len > 0) &&
 128               (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) {
 129                u32 offs = priv->cur_xferlen - priv->tx_len;
 130
 131                if (priv->tx_len >= sizeof(u32) &&
 132                    IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
 133                        const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
 134
 135                        writel(*tx_buf32, base + STM32_SPI_TXDR);
 136                        priv->tx_len -= sizeof(u32);
 137                } else if (priv->tx_len >= sizeof(u16) &&
 138                           IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
 139                        const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
 140
 141                        writew(*tx_buf16, base + STM32_SPI_TXDR);
 142                        priv->tx_len -= sizeof(u16);
 143                } else {
 144                        const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
 145
 146                        writeb(*tx_buf8, base + STM32_SPI_TXDR);
 147                        priv->tx_len -= sizeof(u8);
 148                }
 149        }
 150
 151        log_debug("%d bytes left\n", priv->tx_len);
 152}
 153
 154static void stm32_spi_read_rxfifo(struct udevice *bus)
 155{
 156        struct stm32_spi_priv *priv = dev_get_priv(bus);
 157        struct stm32_spi_plat *plat = dev_get_plat(bus);
 158        void __iomem *base = plat->base;
 159        u32 sr = readl(base + STM32_SPI_SR);
 160        u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
 161
 162        while ((priv->rx_len > 0) &&
 163               ((sr & SPI_SR_RXP) ||
 164               ((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
 165                u32 offs = priv->cur_xferlen - priv->rx_len;
 166
 167                if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
 168                    (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
 169                        u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
 170
 171                        *rx_buf32 = readl(base + STM32_SPI_RXDR);
 172                        priv->rx_len -= sizeof(u32);
 173                } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
 174                           (priv->rx_len >= sizeof(u16) ||
 175                            (!(sr & SPI_SR_RXWNE) &&
 176                            (rxplvl >= 2 || priv->cur_bpw > 8)))) {
 177                        u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
 178
 179                        *rx_buf16 = readw(base + STM32_SPI_RXDR);
 180                        priv->rx_len -= sizeof(u16);
 181                } else {
 182                        u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
 183
 184                        *rx_buf8 = readb(base + STM32_SPI_RXDR);
 185                        priv->rx_len -= sizeof(u8);
 186                }
 187
 188                sr = readl(base + STM32_SPI_SR);
 189                rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
 190        }
 191
 192        log_debug("%d bytes left\n", priv->rx_len);
 193}
 194
 195static int stm32_spi_enable(void __iomem *base)
 196{
 197        log_debug("\n");
 198
 199        /* Enable the SPI hardware */
 200        setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
 201
 202        return 0;
 203}
 204
 205static int stm32_spi_disable(void __iomem *base)
 206{
 207        log_debug("\n");
 208
 209        /* Disable the SPI hardware */
 210        clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE);
 211
 212        return 0;
 213}
 214
 215static int stm32_spi_claim_bus(struct udevice *slave)
 216{
 217        struct udevice *bus = dev_get_parent(slave);
 218        struct stm32_spi_plat *plat = dev_get_plat(bus);
 219        void __iomem *base = plat->base;
 220
 221        dev_dbg(slave, "\n");
 222
 223        /* Enable the SPI hardware */
 224        return stm32_spi_enable(base);
 225}
 226
 227static int stm32_spi_release_bus(struct udevice *slave)
 228{
 229        struct udevice *bus = dev_get_parent(slave);
 230        struct stm32_spi_plat *plat = dev_get_plat(bus);
 231        void __iomem *base = plat->base;
 232
 233        dev_dbg(slave, "\n");
 234
 235        /* Disable the SPI hardware */
 236        return stm32_spi_disable(base);
 237}
 238
 239static void stm32_spi_stopxfer(struct udevice *dev)
 240{
 241        struct stm32_spi_plat *plat = dev_get_plat(dev);
 242        void __iomem *base = plat->base;
 243        u32 cr1, sr;
 244        int ret;
 245
 246        dev_dbg(dev, "\n");
 247
 248        cr1 = readl(base + STM32_SPI_CR1);
 249
 250        if (!(cr1 & SPI_CR1_SPE))
 251                return;
 252
 253        /* Wait on EOT or suspend the flow */
 254        ret = readl_poll_timeout(base + STM32_SPI_SR, sr,
 255                                 !(sr & SPI_SR_EOT), 100000);
 256        if (ret < 0) {
 257                if (cr1 & SPI_CR1_CSTART) {
 258                        writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1);
 259                        if (readl_poll_timeout(base + STM32_SPI_SR,
 260                                               sr, !(sr & SPI_SR_SUSP),
 261                                               100000) < 0)
 262                                dev_err(dev, "Suspend request timeout\n");
 263                }
 264        }
 265
 266        /* clear status flags */
 267        setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
 268}
 269
 270static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
 271{
 272        struct stm32_spi_plat *plat = dev_get_plat(dev);
 273        struct stm32_spi_priv *priv = dev_get_priv(dev);
 274
 275        dev_dbg(dev, "cs=%d enable=%d\n", cs, enable);
 276
 277        if (cs >= MAX_CS_COUNT)
 278                return -ENODEV;
 279
 280        if (!dm_gpio_is_valid(&plat->cs_gpios[cs]))
 281                return -EINVAL;
 282
 283        if (priv->cs_high)
 284                enable = !enable;
 285
 286        return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0);
 287}
 288
 289static int stm32_spi_set_mode(struct udevice *bus, uint mode)
 290{
 291        struct stm32_spi_priv *priv = dev_get_priv(bus);
 292        struct stm32_spi_plat *plat = dev_get_plat(bus);
 293        void __iomem *base = plat->base;
 294        u32 cfg2_clrb = 0, cfg2_setb = 0;
 295
 296        dev_dbg(bus, "mode=%d\n", mode);
 297
 298        if (mode & SPI_CPOL)
 299                cfg2_setb |= SPI_CFG2_CPOL;
 300        else
 301                cfg2_clrb |= SPI_CFG2_CPOL;
 302
 303        if (mode & SPI_CPHA)
 304                cfg2_setb |= SPI_CFG2_CPHA;
 305        else
 306                cfg2_clrb |= SPI_CFG2_CPHA;
 307
 308        if (mode & SPI_LSB_FIRST)
 309                cfg2_setb |= SPI_CFG2_LSBFRST;
 310        else
 311                cfg2_clrb |= SPI_CFG2_LSBFRST;
 312
 313        if (cfg2_clrb || cfg2_setb)
 314                clrsetbits_le32(base + STM32_SPI_CFG2,
 315                                cfg2_clrb, cfg2_setb);
 316
 317        if (mode & SPI_CS_HIGH)
 318                priv->cs_high = true;
 319        else
 320                priv->cs_high = false;
 321        return 0;
 322}
 323
 324static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
 325{
 326        struct stm32_spi_priv *priv = dev_get_priv(dev);
 327        struct stm32_spi_plat *plat = dev_get_plat(dev);
 328        void __iomem *base = plat->base;
 329        u32 fthlv, half_fifo;
 330
 331        /* data packet should not exceed 1/2 of fifo space */
 332        half_fifo = (priv->fifo_size / 2);
 333
 334        /* data_packet should not exceed transfer length */
 335        fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
 336
 337        /* align packet size with data registers access */
 338        fthlv -= (fthlv % 4);
 339
 340        if (!fthlv)
 341                fthlv = 1;
 342        clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
 343                        (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
 344
 345        return 0;
 346}
 347
 348static int stm32_spi_set_speed(struct udevice *bus, uint hz)
 349{
 350        struct stm32_spi_priv *priv = dev_get_priv(bus);
 351        struct stm32_spi_plat *plat = dev_get_plat(bus);
 352        void __iomem *base = plat->base;
 353        u32 mbrdiv;
 354        long div;
 355
 356        dev_dbg(bus, "hz=%d\n", hz);
 357
 358        if (priv->cur_hz == hz)
 359                return 0;
 360
 361        div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
 362
 363        if (div < STM32_MBR_DIV_MIN ||
 364            div > STM32_MBR_DIV_MAX)
 365                return -EINVAL;
 366
 367        /* Determine the first power of 2 greater than or equal to div */
 368        if (div & (div - 1))
 369                mbrdiv = fls(div);
 370        else
 371                mbrdiv = fls(div) - 1;
 372
 373        if (!mbrdiv)
 374                return -EINVAL;
 375
 376        clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR,
 377                        (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
 378
 379        priv->cur_hz = hz;
 380
 381        return 0;
 382}
 383
 384static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
 385                          const void *dout, void *din, unsigned long flags)
 386{
 387        struct udevice *bus = dev_get_parent(slave);
 388        struct dm_spi_slave_plat *slave_plat;
 389        struct stm32_spi_priv *priv = dev_get_priv(bus);
 390        struct stm32_spi_plat *plat = dev_get_plat(bus);
 391        void __iomem *base = plat->base;
 392        u32 sr;
 393        u32 ifcr = 0;
 394        u32 xferlen;
 395        u32 mode;
 396        int xfer_status = 0;
 397
 398        xferlen = bitlen / 8;
 399
 400        if (xferlen <= SPI_CR2_TSIZE)
 401                writel(xferlen, base + STM32_SPI_CR2);
 402        else
 403                return -EMSGSIZE;
 404
 405        priv->tx_buf = dout;
 406        priv->rx_buf = din;
 407        priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
 408        priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
 409
 410        mode = SPI_FULL_DUPLEX;
 411        if (!priv->tx_buf)
 412                mode = SPI_SIMPLEX_RX;
 413        else if (!priv->rx_buf)
 414                mode = SPI_SIMPLEX_TX;
 415
 416        if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
 417                priv->cur_mode = mode;
 418                priv->cur_xferlen = xferlen;
 419
 420                /* Disable the SPI hardware to unlock CFG1/CFG2 registers */
 421                stm32_spi_disable(base);
 422
 423                clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM,
 424                                mode << SPI_CFG2_COMM_SHIFT);
 425
 426                stm32_spi_set_fthlv(bus, xferlen);
 427
 428                /* Enable the SPI hardware */
 429                stm32_spi_enable(base);
 430        }
 431
 432        dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n",
 433                priv->tx_len, priv->rx_len);
 434
 435        slave_plat = dev_get_parent_plat(slave);
 436        if (flags & SPI_XFER_BEGIN)
 437                stm32_spi_set_cs(bus, slave_plat->cs, false);
 438
 439        /* Be sure to have data in fifo before starting data transfer */
 440        if (priv->tx_buf)
 441                stm32_spi_write_txfifo(bus);
 442
 443        setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART);
 444
 445        while (1) {
 446                sr = readl(base + STM32_SPI_SR);
 447
 448                if (sr & SPI_SR_OVR) {
 449                        dev_err(bus, "Overrun: RX data lost\n");
 450                        xfer_status = -EIO;
 451                        break;
 452                }
 453
 454                if (sr & SPI_SR_SUSP) {
 455                        dev_warn(bus, "System too slow is limiting data throughput\n");
 456
 457                        if (priv->rx_buf && priv->rx_len > 0)
 458                                stm32_spi_read_rxfifo(bus);
 459
 460                        ifcr |= SPI_SR_SUSP;
 461                }
 462
 463                if (sr & SPI_SR_TXTF)
 464                        ifcr |= SPI_SR_TXTF;
 465
 466                if (sr & SPI_SR_TXP)
 467                        if (priv->tx_buf && priv->tx_len > 0)
 468                                stm32_spi_write_txfifo(bus);
 469
 470                if (sr & SPI_SR_RXP)
 471                        if (priv->rx_buf && priv->rx_len > 0)
 472                                stm32_spi_read_rxfifo(bus);
 473
 474                if (sr & SPI_SR_EOT) {
 475                        if (priv->rx_buf && priv->rx_len > 0)
 476                                stm32_spi_read_rxfifo(bus);
 477                        break;
 478                }
 479
 480                writel(ifcr, base + STM32_SPI_IFCR);
 481        }
 482
 483        /* clear status flags */
 484        setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL);
 485        stm32_spi_stopxfer(bus);
 486
 487        if (flags & SPI_XFER_END)
 488                stm32_spi_set_cs(bus, slave_plat->cs, true);
 489
 490        return xfer_status;
 491}
 492
 493static int stm32_spi_get_fifo_size(struct udevice *dev)
 494{
 495        struct stm32_spi_plat *plat = dev_get_plat(dev);
 496        void __iomem *base = plat->base;
 497        u32 count = 0;
 498
 499        stm32_spi_enable(base);
 500
 501        while (readl(base + STM32_SPI_SR) & SPI_SR_TXP)
 502                writeb(++count, base + STM32_SPI_TXDR);
 503
 504        stm32_spi_disable(base);
 505
 506        dev_dbg(dev, "%d x 8-bit fifo size\n", count);
 507
 508        return count;
 509}
 510
 511static int stm32_spi_of_to_plat(struct udevice *dev)
 512{
 513        struct stm32_spi_plat *plat = dev_get_plat(dev);
 514        int ret;
 515
 516        plat->base = dev_read_addr_ptr(dev);
 517        if (!plat->base) {
 518                dev_err(dev, "can't get registers base address\n");
 519                return -ENOENT;
 520        }
 521
 522        ret = clk_get_by_index(dev, 0, &plat->clk);
 523        if (ret < 0)
 524                return ret;
 525
 526        ret = reset_get_by_index(dev, 0, &plat->rst_ctl);
 527        if (ret < 0)
 528                goto clk_err;
 529
 530        ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios,
 531                                        ARRAY_SIZE(plat->cs_gpios), 0);
 532        if (ret < 0) {
 533                dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret);
 534                ret = -ENOENT;
 535                goto clk_err;
 536        }
 537
 538        return 0;
 539
 540clk_err:
 541        clk_free(&plat->clk);
 542
 543        return ret;
 544}
 545
 546static int stm32_spi_probe(struct udevice *dev)
 547{
 548        struct stm32_spi_plat *plat = dev_get_plat(dev);
 549        struct stm32_spi_priv *priv = dev_get_priv(dev);
 550        void __iomem *base = plat->base;
 551        unsigned long clk_rate;
 552        int ret;
 553        unsigned int i;
 554
 555        /* enable clock */
 556        ret = clk_enable(&plat->clk);
 557        if (ret < 0)
 558                return ret;
 559
 560        clk_rate = clk_get_rate(&plat->clk);
 561        if (!clk_rate) {
 562                ret = -EINVAL;
 563                goto clk_err;
 564        }
 565
 566        priv->bus_clk_rate = clk_rate;
 567
 568        /* perform reset */
 569        reset_assert(&plat->rst_ctl);
 570        udelay(2);
 571        reset_deassert(&plat->rst_ctl);
 572
 573        priv->fifo_size = stm32_spi_get_fifo_size(dev);
 574        priv->cur_mode = SPI_FULL_DUPLEX;
 575        priv->cur_xferlen = 0;
 576        priv->cur_bpw = SPI_DEFAULT_WORDLEN;
 577        clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
 578                        priv->cur_bpw - 1);
 579
 580        for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) {
 581                if (!dm_gpio_is_valid(&plat->cs_gpios[i]))
 582                        continue;
 583
 584                dm_gpio_set_dir_flags(&plat->cs_gpios[i],
 585                                      GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 586        }
 587
 588        /* Ensure I2SMOD bit is kept cleared */
 589        clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
 590
 591        /*
 592         * - SS input value high
 593         * - transmitter half duplex direction
 594         * - automatic communication suspend when RX-Fifo is full
 595         */
 596        setbits_le32(base + STM32_SPI_CR1,
 597                     SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
 598
 599        /*
 600         * - Set the master mode (default Motorola mode)
 601         * - Consider 1 master/n slaves configuration and
 602         *   SS input value is determined by the SSI bit
 603         * - keep control of all associated GPIOs
 604         */
 605        setbits_le32(base + STM32_SPI_CFG2,
 606                     SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
 607
 608        return 0;
 609
 610clk_err:
 611        clk_disable(&plat->clk);
 612        clk_free(&plat->clk);
 613
 614        return ret;
 615};
 616
 617static int stm32_spi_remove(struct udevice *dev)
 618{
 619        struct stm32_spi_plat *plat = dev_get_plat(dev);
 620        void __iomem *base = plat->base;
 621        int ret;
 622
 623        stm32_spi_stopxfer(dev);
 624        stm32_spi_disable(base);
 625
 626        ret = reset_assert(&plat->rst_ctl);
 627        if (ret < 0)
 628                return ret;
 629
 630        reset_free(&plat->rst_ctl);
 631
 632        ret = clk_disable(&plat->clk);
 633        if (ret < 0)
 634                return ret;
 635
 636        clk_free(&plat->clk);
 637
 638        return ret;
 639};
 640
 641static const struct dm_spi_ops stm32_spi_ops = {
 642        .claim_bus      = stm32_spi_claim_bus,
 643        .release_bus    = stm32_spi_release_bus,
 644        .set_mode       = stm32_spi_set_mode,
 645        .set_speed      = stm32_spi_set_speed,
 646        .xfer           = stm32_spi_xfer,
 647};
 648
 649static const struct udevice_id stm32_spi_ids[] = {
 650        { .compatible = "st,stm32h7-spi", },
 651        { }
 652};
 653
 654U_BOOT_DRIVER(stm32_spi) = {
 655        .name                   = "stm32_spi",
 656        .id                     = UCLASS_SPI,
 657        .of_match               = stm32_spi_ids,
 658        .ops                    = &stm32_spi_ops,
 659        .of_to_plat             = stm32_spi_of_to_plat,
 660        .plat_auto              = sizeof(struct stm32_spi_plat),
 661        .priv_auto              = sizeof(struct stm32_spi_priv),
 662        .probe                  = stm32_spi_probe,
 663        .remove                 = stm32_spi_remove,
 664};
 665