LXR uboot/include/configs/T4240RDB.h

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright 2014 Freescale Semiconductor, Inc.
   4 * Copyright 2020-2021 NXP
   5 */
   6
   7/*
   8 * T4240 RDB board configuration file
   9 */
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13#include <linux/stringify.h>
  14
  15#define CFG_ICS307_REFCLK_HZ            25000000  /* ICS307 ref clk freq */
  16
  17#ifdef CONFIG_RAMBOOT_PBL
  18#ifndef CONFIG_SDCARD
  19#define CFG_RESET_VECTOR_ADDRESS     0xfffffffc
  20#else
  21#define RESET_VECTOR_OFFSET             0x27FFC
  22#define BOOT_PAGE_OFFSET                0x27000
  23
  24#ifdef  CONFIG_SDCARD
  25#define CFG_RESET_VECTOR_ADDRESS        0x200FFC
  26#define CFG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  27#define CFG_SYS_MMC_U_BOOT_DST  0x00200000
  28#define CFG_SYS_MMC_U_BOOT_START        0x00200000
  29#define CFG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  30#endif
  31
  32#endif
  33#endif /* CONFIG_RAMBOOT_PBL */
  34
  35/* High Level Configuration Options */
  36
  37#ifndef CFG_RESET_VECTOR_ADDRESS
  38#define CFG_RESET_VECTOR_ADDRESS        0xeffffffc
  39#endif
  40
  41#define CFG_SYS_NUM_CPC         CONFIG_SYS_NUM_DDR_CTLRS
  42
  43/*
  44 *  Config the L3 Cache as L3 SRAM
  45 */
  46#define CFG_SYS_INIT_L3_ADDR            0xFFFC0000
  47#define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
  48
  49#define CFG_SYS_DCSRBAR         0xf0000000
  50#define CFG_SYS_DCSRBAR_PHYS            0xf00000000ull
  51
  52/*
  53 * DDR Setup
  54 */
  55#define CFG_SYS_DDR_SDRAM_BASE  0x00000000
  56#define CFG_SYS_SDRAM_BASE              CFG_SYS_DDR_SDRAM_BASE
  57
  58/*
  59 * IFC Definitions
  60 */
  61#define CFG_SYS_FLASH_BASE      0xe0000000
  62#define CFG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CFG_SYS_FLASH_BASE)
  63
  64/* define to use L1 as initial stack */
  65#define CFG_SYS_INIT_RAM_ADDR   0xfdd00000      /* Initial L1 address */
  66#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  67#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xfe03c000
  68/* The assembler doesn't like typecast */
  69#define CFG_SYS_INIT_RAM_ADDR_PHYS \
  70        ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  71          CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  72#define CFG_SYS_INIT_RAM_SIZE           0x00004000
  73
  74#define CFG_SYS_INIT_SP_OFFSET  (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  75
  76/* Serial Port - controlled on board with jumper J8
  77 * open - index 2
  78 * shorted - index 1
  79 */
  80#define CFG_SYS_NS16550_CLK             (get_bus_freq(0)/2)
  81
  82#define CFG_SYS_BAUDRATE_TABLE  \
  83        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  84
  85#define CFG_SYS_NS16550_COM1    (CFG_SYS_CCSRBAR+0x11C500)
  86#define CFG_SYS_NS16550_COM2    (CFG_SYS_CCSRBAR+0x11C600)
  87#define CFG_SYS_NS16550_COM3    (CFG_SYS_CCSRBAR+0x11D500)
  88#define CFG_SYS_NS16550_COM4    (CFG_SYS_CCSRBAR+0x11D600)
  89
  90/* I2C */
  91
  92/*
  93 * General PCI
  94 * Memory space is mapped 1-1, but I/O space must start from 0.
  95 */
  96
  97/* controller 1, direct to uli, tgtid 3, Base address 20000 */
  98#define CFG_SYS_PCIE1_MEM_VIRT  0x80000000
  99#define CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
 100#define CFG_SYS_PCIE1_IO_VIRT   0xf8000000
 101#define CFG_SYS_PCIE1_IO_PHYS   0xff8000000ull
 102
 103/* controller 2, Slot 2, tgtid 2, Base address 201000 */
 104#define CFG_SYS_PCIE2_MEM_VIRT  0xa0000000
 105#define CFG_SYS_PCIE2_MEM_PHYS  0xc20000000ull
 106#define CFG_SYS_PCIE2_IO_VIRT   0xf8010000
 107#define CFG_SYS_PCIE2_IO_PHYS   0xff8010000ull
 108
 109/* controller 3, Slot 1, tgtid 1, Base address 202000 */
 110#define CFG_SYS_PCIE3_MEM_VIRT  0xc0000000
 111#define CFG_SYS_PCIE3_MEM_PHYS  0xc40000000ull
 112
 113/* controller 4, Base address 203000 */
 114#define CFG_SYS_PCIE4_MEM_BUS   0xe0000000
 115#define CFG_SYS_PCIE4_MEM_PHYS  0xc60000000ull
 116
 117/*
 118 * Miscellaneous configurable options
 119 */
 120
 121/*
 122 * For booting Linux, the board info and command line data
 123 * have to be in the first 64 MB of memory, since this is
 124 * the maximum mapped by the Linux kernel during initialization.
 125 */
 126#define CFG_SYS_BOOTMAPSZ       (64 << 20)      /* Initial map for Linux*/
 127
 128/*
 129 * Environment Configuration
 130 */
 131
 132#define HVBOOT                                  \
 133        "setenv bootargs config-addr=0x60000000; "      \
 134        "bootm 0x01000000 - 0x00f00000"
 135
 136/*
 137 * DDR Setup
 138 */
 139#define SPD_EEPROM_ADDRESS1     0x52
 140#define SPD_EEPROM_ADDRESS2     0x54
 141#define SPD_EEPROM_ADDRESS3     0x56
 142#define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1     /* for p3041/p5010 */
 143#define CFG_SYS_SDRAM_SIZE      4096    /* for fixed parameter use */
 144
 145/*
 146 * IFC Definitions
 147 */
 148#define CFG_SYS_NOR0_CSPR_EXT   (0xf)
 149#define CFG_SYS_NOR0_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS \
 150                                + 0x8000000) | \
 151                                CSPR_PORT_SIZE_16 | \
 152                                CSPR_MSEL_NOR | \
 153                                CSPR_V)
 154#define CFG_SYS_NOR1_CSPR_EXT   (0xf)
 155#define CFG_SYS_NOR1_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
 156                                CSPR_PORT_SIZE_16 | \
 157                                CSPR_MSEL_NOR | \
 158                                CSPR_V)
 159#define CFG_SYS_NOR_AMASK       IFC_AMASK(128*1024*1024)
 160/* NOR Flash Timing Params */
 161#define CFG_SYS_NOR_CSOR        CSOR_NAND_TRHZ_80
 162
 163#define CFG_SYS_NOR_FTIM0       (FTIM0_NOR_TACSE(0x4) | \
 164                                FTIM0_NOR_TEADC(0x5) | \
 165                                FTIM0_NOR_TEAHC(0x5))
 166#define CFG_SYS_NOR_FTIM1       (FTIM1_NOR_TACO(0x35) | \
 167                                FTIM1_NOR_TRAD_NOR(0x1A) |\
 168                                FTIM1_NOR_TSEQRAD_NOR(0x13))
 169#define CFG_SYS_NOR_FTIM2       (FTIM2_NOR_TCS(0x4) | \
 170                                FTIM2_NOR_TCH(0x4) | \
 171                                FTIM2_NOR_TWPH(0x0E) | \
 172                                FTIM2_NOR_TWP(0x1c))
 173#define CFG_SYS_NOR_FTIM3       0x0
 174
 175#define CFG_SYS_FLASH_BANKS_LIST        {CFG_SYS_FLASH_BASE_PHYS \
 176                                        + 0x8000000, CFG_SYS_FLASH_BASE_PHYS}
 177
 178/* NAND Flash on IFC */
 179#define CFG_SYS_NAND_BASE               0xff800000
 180#define CFG_SYS_NAND_BASE_PHYS  (0xf00000000ull | CFG_SYS_NAND_BASE)
 181
 182#define CFG_SYS_NAND_CSPR_EXT   (0xf)
 183#define CFG_SYS_NAND_CSPR       (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 184                                | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 185                                | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 186                                | CSPR_V)
 187#define CFG_SYS_NAND_AMASK      IFC_AMASK(64*1024)
 188
 189#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 190                                | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 191                                | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 192                                | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 193                                | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 194                                | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 195                                | CSOR_NAND_PB(128))    /*Page Per Block = 128*/
 196
 197/* ONFI NAND Flash mode0 Timing Params */
 198#define CFG_SYS_NAND_FTIM0              (FTIM0_NAND_TCCST(0x07) | \
 199                                        FTIM0_NAND_TWP(0x18)   | \
 200                                        FTIM0_NAND_TWCHT(0x07) | \
 201                                        FTIM0_NAND_TWH(0x0a))
 202#define CFG_SYS_NAND_FTIM1              (FTIM1_NAND_TADLE(0x32) | \
 203                                        FTIM1_NAND_TWBE(0x39)  | \
 204                                        FTIM1_NAND_TRR(0x0e)   | \
 205                                        FTIM1_NAND_TRP(0x18))
 206#define CFG_SYS_NAND_FTIM2              (FTIM2_NAND_TRAD(0x0f) | \
 207                                        FTIM2_NAND_TREH(0x0a) | \
 208                                        FTIM2_NAND_TWHRE(0x1e))
 209#define CFG_SYS_NAND_FTIM3              0x0
 210
 211#define CFG_SYS_NAND_BASE_LIST  { CFG_SYS_NAND_BASE }
 212
 213#if defined(CONFIG_MTD_RAW_NAND)
 214#define CFG_SYS_CSPR0_EXT               CFG_SYS_NAND_CSPR_EXT
 215#define CFG_SYS_CSPR0           CFG_SYS_NAND_CSPR
 216#define CFG_SYS_AMASK0          CFG_SYS_NAND_AMASK
 217#define CFG_SYS_CSOR0           CFG_SYS_NAND_CSOR
 218#define CFG_SYS_CS0_FTIM0               CFG_SYS_NAND_FTIM0
 219#define CFG_SYS_CS0_FTIM1               CFG_SYS_NAND_FTIM1
 220#define CFG_SYS_CS0_FTIM2               CFG_SYS_NAND_FTIM2
 221#define CFG_SYS_CS0_FTIM3               CFG_SYS_NAND_FTIM3
 222#define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR0_CSPR_EXT
 223#define CFG_SYS_CSPR2           CFG_SYS_NOR0_CSPR
 224#define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 225#define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 226#define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 227#define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 228#define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 229#define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 230#else
 231#define CFG_SYS_CSPR0_EXT               CFG_SYS_NOR0_CSPR_EXT
 232#define CFG_SYS_CSPR0           CFG_SYS_NOR0_CSPR
 233#define CFG_SYS_AMASK0          CFG_SYS_NOR_AMASK
 234#define CFG_SYS_CSOR0           CFG_SYS_NOR_CSOR
 235#define CFG_SYS_CS0_FTIM0               CFG_SYS_NOR_FTIM0
 236#define CFG_SYS_CS0_FTIM1               CFG_SYS_NOR_FTIM1
 237#define CFG_SYS_CS0_FTIM2               CFG_SYS_NOR_FTIM2
 238#define CFG_SYS_CS0_FTIM3               CFG_SYS_NOR_FTIM3
 239#define CFG_SYS_CSPR1_EXT               CFG_SYS_NAND_CSPR_EXT
 240#define CFG_SYS_CSPR1           CFG_SYS_NAND_CSPR
 241#define CFG_SYS_AMASK1          CFG_SYS_NAND_AMASK
 242#define CFG_SYS_CSOR1           CFG_SYS_NAND_CSOR
 243#define CFG_SYS_CS1_FTIM0               CFG_SYS_NAND_FTIM0
 244#define CFG_SYS_CS1_FTIM1               CFG_SYS_NAND_FTIM1
 245#define CFG_SYS_CS1_FTIM2               CFG_SYS_NAND_FTIM2
 246#define CFG_SYS_CS1_FTIM3               CFG_SYS_NAND_FTIM3
 247#endif
 248#define CFG_SYS_CSPR2_EXT               CFG_SYS_NOR1_CSPR_EXT
 249#define CFG_SYS_CSPR2           CFG_SYS_NOR1_CSPR
 250#define CFG_SYS_AMASK2          CFG_SYS_NOR_AMASK
 251#define CFG_SYS_CSOR2           CFG_SYS_NOR_CSOR
 252#define CFG_SYS_CS2_FTIM0               CFG_SYS_NOR_FTIM0
 253#define CFG_SYS_CS2_FTIM1               CFG_SYS_NOR_FTIM1
 254#define CFG_SYS_CS2_FTIM2               CFG_SYS_NOR_FTIM2
 255#define CFG_SYS_CS2_FTIM3               CFG_SYS_NOR_FTIM3
 256
 257/* CPLD on IFC */
 258#define CFG_SYS_CPLD_BASE       0xffdf0000
 259#define CFG_SYS_CPLD_BASE_PHYS  (0xf00000000ull | CFG_SYS_CPLD_BASE)
 260#define CFG_SYS_CSPR3_EXT       (0xf)
 261#define CFG_SYS_CSPR3   (CSPR_PHYS_ADDR(CFG_SYS_CPLD_BASE_PHYS) \
 262                                | CSPR_PORT_SIZE_8 \
 263                                | CSPR_MSEL_GPCM \
 264                                | CSPR_V)
 265
 266#define CFG_SYS_AMASK3  IFC_AMASK(64 * 1024)
 267#define CFG_SYS_CSOR3   0x0
 268
 269/* CPLD Timing parameters for IFC CS3 */
 270#define CFG_SYS_CS3_FTIM0               (FTIM0_GPCM_TACSE(0x0e) | \
 271                                        FTIM0_GPCM_TEADC(0x0e) | \
 272                                        FTIM0_GPCM_TEAHC(0x0e))
 273#define CFG_SYS_CS3_FTIM1               (FTIM1_GPCM_TACO(0x0e) | \
 274                                        FTIM1_GPCM_TRAD(0x1f))
 275#define CFG_SYS_CS3_FTIM2               (FTIM2_GPCM_TCS(0x0e) | \
 276                                        FTIM2_GPCM_TCH(0x8) | \
 277                                        FTIM2_GPCM_TWP(0x1f))
 278#define CFG_SYS_CS3_FTIM3               0x0
 279
 280/* I2C */
 281#define I2C_MUX_PCA_ADDR_PRI            0x77 /* I2C bus multiplexer,primary */
 282#define I2C_MUX_PCA_ADDR_SEC            0x76 /* I2C bus multiplexer,secondary */
 283
 284#define I2C_MUX_CH_DEFAULT      0x8
 285#define I2C_MUX_CH_VOL_MONITOR  0xa
 286#define I2C_MUX_CH_VSC3316_FS   0xc
 287#define I2C_MUX_CH_VSC3316_BS   0xd
 288
 289/* Voltage monitor on channel 2*/
 290#define I2C_VOL_MONITOR_ADDR            0x40
 291#define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 292#define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 293#define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 294
 295/* The lowest and highest voltage allowed for T4240RDB */
 296#define VDD_MV_MIN                      819
 297#define VDD_MV_MAX                      1212
 298
 299/*
 300 * eSPI - Enhanced SPI
 301 */
 302
 303/* Qman/Bman */
 304#ifndef CONFIG_NOBQFMAN
 305#define CFG_SYS_BMAN_NUM_PORTALS        50
 306#define CFG_SYS_BMAN_MEM_BASE   0xf4000000
 307#define CFG_SYS_BMAN_MEM_PHYS   0xff4000000ull
 308#define CFG_SYS_BMAN_MEM_SIZE   0x02000000
 309#define CFG_SYS_BMAN_SP_CENA_SIZE    0x4000
 310#define CFG_SYS_BMAN_SP_CINH_SIZE    0x1000
 311#define CFG_SYS_BMAN_CENA_BASE       CFG_SYS_BMAN_MEM_BASE
 312#define CFG_SYS_BMAN_CENA_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 313#define CFG_SYS_BMAN_CINH_BASE       (CFG_SYS_BMAN_MEM_BASE + \
 314                                        CFG_SYS_BMAN_CENA_SIZE)
 315#define CFG_SYS_BMAN_CINH_SIZE       (CFG_SYS_BMAN_MEM_SIZE >> 1)
 316#define CFG_SYS_BMAN_SWP_ISDR_REG    0xE08
 317#define CFG_SYS_QMAN_NUM_PORTALS        50
 318#define CFG_SYS_QMAN_MEM_BASE   0xf6000000
 319#define CFG_SYS_QMAN_MEM_PHYS   0xff6000000ull
 320#define CFG_SYS_QMAN_MEM_SIZE   0x02000000
 321#define CFG_SYS_QMAN_SP_CINH_SIZE    0x1000
 322#define CFG_SYS_QMAN_CENA_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 323#define CFG_SYS_QMAN_CINH_BASE       (CFG_SYS_QMAN_MEM_BASE + \
 324                                        CFG_SYS_QMAN_CENA_SIZE)
 325#define CFG_SYS_QMAN_CINH_SIZE       (CFG_SYS_QMAN_MEM_SIZE >> 1)
 326#define CFG_SYS_QMAN_SWP_ISDR_REG       0xE08
 327#endif /* CONFIG_NOBQFMAN */
 328
 329#ifdef CONFIG_SYS_DPAA_FMAN
 330#define SGMII_PHY_ADDR1 0x0
 331#define SGMII_PHY_ADDR2 0x1
 332#define SGMII_PHY_ADDR3 0x2
 333#define SGMII_PHY_ADDR4 0x3
 334#define SGMII_PHY_ADDR5 0x4
 335#define SGMII_PHY_ADDR6 0x5
 336#define SGMII_PHY_ADDR7 0x6
 337#define SGMII_PHY_ADDR8 0x7
 338#define FM1_10GEC1_PHY_ADDR     0x10
 339#define FM1_10GEC2_PHY_ADDR     0x11
 340#define FM2_10GEC1_PHY_ADDR     0x12
 341#define FM2_10GEC2_PHY_ADDR     0x13
 342#define CORTINA_PHY_ADDR1       FM1_10GEC1_PHY_ADDR
 343#define CORTINA_PHY_ADDR2       FM1_10GEC2_PHY_ADDR
 344#define CORTINA_PHY_ADDR3       FM2_10GEC1_PHY_ADDR
 345#define CORTINA_PHY_ADDR4       FM2_10GEC2_PHY_ADDR
 346#endif
 347
 348/*
 349* USB
 350*/
 351
 352#ifdef CONFIG_MMC
 353#define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 354#endif
 355
 356
 357#define __USB_PHY_TYPE  utmi
 358
 359/*
 360 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
 361 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
 362 * interleaving. It can be cacheline, page, bank, superbank.
 363 * See doc/README.fsl-ddr for details.
 364 */
 365#ifdef CONFIG_ARCH_T4240
 366#define CTRL_INTLV_PREFERED 3way_4KB
 367#else
 368#define CTRL_INTLV_PREFERED cacheline
 369#endif
 370
 371#define CFG_EXTRA_ENV_SETTINGS                          \
 372        "hwconfig=fsl_ddr:"                                     \
 373        "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 374        "bank_intlv=auto;"                                      \
 375        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 376        "netdev=eth0\0"                                         \
 377        "uboot=" CONFIG_UBOOTPATH "\0"          \
 378        "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
 379        "tftpflash=tftpboot $loadaddr $uboot && "               \
 380        "protect off $ubootaddr +$filesize && "                 \
 381        "erase $ubootaddr +$filesize && "                       \
 382        "cp.b $loadaddr $ubootaddr $filesize && "               \
 383        "protect on $ubootaddr +$filesize && "                  \
 384        "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 385        "consoledev=ttyS0\0"                                    \
 386        "ramdiskaddr=2000000\0"                                 \
 387        "ramdiskfile=t4240rdb/ramdisk.uboot\0"                  \
 388        "fdtaddr=1e00000\0"                                     \
 389        "fdtfile=t4240rdb/t4240rdb.dtb\0"                       \
 390        "bdev=sda3\0"
 391
 392#define HVBOOT                                  \
 393        "setenv bootargs config-addr=0x60000000; "      \
 394        "bootm 0x01000000 - 0x00f00000"
 395
 396#include <asm/fsl_secure_boot.h>
 397
 398#endif  /* __CONFIG_H */
 399