LXR uboot/include/configs/socfpga

   1/* SPDX-License-Identifier: GPL-2.0+ */
   2/*
   3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
   4 */
   5#ifndef __CONFIG_SOCFPGA_COMMON_H__
   6#define __CONFIG_SOCFPGA_COMMON_H__
   7
   8#include <linux/stringify.h>
   9
  10/*
  11 * Memory configurations
  12 */
  13#define PHYS_SDRAM_1                    0x0
  14#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  15#define CFG_SYS_INIT_RAM_ADDR   0xFFFF0000
  16#define CFG_SYS_INIT_RAM_SIZE   SOCFPGA_PHYS_OCRAM_SIZE
  17#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  18#define CFG_SYS_INIT_RAM_ADDR   0xFFE00000
  19/* SPL memory allocation configuration, this is for FAT implementation */
  20#define CFG_SYS_INIT_RAM_SIZE   (SOCFPGA_PHYS_OCRAM_SIZE - \
  21                                         CONFIG_SYS_SPL_MALLOC_SIZE)
  22#endif
  23
  24/*
  25 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  26 * SRAM as bootcounter storage. Make sure to not put the stack directly
  27 * at this address to not overwrite the bootcounter by checking, if the
  28 * bootcounter address is located in the internal SRAM.
  29 */
  30#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CFG_SYS_INIT_RAM_ADDR) &&     \
  31     (CONFIG_SYS_BOOTCOUNT_ADDR < (CFG_SYS_INIT_RAM_ADDR +      \
  32                                   CFG_SYS_INIT_RAM_SIZE)))
  33#endif
  34
  35/*
  36 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  37 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  38 * in U-Boot pre-reloc is higher than in SPL.
  39 */
  40
  41#define CFG_SYS_SDRAM_BASE              PHYS_SDRAM_1
  42
  43/*
  44 * U-Boot general configurations
  45 */
  46                                                /* Print buffer size */
  47
  48/*
  49 * Cache
  50 */
  51#define CFG_SYS_PL310_BASE              SOCFPGA_MPUL2_ADDRESS
  52
  53/*
  54 * L4 OSC1 Timer 0
  55 */
  56#ifndef CONFIG_TIMER
  57#define CFG_SYS_TIMERBASE               SOCFPGA_OSC1TIMER0_ADDRESS
  58#define CFG_SYS_TIMER_COUNTER   (CFG_SYS_TIMERBASE + 0x4)
  59#ifndef CFG_SYS_TIMER_RATE
  60#define CFG_SYS_TIMER_RATE              25000000
  61#endif
  62#endif
  63
  64/*
  65 * L4 Watchdog
  66 */
  67#define CFG_DW_WDT_CLOCK_KHZ            25000
  68
  69/*
  70 * NAND Support
  71 */
  72#ifdef CONFIG_NAND_DENALI
  73#define CFG_SYS_NAND_REGS_BASE  SOCFPGA_NANDREGS_ADDRESS
  74#define CFG_SYS_NAND_DATA_BASE  SOCFPGA_NANDDATA_ADDRESS
  75#endif
  76
  77/*
  78 * USB
  79 */
  80
  81/*
  82 * USB Gadget (DFU, UMS)
  83 */
  84#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
  85#define DFU_DEFAULT_POLL_TIMEOUT        300
  86#endif
  87
  88/*
  89 * U-Boot environment
  90 */
  91
  92/* Environment for SDMMC boot */
  93
  94/* Environment for QSPI boot */
  95
  96/*
  97 * SPL
  98 *
  99 * SRAM Memory layout for gen 5:
 100 *
 101 * 0xFFFF_0000 ...... Start of SRAM
 102 * 0xFFFF_xxxx ...... Top of stack (grows down)
 103 * 0xFFFF_yyyy ...... Global Data
 104 * 0xFFFF_zzzz ...... Malloc area
 105 * 0xFFFF_FFFF ...... End of SRAM
 106 *
 107 * SRAM Memory layout for Arria 10:
 108 * 0xFFE0_0000 ...... Start of SRAM (bottom)
 109 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 110 * 0xFFEy_yyyy ...... Global Data
 111 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 112 * 0xFFE3_FFFF ...... End of SRAM (top)
 113 */
 114
 115/* SPL QSPI boot support */
 116
 117/* SPL NAND boot support */
 118
 119/* Extra Environment */
 120#ifndef CONFIG_SPL_BUILD
 121
 122#ifdef CONFIG_CMD_DHCP
 123#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
 124#else
 125#define BOOT_TARGET_DEVICES_DHCP(func)
 126#endif
 127
 128#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 129#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 130#else
 131#define BOOT_TARGET_DEVICES_PXE(func)
 132#endif
 133
 134#ifdef CONFIG_CMD_MMC
 135#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 136#else
 137#define BOOT_TARGET_DEVICES_MMC(func)
 138#endif
 139
 140#define BOOT_TARGET_DEVICES(func) \
 141        BOOT_TARGET_DEVICES_MMC(func) \
 142        BOOT_TARGET_DEVICES_PXE(func) \
 143        BOOT_TARGET_DEVICES_DHCP(func)
 144
 145#include <config_distro_bootcmd.h>
 146
 147#ifndef CFG_EXTRA_ENV_SETTINGS
 148#define CFG_EXTRA_ENV_SETTINGS \
 149        "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 150        "bootm_size=0xa000000\0" \
 151        "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 152        "fdt_addr_r=0x02000000\0" \
 153        "scriptaddr=0x02100000\0" \
 154        "pxefile_addr_r=0x02200000\0" \
 155        "ramdisk_addr_r=0x02300000\0" \
 156        "socfpga_legacy_reset_compat=1\0" \
 157        BOOTENV
 158
 159#endif
 160#endif
 161
 162#endif  /* __CONFIG_SOCFPGA_COMMON_H__ */
 163