LXR uboot/arch/arm/cpu/armv7/ls102xa/soc.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright 2015 Freescale Semiconductor, Inc.
   4 */
   5
   6#include <common.h>
   7#include <log.h>
   8#include <asm/arch/clock.h>
   9#include <asm/io.h>
  10#include <asm/arch/fsl_serdes.h>
  11#include <asm/arch/immap_ls102xa.h>
  12#include <asm/arch/ls102xa_soc.h>
  13#include <asm/arch/ls102xa_stream_id.h>
  14#include <fsl_csu.h>
  15#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
  16#include <fsl_ddr_sdram.h>
  17#endif
  18
  19struct liodn_id_table sec_liodn_tbl[] = {
  20        SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
  21        SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
  22        SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
  23        SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
  24        SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
  25        SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
  26        SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
  27        SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
  28        SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
  29        SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
  30        SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
  31        SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
  32        SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
  33        SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
  34        SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
  35        SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
  36};
  37
  38struct smmu_stream_id dev_stream_id[] = {
  39        { 0x100, 0x01, "ETSEC MAC1" },
  40        { 0x104, 0x02, "ETSEC MAC2" },
  41        { 0x108, 0x03, "ETSEC MAC3" },
  42        { 0x10c, 0x04, "PEX1" },
  43        { 0x110, 0x05, "PEX2" },
  44        { 0x114, 0x06, "qDMA" },
  45        { 0x118, 0x07, "SATA" },
  46        { 0x11c, 0x08, "USB3" },
  47        { 0x120, 0x09, "QE" },
  48        { 0x124, 0x0a, "eSDHC" },
  49        { 0x128, 0x0b, "eMA" },
  50        { 0x14c, 0x0c, "2D-ACE" },
  51        { 0x150, 0x0d, "USB2" },
  52        { 0x18c, 0x0e, "DEBUG" },
  53};
  54
  55unsigned int get_soc_major_rev(void)
  56{
  57        struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
  58        unsigned int svr, major;
  59
  60        svr = in_be32(&gur->svr);
  61        major = SVR_MAJ(svr);
  62
  63        return major;
  64}
  65
  66static void erratum_a009008(void)
  67{
  68#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
  69        u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  70
  71        clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  72                        0xF << 6,
  73                        SCFG_USB_TXVREFTUNE << 6);
  74#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
  75}
  76
  77static void erratum_a009798(void)
  78{
  79#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
  80        u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  81
  82        clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
  83                        SCFG_USB_SQRXTUNE_MASK << 23);
  84#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
  85}
  86
  87static void erratum_a008997(void)
  88{
  89#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
  90        u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
  91
  92        clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
  93                        SCFG_USB_PCSTXSWINGFULL_MASK,
  94                        SCFG_USB_PCSTXSWINGFULL_VAL);
  95#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
  96}
  97
  98static void erratum_a009007(void)
  99{
 100#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
 101        void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
 102
 103        out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
 104        out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
 105        out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
 106        out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
 107#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
 108}
 109
 110static void erratum_a008850_early(void)
 111{
 112#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 113        /* part 1 of 2 */
 114        struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 115                                                CONFIG_SYS_CCI400_OFFSET);
 116        struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 117
 118        /* disables propagation of barrier transactions to DDRC from CCI400 */
 119        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 120
 121        /* disable the re-ordering in DDRC */
 122        out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 123#endif
 124}
 125
 126void erratum_a008850_post(void)
 127{
 128#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 129        /* part 2 of 2 */
 130        struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
 131                                                CONFIG_SYS_CCI400_OFFSET);
 132        struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
 133        u32 tmp;
 134
 135        /* enable propagation of barrier transactions to DDRC from CCI400 */
 136        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 137
 138        /* enable the re-ordering in DDRC */
 139        tmp = in_be32(&ddr->eor);
 140        tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
 141        out_be32(&ddr->eor, tmp);
 142#endif
 143}
 144
 145void s_init(void)
 146{
 147}
 148
 149#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 150void erratum_a010315(void)
 151{
 152        int i;
 153
 154        for (i = PCIE1; i <= PCIE2; i++)
 155                if (!is_serdes_configured(i)) {
 156                        debug("PCIe%d: disabled all R/W permission!\n", i);
 157                        set_pcie_ns_access(i, 0);
 158                }
 159}
 160#endif
 161
 162int arch_soc_init(void)
 163{
 164        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 165        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
 166                                        CONFIG_SYS_CCI400_OFFSET);
 167        unsigned int major;
 168
 169#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 170        enable_layerscape_ns_access();
 171#endif
 172
 173#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_SYS_FSL_QSPI_SKIP_CLKSEL)
 174        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 175#endif
 176
 177        /* Configure Little endian for SAI, ASRC and SPDIF */
 178        out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
 179
 180        /*
 181         * Enable snoop requests and DVM message requests for
 182         * All the slave insterfaces.
 183         */
 184        out_le32(&cci->slave[0].snoop_ctrl,
 185                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 186        out_le32(&cci->slave[1].snoop_ctrl,
 187                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 188        out_le32(&cci->slave[2].snoop_ctrl,
 189                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 190        out_le32(&cci->slave[4].snoop_ctrl,
 191                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 192
 193        major = get_soc_major_rev();
 194        if (major == SOC_MAJOR_VER_1_0) {
 195                /*
 196                 * Set CCI-400 Slave interface S1, S2 Shareable Override
 197                 * Register All transactions are treated as non-shareable
 198                 */
 199                out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 200                out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 201        }
 202
 203        /* Enable all the snoop signal for various masters */
 204        out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
 205                                SCFG_SNPCNFGCR_DCU_RD_WR |
 206                                SCFG_SNPCNFGCR_SATA_RD_WR |
 207                                SCFG_SNPCNFGCR_USB3_RD_WR |
 208                                SCFG_SNPCNFGCR_DBG_RD_WR |
 209                                SCFG_SNPCNFGCR_EDMA_SNP);
 210
 211        /*
 212         * Memory controller require a register write before being enabled.
 213         * Affects: DDR
 214         * Register: EDDRTQCFG
 215         * Description: Memory controller performance is not optimal with
 216         *              default internal target queue register values.
 217         * Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
 218         */
 219        out_be32(&scfg->eddrtqcfg, 0x63b20042);
 220
 221        /* Erratum */
 222        erratum_a008850_early();
 223        erratum_a009008();
 224        erratum_a009798();
 225        erratum_a008997();
 226        erratum_a009007();
 227
 228        return 0;
 229}
 230
 231int ls102xa_smmu_stream_id_init(void)
 232{
 233        ls1021x_config_caam_stream_id(sec_liodn_tbl,
 234                                      ARRAY_SIZE(sec_liodn_tbl));
 235
 236        ls102xa_config_smmu_stream_id(dev_stream_id,
 237                                      ARRAY_SIZE(dev_stream_id));
 238
 239        return 0;
 240}
 241