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9#ifndef _ASM_ARCH_CLOCK_H
10#define _ASM_ARCH_CLOCK_H
11
12#include <asm/arch/crm_regs.h>
13
14#ifdef CONFIG_SYS_MX7_HCLK
15#define MXC_HCLK CONFIG_SYS_MX7_HCLK
16#else
17#define MXC_HCLK 24000000
18#endif
19
20#ifdef CONFIG_SYS_MX7_CLK32
21#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
22#else
23#define MXC_CLK32 32768
24#endif
25
26
27enum mxc_clock {
28 MXC_ARM_CLK = 0,
29 MXC_AHB_CLK,
30 MXC_IPG_CLK,
31 MXC_UART_CLK,
32 MXC_CSPI_CLK,
33 MXC_AXI_CLK,
34 MXC_DDR_CLK,
35 MXC_ESDHC_CLK,
36 MXC_ESDHC2_CLK,
37 MXC_ESDHC3_CLK,
38 MXC_I2C_CLK,
39};
40
41
42enum pll_clocks {
43 PLL_CORE,
44 PLL_SYS,
45 PLL_ENET,
46 PLL_AUDIO,
47 PLL_VIDEO,
48 PLL_DDR,
49 PLL_USB,
50};
51
52
53enum clk_root_src {
54 OSC_24M_CLK,
55
56 PLL_ARM_MAIN_800M_CLK,
57
58 PLL_SYS_MAIN_480M_CLK,
59 PLL_SYS_MAIN_240M_CLK,
60 PLL_SYS_MAIN_120M_CLK,
61 PLL_SYS_PFD0_392M_CLK,
62 PLL_SYS_PFD0_196M_CLK,
63 PLL_SYS_PFD1_332M_CLK,
64 PLL_SYS_PFD1_166M_CLK,
65 PLL_SYS_PFD2_270M_CLK,
66 PLL_SYS_PFD2_135M_CLK,
67 PLL_SYS_PFD3_CLK,
68 PLL_SYS_PFD4_CLK,
69 PLL_SYS_PFD5_CLK,
70 PLL_SYS_PFD6_CLK,
71 PLL_SYS_PFD7_CLK,
72
73 PLL_ENET_MAIN_500M_CLK,
74 PLL_ENET_MAIN_250M_CLK,
75 PLL_ENET_MAIN_125M_CLK,
76 PLL_ENET_MAIN_100M_CLK,
77 PLL_ENET_MAIN_50M_CLK,
78 PLL_ENET_MAIN_40M_CLK,
79 PLL_ENET_MAIN_25M_CLK,
80
81 PLL_DRAM_MAIN_1066M_CLK,
82 PLL_DRAM_MAIN_533M_CLK,
83
84 PLL_AUDIO_MAIN_CLK,
85 PLL_VIDEO_MAIN_CLK,
86
87 PLL_USB_MAIN_480M_CLK,
88
89 EXT_CLK_1,
90 EXT_CLK_2,
91 EXT_CLK_3,
92 EXT_CLK_4,
93
94 REF_1M_CLK,
95 OSC_32K_CLK,
96};
97
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99
100
101enum clk_root_index {
102 ARM_A7_CLK_ROOT = 0,
103 ARM_M4_CLK_ROOT = 1,
104 ARM_M0_CLK_ROOT = 2,
105 MAIN_AXI_CLK_ROOT = 16,
106 DISP_AXI_CLK_ROOT = 17,
107 ENET_AXI_CLK_ROOT = 18,
108 NAND_USDHC_BUS_CLK_ROOT = 19,
109 AHB_CLK_ROOT = 32,
110 DRAM_PHYM_CLK_ROOT = 48,
111 DRAM_CLK_ROOT = 49,
112 DRAM_PHYM_ALT_CLK_ROOT = 64,
113 DRAM_ALT_CLK_ROOT = 65,
114 USB_HSIC_CLK_ROOT = 66,
115 PCIE_CTRL_CLK_ROOT = 67,
116 PCIE_PHY_CLK_ROOT = 68,
117 EPDC_PIXEL_CLK_ROOT = 69,
118 LCDIF_PIXEL_CLK_ROOT = 70,
119 MIPI_DSI_EXTSER_CLK_ROOT = 71,
120 MIPI_CSI_WARP_CLK_ROOT = 72,
121 MIPI_DPHY_REF_CLK_ROOT = 73,
122 SAI1_CLK_ROOT = 74,
123 SAI2_CLK_ROOT = 75,
124 SAI3_CLK_ROOT = 76,
125 SPDIF_CLK_ROOT = 77,
126 ENET1_REF_CLK_ROOT = 78,
127 ENET1_TIME_CLK_ROOT = 79,
128 ENET2_REF_CLK_ROOT = 80,
129 ENET2_TIME_CLK_ROOT = 81,
130 ENET_PHY_REF_CLK_ROOT = 82,
131 EIM_CLK_ROOT = 83,
132 NAND_CLK_ROOT = 84,
133 QSPI_CLK_ROOT = 85,
134 USDHC1_CLK_ROOT = 86,
135 USDHC2_CLK_ROOT = 87,
136 USDHC3_CLK_ROOT = 88,
137 CAN1_CLK_ROOT = 89,
138 CAN2_CLK_ROOT = 90,
139 I2C1_CLK_ROOT = 91,
140 I2C2_CLK_ROOT = 92,
141 I2C3_CLK_ROOT = 93,
142 I2C4_CLK_ROOT = 94,
143 UART1_CLK_ROOT = 95,
144 UART2_CLK_ROOT = 96,
145 UART3_CLK_ROOT = 97,
146 UART4_CLK_ROOT = 98,
147 UART5_CLK_ROOT = 99,
148 UART6_CLK_ROOT = 100,
149 UART7_CLK_ROOT = 101,
150 ECSPI1_CLK_ROOT = 102,
151 ECSPI2_CLK_ROOT = 103,
152 ECSPI3_CLK_ROOT = 104,
153 ECSPI4_CLK_ROOT = 105,
154 PWM1_CLK_ROOT = 106,
155 PWM2_CLK_ROOT = 107,
156 PWM3_CLK_ROOT = 108,
157 PWM4_CLK_ROOT = 109,
158 FLEXTIMER1_CLK_ROOT = 110,
159 FLEXTIMER2_CLK_ROOT = 111,
160 SIM1_CLK_ROOT = 112,
161 SIM2_CLK_ROOT = 113,
162 GPT1_CLK_ROOT = 114,
163 GPT2_CLK_ROOT = 115,
164 GPT3_CLK_ROOT = 116,
165 GPT4_CLK_ROOT = 117,
166 TRACE_CLK_ROOT = 118,
167 WDOG_CLK_ROOT = 119,
168 CSI_MCLK_CLK_ROOT = 120,
169 AUDIO_MCLK_CLK_ROOT = 121,
170 WRCLK_CLK_ROOT = 122,
171 IPP_DO_CLKO1 = 123,
172 IPP_DO_CLKO2 = 124,
173
174 CLK_ROOT_MAX,
175};
176
177#if (CONFIG_CONS_INDEX == 0)
178#define UART_CLK_ROOT UART1_CLK_ROOT
179#elif (CONFIG_CONS_INDEX == 1)
180#define UART_CLK_ROOT UART2_CLK_ROOT
181#elif (CONFIG_CONS_INDEX == 2)
182#define UART_CLK_ROOT UART3_CLK_ROOT
183#elif (CONFIG_CONS_INDEX == 3)
184#define UART_CLK_ROOT UART4_CLK_ROOT
185#elif (CONFIG_CONS_INDEX == 4)
186#define UART_CLK_ROOT UART5_CLK_ROOT
187#elif (CONFIG_CONS_INDEX == 5)
188#define UART_CLK_ROOT UART6_CLK_ROOT
189#elif (CONFIG_CONS_INDEX == 6)
190#define UART_CLK_ROOT UART7_CLK_ROOT
191#else
192#error "Invalid IMX UART ID for serial console is defined"
193#endif
194
195struct clk_root_setting {
196 enum clk_root_index root;
197 u32 setting;
198};
199
200
201
202
203enum clk_ccgr_index {
204 CCGR_CPU = 0,
205 CCGR_M4 = 1,
206 CCGR_SIM_MAIN = 4,
207 CCGR_SIM_DISPLAY = 5,
208 CCGR_SIM_ENET = 6,
209 CCGR_SIM_M = 7,
210 CCGR_SIM_S = 8,
211 CCGR_SIM_WAKEUP = 9,
212 CCGR_IPMUX1 = 10,
213 CCGR_IPMUX2 = 11,
214 CCGR_IPMUX3 = 12,
215 CCGR_ROM = 16,
216 CCGR_OCRAM = 17,
217 CCGR_OCRAM_S = 18,
218 CCGR_DRAM = 19,
219 CCGR_RAWNAND = 20,
220 CCGR_QSPI = 21,
221 CCGR_WEIM = 22,
222 CCGR_ADC = 32,
223 CCGR_ANATOP = 33,
224 CCGR_SCTR = 34,
225 CCGR_OCOTP = 35,
226 CCGR_CAAM = 36,
227 CCGR_SNVS = 37,
228 CCGR_RDC = 38,
229 CCGR_MU = 39,
230 CCGR_HS = 40,
231 CCGR_DVFS = 41,
232 CCGR_QOS = 42,
233 CCGR_QOS_DISPMIX = 43,
234 CCGR_QOS_MEGAMIX = 44,
235 CCGR_CSU = 45,
236 CCGR_DBGMON = 46,
237 CCGR_DEBUG = 47,
238 CCGR_TRACE = 48,
239 CCGR_SEC_DEBUG = 49,
240 CCGR_SEMA1 = 64,
241 CCGR_SEMA2 = 65,
242 CCGR_PERFMON1 = 68,
243 CCGR_PERFMON2 = 69,
244 CCGR_SDMA = 72,
245 CCGR_CSI = 73,
246 CCGR_EPDC = 74,
247 CCGR_LCDIF = 75,
248 CCGR_PXP = 76,
249 CCGR_PCIE = 96,
250 CCGR_MIPI_CSI = 100,
251 CCGR_MIPI_DSI = 101,
252 CCGR_MIPI_MEM_PHY = 102,
253 CCGR_USB_CTRL = 104,
254 CCGR_USB_HSIC = 105,
255 CCGR_USB_PHY1 = 106,
256 CCGR_USB_PHY2 = 107,
257 CCGR_USDHC1 = 108,
258 CCGR_USDHC2 = 109,
259 CCGR_USDHC3 = 110,
260 CCGR_ENET1 = 112,
261 CCGR_ENET2 = 113,
262 CCGR_CAN1 = 116,
263 CCGR_CAN2 = 117,
264 CCGR_ECSPI1 = 120,
265 CCGR_ECSPI2 = 121,
266 CCGR_ECSPI3 = 122,
267 CCGR_ECSPI4 = 123,
268 CCGR_GPT1 = 124,
269 CCGR_GPT2 = 125,
270 CCGR_GPT3 = 126,
271 CCGR_GPT4 = 127,
272 CCGR_FTM1 = 128,
273 CCGR_FTM2 = 129,
274 CCGR_PWM1 = 132,
275 CCGR_PWM2 = 133,
276 CCGR_PWM3 = 134,
277 CCGR_PWM4 = 135,
278 CCGR_I2C1 = 136,
279 CCGR_I2C2 = 137,
280 CCGR_I2C3 = 138,
281 CCGR_I2C4 = 139,
282 CCGR_SAI1 = 140,
283 CCGR_SAI2 = 141,
284 CCGR_SAI3 = 142,
285 CCGR_SIM1 = 144,
286 CCGR_SIM2 = 145,
287 CCGR_UART1 = 148,
288 CCGR_UART2 = 149,
289 CCGR_UART3 = 150,
290 CCGR_UART4 = 151,
291 CCGR_UART5 = 152,
292 CCGR_UART6 = 153,
293 CCGR_UART7 = 154,
294 CCGR_WDOG1 = 156,
295 CCGR_WDOG2 = 157,
296 CCGR_WDOG3 = 158,
297 CCGR_WDOG4 = 159,
298 CCGR_GPIO1 = 160,
299 CCGR_GPIO2 = 161,
300 CCGR_GPIO3 = 162,
301 CCGR_GPIO4 = 163,
302 CCGR_GPIO5 = 164,
303 CCGR_GPIO6 = 165,
304 CCGR_GPIO7 = 166,
305 CCGR_IOMUX = 168,
306 CCGR_IOMUX_LPSR = 169,
307 CCGR_KPP = 170,
308
309 CCGR_SKIP,
310 CCGR_MAX,
311};
312
313
314enum clk_root_type {
315 CCM_CORE_CHANNEL,
316 CCM_BUS_CHANNEL,
317 CCM_AHB_CHANNEL,
318 CCM_DRAM_PHYM_CHANNEL,
319 CCM_DRAM_CHANNEL,
320 CCM_IP_CHANNEL,
321};
322
323#include <asm/arch/clock_slice.h>
324
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327
328
329
330struct clk_root_map {
331 enum clk_root_index entry;
332 enum clk_root_type type;
333 uint8_t src_mux[8];
334};
335
336enum enet_freq {
337 ENET_25MHZ,
338 ENET_50MHZ,
339 ENET_125MHZ,
340};
341
342u32 get_root_clk(enum clk_root_index clock_id);
343u32 mxc_get_clock(enum mxc_clock clk);
344u32 imx_get_uartclk(void);
345u32 imx_get_fecclk(void);
346void clock_init(void);
347#ifdef CONFIG_SYS_I2C_MXC
348int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
349#endif
350#ifdef CONFIG_FEC_MXC
351int set_clk_enet(enum enet_freq type);
352#endif
353int set_clk_qspi(void);
354int set_clk_nand(void);
355#ifdef CONFIG_MXC_OCOTP
356void enable_ocotp_clk(unsigned char enable);
357#endif
358void enable_usboh3_clk(unsigned char enable);
359#ifdef CONFIG_IMX_HAB
360void hab_caam_clock_enable(unsigned char enable);
361#endif
362void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
363void enable_thermal_clk(void);
364#endif
365
