LXR uboot/arch/arm/include/asm/arch-sunxi/dram_sun50i

   1/*
   2 * H616 dram controller register and constant defines
   3 *
   4 * (C) Copyright 2020  Jernej Skrabec <jernej.skrabec@siol.net>
   5 *
   6 * Based on H6 one, which is:
   7 * (C) Copyright 2017  Icenowy Zheng <icenowy@aosc.io>
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#ifndef _SUNXI_DRAM_SUN50I_H616_H
  13#define _SUNXI_DRAM_SUN50I_H616_H
  14
  15#include <stdbool.h>
  16#ifndef __ASSEMBLY__
  17#include <linux/bitops.h>
  18#endif
  19
  20enum sunxi_dram_type {
  21        SUNXI_DRAM_TYPE_DDR3 = 3,
  22        SUNXI_DRAM_TYPE_DDR4,
  23        SUNXI_DRAM_TYPE_LPDDR3 = 7,
  24        SUNXI_DRAM_TYPE_LPDDR4
  25};
  26
  27/* MBUS part is largely the same as in H6, except for one special register */
  28struct sunxi_mctl_com_reg {
  29        u32 cr;                 /* 0x000 control register */
  30        u8 reserved_0x004[4];   /* 0x004 */
  31        u32 unk_0x008;          /* 0x008 */
  32        u32 tmr;                /* 0x00c timer register */
  33        u8 reserved_0x010[4];   /* 0x010 */
  34        u32 unk_0x014;          /* 0x014 */
  35        u8 reserved_0x018[8];   /* 0x018 */
  36        u32 maer0;              /* 0x020 master enable register 0 */
  37        u32 maer1;              /* 0x024 master enable register 1 */
  38        u32 maer2;              /* 0x028 master enable register 2 */
  39        u8 reserved_0x02c[468]; /* 0x02c */
  40        u32 bwcr;               /* 0x200 bandwidth control register */
  41        u8 reserved_0x204[12];  /* 0x204 */
  42        /*
  43         * The last master configured by BSP libdram is at 0x49x, so the
  44         * size of this struct array is set to 41 (0x29) now.
  45         */
  46        struct {
  47                u32 cfg0;               /* 0x0 */
  48                u32 cfg1;               /* 0x4 */
  49                u8 reserved_0x8[8];     /* 0x8 */
  50        } master[41];           /* 0x210 + index * 0x10 */
  51        u8 reserved_0x4a0[96];  /* 0x4a0 */
  52        u32 unk_0x500;          /* 0x500 */
  53};
  54check_member(sunxi_mctl_com_reg, unk_0x500, 0x500);
  55
  56/*
  57 * Controller registers seems to be the same or at least very similar
  58 * to those in H6.
  59 */
  60struct sunxi_mctl_ctl_reg {
  61        u32 mstr;               /* 0x000 */
  62        u32 statr;              /* 0x004 unused */
  63        u32 mstr1;              /* 0x008 unused */
  64        u32 clken;              /* 0x00c */
  65        u32 mrctrl0;            /* 0x010 unused */
  66        u32 mrctrl1;            /* 0x014 unused */
  67        u32 mrstatr;            /* 0x018 unused */
  68        u32 mrctrl2;            /* 0x01c unused */
  69        u32 derateen;           /* 0x020 unused */
  70        u32 derateint;          /* 0x024 unused */
  71        u8 reserved_0x028[8];   /* 0x028 */
  72        u32 pwrctl;             /* 0x030 unused */
  73        u32 pwrtmg;             /* 0x034 unused */
  74        u32 hwlpctl;            /* 0x038 unused */
  75        u8 reserved_0x03c[20];  /* 0x03c */
  76        u32 rfshctl0;           /* 0x050 unused */
  77        u32 rfshctl1;           /* 0x054 unused */
  78        u8 reserved_0x058[8];   /* 0x05c */
  79        u32 rfshctl3;           /* 0x060 */
  80        u32 rfshtmg;            /* 0x064 */
  81        u8 reserved_0x068[104]; /* 0x068 */
  82        u32 init[8];            /* 0x0d0 */
  83        u32 dimmctl;            /* 0x0f0 unused */
  84        u32 rankctl;            /* 0x0f4 */
  85        u8 reserved_0x0f8[8];   /* 0x0f8 */
  86        u32 dramtmg[17];        /* 0x100 */
  87        u8 reserved_0x144[60];  /* 0x144 */
  88        u32 zqctl[3];           /* 0x180 */
  89        u32 zqstat;             /* 0x18c unused */
  90        u32 dfitmg0;            /* 0x190 */
  91        u32 dfitmg1;            /* 0x194 */
  92        u32 dfilpcfg[2];        /* 0x198 unused */
  93        u32 dfiupd[3];          /* 0x1a0 */
  94        u32 reserved_0x1ac;     /* 0x1ac */
  95        u32 dfimisc;            /* 0x1b0 */
  96        u32 dfitmg2;            /* 0x1b4 unused */
  97        u32 dfitmg3;            /* 0x1b8 unused */
  98        u32 dfistat;            /* 0x1bc */
  99        u32 dbictl;             /* 0x1c0 */
 100        u8 reserved_0x1c4[60];  /* 0x1c4 */
 101        u32 addrmap[12];        /* 0x200 */
 102        u8 reserved_0x230[16];  /* 0x230 */
 103        u32 odtcfg;             /* 0x240 */
 104        u32 odtmap;             /* 0x244 */
 105        u8 reserved_0x248[8];   /* 0x248 */
 106        u32 sched[2];           /* 0x250 */
 107        u8 reserved_0x258[180]; /* 0x258 */
 108        u32 dbgcmd;             /* 0x30c unused */
 109        u32 dbgstat;            /* 0x310 unused */
 110        u8 reserved_0x314[12];  /* 0x314 */
 111        u32 swctl;              /* 0x320 */
 112        u32 swstat;             /* 0x324 */
 113        u8 reserved_0x328[7768];/* 0x328 */
 114        u32 unk_0x2180;         /* 0x2180 */
 115        u8 reserved_0x2184[188];/* 0x2184 */
 116        u32 unk_0x2240;         /* 0x2240 */
 117        u8 reserved_0x2244[3900];/* 0x2244 */
 118        u32 unk_0x3180;         /* 0x3180 */
 119        u8 reserved_0x3184[188];/* 0x3184 */
 120        u32 unk_0x3240;         /* 0x3240 */
 121        u8 reserved_0x3244[3900];/* 0x3244 */
 122        u32 unk_0x4180;         /* 0x4180 */
 123        u8 reserved_0x4184[188];/* 0x4184 */
 124        u32 unk_0x4240;         /* 0x4240 */
 125};
 126check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
 127check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240);
 128
 129#define MSTR_DEVICETYPE_DDR3    BIT(0)
 130#define MSTR_DEVICETYPE_LPDDR2  BIT(2)
 131#define MSTR_DEVICETYPE_LPDDR3  BIT(3)
 132#define MSTR_DEVICETYPE_DDR4    BIT(4)
 133#define MSTR_DEVICETYPE_MASK    GENMASK(5, 0)
 134#define MSTR_2TMODE             BIT(10)
 135#define MSTR_BUSWIDTH_FULL      (0 << 12)
 136#define MSTR_BUSWIDTH_HALF      (1 << 12)
 137#define MSTR_ACTIVE_RANKS(x)    (((x == 2) ? 3 : 1) << 24)
 138#define MSTR_BURST_LENGTH(x)    (((x) >> 1) << 16)
 139
 140#define TPR10_CA_BIT_DELAY      BIT(16)
 141#define TPR10_DX_BIT_DELAY0     BIT(17)
 142#define TPR10_DX_BIT_DELAY1     BIT(18)
 143#define TPR10_WRITE_LEVELING    BIT(20)
 144#define TPR10_READ_CALIBRATION  BIT(21)
 145#define TPR10_READ_TRAINING     BIT(22)
 146#define TPR10_WRITE_TRAINING    BIT(23)
 147
 148struct dram_para {
 149        u32 clk;
 150        enum sunxi_dram_type type;
 151        u8 cols;
 152        u8 rows;
 153        u8 ranks;
 154        u8 bus_full_width;
 155        u32 dx_odt;
 156        u32 dx_dri;
 157        u32 ca_dri;
 158        u32 odt_en;
 159        u32 tpr0;
 160        u32 tpr2;
 161        u32 tpr10;
 162        u32 tpr11;
 163        u32 tpr12;
 164};
 165
 166
 167static inline int ns_to_t(int nanoseconds)
 168{
 169        const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
 170
 171        return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
 172}
 173
 174void mctl_set_timing_params(struct dram_para *para);
 175
 176#endif /* _SUNXI_DRAM_SUN50I_H616_H */
 177